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COSC 3330/6308 First Review Session

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COSC 3330/6308 First Review Session. Fall 2012. First Question. Simplify the following Boolean expression. w (v x y + y) +w' y + v w x + y. Answer. w (v x y + y) +w' y + v w x + y = v w x y + w y + w' y + v w x + y. v w x y + w y + w' y + v w x + y. Answer. - PowerPoint PPT Presentation
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COSC 3330/6308 First Review Session Fall 2012
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Page 1: COSC 3330/6308 First Review Session

COSC 3330/6308First Review Session

Fall 2012

Page 2: COSC 3330/6308 First Review Session

First Question

Simplify the following Boolean expression. – w (v x y + y) +w' y + v w x + y

Page 3: COSC 3330/6308 First Review Session

Answer

w (v x y + y) +w' y + v w x + y =v w x y + w y + w' y + v w x + y

Page 4: COSC 3330/6308 First Review Session

Answer

v w x y +w y + w' y + v w x + y

v'w' v'w vw vw'

x'y'

x'y

xy

xy'

Page 5: COSC 3330/6308 First Review Session

Answer

v w x y +w y + w' y + v w x + y

v'w' v'w vw vw'

x'y' 0 0 0 0

x'y 1 1 1 1

xy 1 1 1 1

xy' 0 0 1 0

Page 6: COSC 3330/6308 First Review Session

Answer

v w x y +w y + w' y + v w x + y

v'w' v'w vw vw'

x'y' 0 0 0 0

x'y 1 1 1 1

xy 1 1 1 1

xy' 0 0 1 0

Page 7: COSC 3330/6308 First Review Session

Answer

By Karnaugh maps:– v w x + y

By algebra:

– w (v x y + y) +w' y + v w x + y =v w x y + w y + w' y + v w x + y =y (v w x + w + w' + 1) + v w x =y + v w x

Page 8: COSC 3330/6308 First Review Session

Second Question

Give a simplified implementation for the following expression using only NAND gates.

– w' (x y) + w x y' + x' y'

Page 9: COSC 3330/6308 First Review Session

Answer

w' (x y) + w x y' + x' y' =w' (x' y + x y') + w x y' + x' y' =w' x' y + w' x y' + w x y' + x' y'

Page 10: COSC 3330/6308 First Review Session

Answer

w' x' y + w x y' + w' x y' + x' y'

w' x' + y'

x'y' x'y xy xy'

w' 1 1 0 1

w 1 0 0 1

Page 11: COSC 3330/6308 First Review Session

Answer

Using algebra:

– w' (x y) + w x y' + x' y' =w' (x' y + x y') + w x y' + x' y' =w' x' y + w' x y' + w x y' + x' y' =w' x' y + x y' (w' + w) + x' y' =w' x' y + x y' + x' y' =w' x' y + y' =w' x' y + w' x' y' + y' =w' x'( y + y') + y' = w'x' + y'

Page 12: COSC 3330/6308 First Review Session

Reminder

A NAND B = (A B)' = A' + B'

(NOT A) NAND(NOT B) ( A' B')' = A+ B

NOT(A NAND B) = (A B)'' = A B

(A NAND B) NAND (C NAND D) =((AB)' (CD)')' = AB + CD

Page 13: COSC 3330/6308 First Review Session

Answer

w'

x'

y

(w'x')' = w + x

((w + x)y)' = w'x' + y'

Page 14: COSC 3330/6308 First Review Session

Third Question (I)

What is the main reason for using a base plus displacement representation of memory addresses in an instructions set?

Page 15: COSC 3330/6308 First Review Session

Answer

What is the main reason for using a base plus displacement representation of memory addresses in an instructions set?

– To be able to access a very large address space with as few bits as possible in order to keep instructions as short as possible MIPS IS uses 5 bits to specify which register and

16 bits for the displacement

Page 16: COSC 3330/6308 First Review Session

Third Question (II)

What is the main reason for requiring all instructions to have the same length?

– To allow the CPU to fetch the next instruction before the current instruction is decoded Would not work if we had 16-bit and 32-bit

instructions

Page 17: COSC 3330/6308 First Review Session

Fourth Question

Assume we have a very basic microprocessor doing 4-bit arithmetic.

How would you represent the decimal value – 8 in signed arithmetic?

Page 18: COSC 3330/6308 First Review Session

Answer

How would you represent the decimalvalue – 8 in signed arithmetic?

– 1000

Page 19: COSC 3330/6308 First Review Session

Fourth question (II)

What would be its result of adding 0100 to 0101 assuming that the numbers being added were

Unsigned integers? Signed integers?

Page 20: COSC 3330/6308 First Review Session

Answer

What would be its result of adding 0100 to 0101 assuming that the numbers being added were

– Unsigned integers?– Signed integers?

0100 + 0101 = 1001– 1001 represents 9 in unsigned arithmetic– 1001 represents -7 in signed arithmetic

Page 21: COSC 3330/6308 First Review Session

Explanation

We use two complement's arithmetic– To change the sign of a positive value

Negate all its bits then add 1– To change the sign of a positive value

Negate all its bits then add 1 For 1001 we do

– not(1001) + 1 = 0110 + 1 = 0111 = 7

Page 22: COSC 3330/6308 First Review Session

Fifth question

Implement a two-bit counter going to the cycle 00, 01, 10, 11, 00, … when its input is on. You may use the flip-flops and the gates of your choice.

Page 23: COSC 3330/6308 First Review Session

Answer

Implement a two-bit counter going to the cycle 00, 01, 10, 11, 00, … when its input is on. You may use the flip-flops and the gates of your choice.

– How many flip-flops do we need?

Page 24: COSC 3330/6308 First Review Session

Answer

Implement a two-bit counter going to the cycle 00, 01, 10, 11, 00, … when its input is on. You may use the flip-flops and the gates of your choice.

– How many flip-flops do we need? Two because we have 22 =4 states

Page 25: COSC 3330/6308 First Review Session

Answer

Implement a two-bit counter going to the cycle 00, 01, 10, 11, 00, … when its input is on. You may use the flip-flops and the gates of your choice.

– How many flip-flops do we need? Two because we have 22 =4 states

Page 26: COSC 3330/6308 First Review Session

Answer

Draw the Karnaugh maps for these flip-flops:

– Least significant bit y

x'y' x'y xy xy'

i

i'

Page 27: COSC 3330/6308 First Review Session

Answer

Draw the Karnaugh maps for these flip-flops:

– Least significant bit y

x'y' x'y xy xy'

i' 0 1 1 0

i 1 0 0 1

Page 28: COSC 3330/6308 First Review Session

Answer

Draw the Karnaugh maps for these flip-flops:

– Most significant bit x

x'y' x'y xy xy'

i'

i

Page 29: COSC 3330/6308 First Review Session

Answer

Draw the Karnaugh maps for these flip-flops:

– Most significant bit x

x'y' x'y xy xy'

i' 0 0 1 1

i 0 1 0 1

Page 30: COSC 3330/6308 First Review Session

Answer

The system equations are – y = y i– x = x iy = x(i' + y') + x' iy

Page 31: COSC 3330/6308 First Review Session

Answer

We will use T flip-flops for x and y– y will be triggered by input i– x will be triggered by input iy

Page 32: COSC 3330/6308 First Review Session

Answer

Page 33: COSC 3330/6308 First Review Session

Sixth Question (I)

Which decimal values are stored in the following single precision floating point numbers?

1 129 010000000000000000000000000…

0 124 10000000000000000000000000…

Page 34: COSC 3330/6308 First Review Session

Sixth Question (II)

Sign is negative Exponent is 129 -127 = 2 Coefficient is 1.01two = 1 + ¼ - (1 + ¼) 22 = -5

1 129 0100000000000000000000000000…

Page 35: COSC 3330/6308 First Review Session

Sixth Question (III)

Sign is positive Exponent is 124 – 127 = -3 Coefficient is 1.1two = 1+ ½ = 1.5 1.5 2-3 =1.5/8 = 3/16

0 124 10000000000000000000000000…

Page 36: COSC 3330/6308 First Review Session

Seventh Question

Multiply the two following floating-point numbers:

1 129ten 000000000000000000000 …

0 129ten 000000000000000000000 …

Page 37: COSC 3330/6308 First Review Session

Answer

Multiply the two following floating-point numbers:

– Compute the new sign– Add the exponents– Multiply the coefficients

1 129ten 000000000000000000000 …

0 129ten 000000000000000000000 …

Page 38: COSC 3330/6308 First Review Session

Answer

Multiply the two following floating-point numbers:

– Compute the new sign: Negative– Add exponents: (129 – 127) + (129- 127)– Multiply the coefficients: 11

1 129ten 000000000000000000000 …

0 129ten 000000000000000000000 …

Page 39: COSC 3330/6308 First Review Session

Answer

Result is -1 24

– Sign bit is 1– Biased exponent is 127 + 4 =131– Coefficient is 1

1 131ten 0000000000000000000000…


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