Cross Talk Details and Routing

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Minimisation of crosstalk

in VLSI

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Presented By: Subhradeep Mitra

Ankita Dutta

Paramita Sau

Debanjana Biswas

(Mca Students of Rajabazar sc. College)


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Outlines

VLSI DESIGN CYCLE

PHYSICAL DESIGN CYCLE

ROUTING

PHASES OF ROUTING

CROSSTALK OVERVIEW

EFFECT OF CROSSTALK

HOW TO MINIMIZE CROSSTALK

HOW TO PREVENT CROSSTALK

CONCLUSION

REFERENCES


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VLSI Design Cycle

The VLSI design cycle starts with a formal specification of a VLSI chip

follows a series of steps, and eventually produces a packaged chip

The steps included into the VLSI Design Cycle are as follows :

System Specification

Architectural Design

Behavioral or Functional Design Logic Design

Circuit Design

Physical Design

Fabrication

Packaging, Testing and Debugging


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Physical Design Cycle

The input of the physical design cycle is a circuit diagram and the output is

the layout of the circuit. This is accomplished in several stages. The stages arefollowing:-

1) Partitioning2) Floorplanning and Placement3) Routing4) Compaction5) Extraction and verification


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Routing

The Routing is to locate a set of wires in the routing space that connect all the nets inthe net list.The capacity of channels width of wires, and wire crossing often need to

be taken into consideration.

Problem :

Input :

Netlist

Timing budget for typically critical nets

Placement information including location of blocks, location of pins in

the block boundary, location of the I/O pins on the chip boundary etc.

Output :

Geometric layouts of all nets


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Objectives of Routing:

Minimize the total wire length

Minimize the no of layers ( fewer layer is less expensive)

Minimize the no of vias,bends i.e. completing all connection without

increasing the chip area

Minimize the crosstalk


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PHASES OF ROUTING:-

Routing

Global Routing Detailed Routing

Line Routing Maze Routing ChannelRouting

Switch BoxRouting


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Global Routing:- .

Its the first phase of routing and generates a loose route for each net.

Minimize the total wire length

Minimize running time

The global routing considers the entire layout.

This routing consists of three distinct phases-

i. Region Definition

ii. Region Assignment

iii. Pin Assignment

Global Routing


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Detailed Routing:-

Its the second phase, of routing to finds the actual geometric layout of

each net within the assigned routing regions.

Three types of detailed routing methods:-

i) Channel Routing

ii) 2-D Switchbox Routing

iii) 3-D Switchbox Routing

Channel Routing 2-D Switchbox 3-D switchbox

If the switchbox or channels are unroutable without

a large expansion, global routing to be done again

Detailed Routing


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Crosstalk

1. Mutual inductance (magnetic field)

2. Mutual capacitance (electric field)

Definition :

The electromagnetic coupling of a signal from one conductor to

another is called as crosstalk

Crosstalk can be classified into the following two types:


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1. Mutual Inductance :

Mutual inductance Lm

induces current from a driver line onto a

quiet line by means of the magnetic field.

The mutual inductance Lm

will inject a voltage noise onto thevictim proportional to the rate of change of the current on thedriver line. The magnitude of this noise is calculated as


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Due to the recent trends of higher aspect ratios and lower spacingbetween signal lines, the coupling capacitance is becomingsignificant. Also the vertical height has not been scaled down .

2. Mutual Capacitance:-


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If one line is switching and the other line is steady the energy transfer

through the coupling capacitance results in a glitch on the quiet line

The inductively induced voltages were generally negligible compared to theeffects of the parasitic capacitances of the interconnect lines.

The interconnect capacitance is modeled as Mutual Capacitance.

d(Vvictim Vdriver)

dt


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Crosstalk induced noise:

Crosstalk is the result of mutual capacitance Cm inconjunction with mutual inductance Lm between adjacentconductors.

For simplicity and for measuring the magnitude of noiseinduced on to the adjacent transmission lines we have toconsider the two terms :

Near-end-crosstalk Far-end-crosstalk


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The currentgenerated on thevictim line due to

mutual capacitancewill split and flowtoward both ends ofthe adjacent line.

The currentgenerated on thevictim line due tomutual inductancewill flow from the farend toward the nearend of the victim line

As a result, the crosstalk currents flowing toward the near and far ends canbe broken down into several components:

Near end crosstalk is always positive

Far end crosstalk is always negative


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Effects of Crosstalk:

Signal Integrity Illustration

Noise on Delay effect

Destroying Local Information

Timing Noise


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1. Signal Integrity Illustration:

The term Signal Integrity (SI) addresses two concerns in the electricaldesign aspects the timing and the quality of the signal. Due to crosstalk:

the signal doesnt reach its destination when it is supposed to

when it gets there, it is not in good condition


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2. Noise on delay effect

Depending on the signal switching directions of the signals on the driverand victim nets, the impact of interconnect cross-talk can be either,

negative (increasing signal propagation time)positive (decreasing signal propagation time), which may cause setup-or hold-time violations.


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3. Destroying local information:

When noise acts against a normally static signal, it can destroy the localinformation carried by the static node in the circuit and ultimately result inincorrect machine-state stored in a latch.

4. Timing noiseThis includes the noise by,

Skew that is the DC components of the noiseJitter that is the AC components of the noise


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Basic Approaches in Crosstalk Avoidance

Segregation / Spacing / Ground Shielding

Net Ordering

Layer Assignment


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Noi sy

Regi on

Qui et

Regi onSegr egat i on Spaci ng

Ext r a

space

Segregation / Spacing/ Ground Shielding (1)


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Segregation / Spacing/ Ground Shielding (2)

Segregation : Dividing many (noisy)and less(quiet) signal transition wireand merging group by group.(use withshielding)

Spacing : Spacing can be of two types:

Increasing line spacing capacitivecoupling can be decreased. Widening metal wires decrease the

effect of capacitive coupling byincreasing the line to groundcapacitance to the total capacitanceratio.

Shielding : blocking signal line withground line to minimize signalinterference to the other wire.(groundbounce occurs and must broaden theground line)

Shielding type 1

Shieling type 2


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Net Ordering

Left : Unorderedtrackpermutation

Right : Orderedtrackpermutation forminimizingcrosstalk

SS

SS

LL

LL

LL

SS

SS

LL

LL

LL

Net ordering is used for minimize crosstalk-critical region

between each lines. When, long line and long line is close

together, crosstalk between them is more larger than long

line and short line. So, we must change the permutation of

track for minimizing crosstalk.


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Layer Assignment

Or dered netLayer 1

Unoder ed net

Layer 2

Layer 3

When using more than 3 layer in channel routing, adjacentsignal wire in same layer results crosstalk. For example, leftfigure makes more crosstalk than right.

Layer assignment problem is solved by integer linearprogramming or dynamic programming method.


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Minimize Crosstalk: Rule of Thumb

Widen spacing S between the lines as much as routing restrictions will allow

Minimize H while achieving the target impedance of the design

Use differential routing techniques for critical nets


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Routing adjacent layers orthogonal if there is significant inter layer

coupling

If possible routing the signals on a strip layer or as an embedded micro-

strip to eliminate velocity variation

Minimize parallel run lengths between signals, routing with short parallelsections and minimize long coupled sections between nets

If possible, use slow edge rates (with extreme caution on timing

uncertainty)


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Recently FinFET is used instead of CMOS in VLSI because, FinFET canbe significantly more power efficient than CMOS at the same gatelength.

Conclusion :

Future scope :

NP-hard problem

Optimal solution are taken because some otherconstraints are there like wire length and congestion


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References :

Algorithms for VLSI Physical design Automation by Naveed

Sherwani

VLSI Design Automation Kia Bazragar

J.J.Xiong & L.He.IEEE Transon CAD, 2008

US PATIENT, PATINENT NO : US 6, 218, 631B1


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Cross Talk Details and Routing

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