CS-266 Project Section 1 and 2

10/19/2012

Arithmetic Logic Unit

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Contents Part 1a: 8 Bit Multiplexer ........................................................................................................................ 2

Specifications ...................................................................................................................................... 2

1-Bit 4:1 Multiplexer ........................................................................................................................... 2

8 Bit 4:1 Multiplexer ........................................................................................................................... 3

Testing ............................................................................................................................................. 5

Part 1b: 8-bit full adder ........................................................................................................................... 6

Specifications ...................................................................................................................................... 6

• 8-bit full adder, using a 1-bit full adder as a subdesign component. .............................................. 6

1 Bit Full Adder .................................................................................................................................... 6

8 Bit Full Adder .................................................................................................................................... 7

Testing ................................................................................................................................................. 8

Part 2: Arithmetic Logic Unit (ALU) ......................................................................................................... 9

Specification ........................................................................................................................................ 9

8 Bit Logic Circuit ................................................................................................................................. 9

8 Bit Arithmetic Circuit ...................................................................................................................... 12

Testing ........................................................................................................................................... 16

Reference .............................................................................................................................................. 18

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Part 1a: 8 Bit Multiplexer

Specifications 4:1 multiplexer with 8-bit input and output (8-bit 4:1 multiplexer). This multiplexer uses a

subdesign component, the 1-bit 4:1 multiplexer.

1-Bit 4:1 Multiplexer This schematic is reused from a previous project (mini-project). Depending on the values of

s0 or s1, a different input (in0 – in3) is routed to the output.

This component will work correctly inside the 8-bit multiplexer by the principle of induction.

Input: s0, s1, in0, in1, in2, in3

Output: OUT

1-bit 4:1 multiplexer schematic

1-bit 4:1 multiplexer as subdesign

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8 Bit 4:1 Multiplexer Uses eight 1-bit 4:1 multiplexers as subdesigns. The eight subdesign multiplexers share two

select inputs, four expanders, a merger, four 8bit inputs one 8bit output, and two single bit inputs

for selectors.

Input: 8Bit_Input_0, 8Bit_Input_1, 8Bit_Input_2, 8Bit_Input_3, Sel_0, Sel_1

Output: OUT

1-bit 4:1 multiplexer testing from previous project

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This multiplexer does not need four select inputs or two select inputs with a 2 to 4 decoder

since the decoder function is built into each multiplexer.

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Testing

To test the 8-bit multiplexer, I will activate several input and select combinations, and then

show the appropriate waveform. The basic combinations should be the same as those of the 1-bit

multiplexer. Rather than exhaustively test all 64 basic permutations, I will use various combinations

from the truth table:

Because of these tests and the evidence gathered, I conclude that the circuit works

correctly.

input0 input1 input2 input3 s0 s1 OUT Expected Out

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0

0 0 0 0 1 1 0 0

0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0

0 0 0 1 1 0 0 0

0 0 0 1 1 1 1 1

0 0 1 0 0 0 0 0

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Part 1b: 8-bit full adder

Specifications

• 8-bit full adder, using a 1-bit full adder as a subdesign component.

1 Bit Full Adder To build the 8-bit adder, I first made a 1-bit half adder from the truth table in the textbook.

Then added two half adders together to create the full adder.

Input: In_0, In_1, C_in

Output: Sum, C_out

Truth Table for 1-bit full adder

X(input0) Y(input1) Z(input2) C(carry) S(sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

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1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-map for 1-bit full adder: carry

Color-coded for ease of understanding

X\YZ 00 01 11 10

0 1

1 1 1 1

K-map for 1-bit full adder: sum

Also color coded.

X\YZ 00 01 11 10

0 1 1

1 1 1

8 Bit Full Adder I used the 1-bit full adder as a subdesign for the 8-bit adder. The C_out is connected to the

most significant bit, and will display when the circuit overloads. The extra input would then become

a C-in, and the extra output would become a C-out, and then carried bits could be transferred

between the subdesigns, much like a ripple-type adder shown in the book.

Input: 8Bit_Input_0, 8Bit_Input1, Cin

Output: Sum, C_out

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The eight 1-bit full adders accept three input bits from each of the input busses. If the input

bus 0 carries the signal 00000001, then 1-bit_adder0 will have its input0 port activated. The rest of

the adder subdesigns work this way. The proper output is routed to the appropriate bus.

Testing The 1-bit full adder will be tested first, as it is a component in the 8-bit adder.

X(input0) Y(input1) Z(input2) C(carry) S(sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

The waveform matches the truth table, so the 1-bit full adder works correctly. The purple

box is the operation 0 + 1 + 1, which has sum 0 and carry 1. The orange box is 0 + 0 + 1, which has

carry 0 and sum 1.

If two of three inputs are 1, then the sum is 0, and the carry is 1. If all three inputs are 1,

then both the sum and the carry are 1. If only one input is 1, then the sum is 1 and the carry is 0.

The 8-bit adder would work in the same way as the 1-bit adder, only there would be more

permutations of input and output possible, due to the extra bits. To test the 8-bit adder, I will

perform basic arithmetic operations and show the resulting waveform with the proper output.

1-bit full adder as a subdesign

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The black box is the operation 1 + 0 + 0, which has sum 1 and carry 0. The red box is 1 + 1 +

0, which has sum 0 and carry 1. And lastly, the blue box is 1 + 1 + 1, which has sum 1 and carry 1.

Due to the accurate nature of these results, I conclude that my circuit works correctly.

Part 2: Arithmetic Logic Unit (ALU)

Specification

8 Bit Logic Circuit The logic circuit seems pretty straight forward, the hardest part will be figuring out

how to select it. For this we decided to go with an 8 bit 4 to 1 multiplexor, previously

designed and tested, to select the proper logic function. Implementing the logic circuit was

more difficult than initially expected. We realized that the logic circuit would be taking 8 bits

and created our 8 bit logic circuit. This was done by first creating the single bit logic circuit

shown bellow.

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Shown below is the circuits subdesign.

Then implemented the single bit logic circuit eight times to create our 8 bit logic

circuit. The design was drawn with diagonal lines for clarity of the connections.

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The 8 bit logic circuit was then added to an 8 bit 4 to 1 multiplexer to select which of

the logic outputs to use. At this point we were were expecting to use a 3 bit decoder for the

selection of the logic and arithmetic circuit, but decided to use two 8 bit 4 to 1 multiplexers

and an 8 bit 2 to 1 multiplexer for the selector. Mainly because a decoder would ad more

gate cost to the circuit.

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8 Bit Arithmetic Circuit

The arithmetic circuit required four different components. We used our 8 bit For the

arithmetic we only need B in two separate cases, therefore we will omit B for the 2

cases it is not required for. The two cases that do use B are the 8 bit adder, and the

8 bit adder with the notB case. Since the 8-bit adder has already been tested it will

not be required to test it for this experiment. Two of the 8 bit full adders where used

in the arithmetic circuit.

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For the arithmetic so far we decided to use an 8 bit inverter for the not B and then a

previously created 8 bit adder for the A + B + C_in. The 8 bit inverter is straight

forward, it simply inverts all of the bits coming into this circuit.

For a minus 1 we need to use a decrement or and add a C in, figuring this out next,

followed by using A plus a Cin. So increment by C. For the incremented, we thought

we might just use a modified version of our 8 bit adder. Our multiplexor did not fit

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what we needed for 8 inputs, need to make a change in the encoder and multiplexor.

For the decrement or, some form of modified adder/subtractor might be used.

Decrementer, thinking of adding a vcc circuit to always output one, then connect that

to our 8 bit adder to act as a -1 decrementer. Making a custom part, 8 bit vcc to input

onto our old 8bit adder, removing the B input. Replaced the 8 bit B with our 8 bit

VCC. Last part now works.

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We also needed an incrementer that would increment the value of the input by

C. This was done by using 8 half adders and inputting the C value into the input_0

would go. Then each Carry would increase the and increase the over all value of the

input by C. This was a new circuit and testing is shown in the testing section of part

2.

We decided to use an 8 bit 4 to 1 multiplexer for deciding which input to output from

our arithmetic circuit. And a 1bit 4 to one multiplexer for our C_out or V_out. Only

one of the previously mentioned outputs would be output depending on the inputs.

The circuit worked as desired and was used in our final arithmetic logic unit.

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Finally, we have our arithmetic logic unit (ALU) shown bellow, utilizing the

logic circuit and arithmetic circuit from above. We utilized an 8bit 2 to 1 multiplexer

as a means of selecting which of the two circuit outputs to use. C_out and V_out will

also have their separate Circuits.

Testing

Since the decrementer was a new device we created, we tested it to show that it would

indeed decrease the input by one. Our tests showed that it did have the behaviour we expected, and

would serve the function of our circuit.

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The Incrementer was also one of our new devices, hence we had to test it out.

The incrementer was meant to increase by a value of C and with C activated the

value of the incrementer increased as can be seen from our table below.

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Reference Mano, M. M., & Kime, C. R. (2008). Logic Computer Design Fundamentals.

New Jersey: Pearson Prentice Hall.