CSE241 VLSI Digital Circuits Winter 2003 Lecture 03: ASIC ... · Lecture 03: ASIC Flow and Design...

CSE241 L3 ASICs.1 Kahng & Cichy, UCSD ©2003

CSE241VLSI Digital Circuits

Winter 2003

Lecture 03:ASIC Flow and Design Convergence


This Class + Logistics

Overview of flow (preparation for Smith Chapters 12-17)

Read: Smith Chapter 12 (Synthesis), 13.7 (Static timing)

Lab #1 revised due date: Monday January 20

Near-term schedule:Ben has reserved the lab (EBU I, Room 3329) for this Friday, January 17, noon-1:20pm a running start into synthesis

Recitation #2 tomorrow (noon-12:50pm): not on RTL design, but on datapaths and memories

Lab tomorrow (3:30-5pm): really Lab #1

Slide courtesy of S. P. Levitan, U. Pittsburg


Review

Scaling of gates vs. Scaling of wiresWhat happens when you make a gate bigger?

What happens when you make a wire taller? Wider?

Coupling

InductanceHow does power/ground distribution affect inductance?

RC delay

Dynamic (useful) power vs. Static (useless) power

How do these issues impact estimates and design approaches?



OutlineDesign types and cost / complexity drivers

Basic flow

On convergence and hierarchy


IC Design MethodologiesFull-Custom (high effort, leading-edge performance, high-volume)

Semi-Custom (strong infrastructure, economical in lower volumes)ASIC (Application-Specific Integrated Circuit)

COT (Customer-Owned Tooling)

ASIC vs. COT: “Who pays for the scrap?”

FPGA

System-on-a-ChipLarger components, often from outside of design team

SpecialAnalog (custom layout, I/Os and sense amps)

Mixed-Signal / RF (unique to each process, no scaling)



Acceleration of Gate Length Scaling

What are some implications?•Slide courtesy of Numerical Technologies, Inc.


Mask NRE Cost (1999)

“$1M mask set” in 100nm, but average only 500 wafers per set


Design Technology Crises, ITRS-2001

Manufacturing

NR

E C

ost

SW Design

Verification

HW Design

TestTu

rnar

ound

Tim

eManufacturing

Incremental Cost Per Transistor

2-3X more verification engineers than designers on microprocessor teams

Software = 80% of system development cost (and Analog design hasn’t scaled)

Design NRE > 10’s of $M manufacturing NRE $1M

Design TAT = months or years manufacturing TAT = weeks

Without DFT, test cost per transistor grows exponentially relative to mfg cost


Silicon Complexity ChallengesSilicon Complexity ChallengesSilicon Complexity = impact of process scaling, new materials, new device/interconnect architectures

Non-ideal scaling (leakage, power management, circuit/device innovation, current delivery)

Coupled high-frequency devices and interconnects (signal integrity analysis and management)

Manufacturing variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools)

Scaling of global interconnect performance (communication, synchronization)

Decreased reliability (SEU, gate insulator tunneling and breakdown, joule heating and electromigration)

Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost)


System Complexity ChallengesSystem Complexity ChallengesSystem Complexity = exponentially increasing transistor counts, with increased diversity (mixed-signal SOC, …)

Reuse (hierarchical design support, heterogeneous SOC integration, reuse of verification/test/IP)

Verification and test (specification capture, design for verifiability, verification reuse, system-level and software verification, AMS self-test, noise-delay fault tests, test reuse)

Cost-driven design optimization (manufacturing cost modeling and analysis, quality metrics, die-package co-optimization, …)

Embedded software design (platform-based system design methodologies, software verification/analysis, codesign w/HW)

Reliable implementation platforms (predictable chip implementation onto multiple fabrics, higher-level handoff)

Design process management (team size / geog distribution, data mgmt, collaborative design, process improvement)



Basic flow


CSE241 L3 ASICs.12 Kahng & Cichy, UCSD ©2003Sylvester-Keutzer, Computer Nov. 99

Sylvester-Keutzer: Classic PictureSylvester-Keutzer: Classic Picture


Test Generation

Design Verification Timing Verification

Simulation Floorplanning

Logic PartitioningDie Planning

LogicSynthesis

Logic Design andSimulation

Behavioral Level Design

Global Placement

Detail Placement

Clock Tree Synthesisand Routing

Global Routing

Detail Routing

Power/Ground Stripes, Rings Routing

Extraction and Delay Calc.

Timing Verification

LVSDRCERC

IO Pad Placement

Traditional Flow

Front End

Back End


Fnl. Design

Synthesis

Clock distribution

Design Specs

Lib.+CWLMConstraints

Route, scan re-order

Timing analysis, IPO

ERC, DRC, LVS

Tape-out

Fnl., pwr., SI ECO

Reqmts.

Floor-plan & PGLib.+CWLM

Placement

• Architectural optimization (timing)• Inter-group buses, bandwidth• Clock, SI, test; validation

• Row definitions• Placement of cells• Congestion analysis

• Full RC back-annotation• Hierarchical timing, electrical and

SI analysis and IPO/ECO

• Floorplanning and custom WLM• Power distribution (Internal, I/O)• I/O driver, padring design• Board-level timing, SI

• Placement-based re-synthesis• Noise minimization, isolation • Clock distribution

• Full routing• Scan stitching, re-ordering

Physical re-synth

Block-Level Design Methodology

A. Khan, Simplex/Altius


Generic Flow StepsPreparation

Library data preparation

Design data preparation

Logic designSpecification to RTL

RTL simulation

Hierarchical floorplanning

Synthesis

Formal verification

Gate level simulation

Static timing analysis

Physical design•Physical floorplanning

•Place and route

•RC extraction

•Formal verification

•Physical verification

•Release to manufacturing

Design for test

Engineering change order


Library and Design Data

Models and technology data required to execute the design flow

Power, timing: ALF, DCL, OLA, .lib, STAMP

Layout: LEF, DEF, GDSII

Delays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF, SPEF, SPICE

Layout rules: Dracula, Calibre “deck”


Specification to RTLDefines the logic and fundamental structure of the chip at the RTL level in either the verilog or VHDL language

Requires considerable interaction with the customer, plus specs such as the architecture, system, design, test and block specs

May include RTL from the customer or third party IP providers

Coding guidelines should be established and adhered to, and the code must be compatible with the chosen synthesis tool

Special design considerations such as multiple clock frequencies, asynchronous logic, high speed logic, race conditions, gated clocks, etc. must be addressed


RTL Simulation

RTL code, written in Verilog, VHDL or a combination of both, is simulated to verify functional correctness

Testbenches apply input stimulus to the design

Several methods are used to verify the outputsSelf-checking testbenches automatically verify output correctness andreport mismatches

Results can be stored in a file and compared to previous results

Waveform displays can be used to interactively verify the outputs

Verification-specific tools: Verisity Specman, Synopsys Vera

Functional verificationMostly Modelsim

Cadence’s Verilog-XL or NC-Verilog also used


Hierarchical FloorplanningDecide on the physical layout strategy—flat or hierarchical?Advantages of a flat implementation are generally a smaller die size, and a more straightforward approach to clock and power distribution and RC generationAdvantages of a hierarchical design

better runtimes, better ability to control timing within localized areas of the design, and concurrent design

For hierarchical design, issues physical partitioning of the logic into blocksassignment of the physical locations for the block pinstiming budgeting, distribution of clocks, powersignal bus routingRC generation

Tool Example: Cadence’s design planner


FloorplanningGive placement initial clues

Cells that are interconnected want to be close togetherTake advantage of RTL hierarchyGenerate a physical hierarchyRTL hierarchy = best physical hierarchy?

Place big blocks on chip (memories)

Allow space for power/clk/busses

Reduce complexity of placement


SynthesisConversion of RTL to gate level netlist

Target foundry specific library

Timing driven methodologyclock informationinput arrival times, output required timesInput driving cells, output loadingFalse paths, multi-cycle paths

Interconnect delay is calculated based on a wireload model which uses fanout to calculate delay

Clocks parameters (insertion delay, skew, jitter, etc.) Are assumed to be attainable later in place and route


Synthesis …contd.

Hierarchical synthesisBlock-by-block basis

Minimizes runtimes

Functional blocks

Tools:Cadence Buildgates

Synopsys Design Compiler (used for this course)


Formal VerificationRTL description and gate level netlist are compared to verify functional equivalence, thereby verifying the synthesis results

An emerging technology that supplements the more traditional approach of gate level simulation

Tools:Verplex Tuxedo-lec Design Verifier (Chrysalis), Mentor FormalPro Synopsys Formality (will be used in-class)


Gate Level SimulationAnother method to verify the synthesis process, which covers both the functionality and timing

Correctness is only as good as the test vectors that are usedEspecially critical for non-synchronous designs, verification of false path and multi-cycle path constraints

Cell timing is included in the simulation models and interconnect delay is passed from the synthesis run

Worst case PVT conditions are used to analyze for setup violations, and best case PVT conditions are used to analyze for hold violations

PVT = Process, Voltage, Temperature

Popular tools are Cadence’s Verilog-XL or NC-Verilog


Static Timing AnalysisVerifies that design operates at desired frequency

Implicitly assumes correct timing constraints (!), e.g., boundary conditions

Timing constraints are similar to those used in synthesis

Verifies setup and hold times at FF inputs; can also check timing from and to PI’s and PO’s; can also check point-to-point delay values (with blocking of pins, etc.)

As with gate-level simulation, both best- and worst-case analysis is performed

Typically performed on full-chip (not block) basisMay require modified constraints for inter-block issues: multiple clock domains, multi-cycle paths, etc.

For compatibility with timing-driven layout flow, helps to have simple / single set of constraints

Other issues: incremental analysis, …


Physical FloorplanningDefines the basic chip layout architecture

Define the standard cell rows and I/O placement locations

Place rams and other macro cells

Define power bus structures such as power rings and stripes

Often performed using the standard place and route tool

Rules of thumb for cell density are used to initially calculate design size

Popular standalone tools are Cadence’s design planner and avanti’s planet


Place and RouteAutomatically place the standard cells

Generate clock trees

Add any remaining power bus connections

Route clock lines

Route signal interconnects

Design rule checks on the routes and cell placements

Timing driven toolsRequire timing constraints and analysis algorithms similar to those used during the static timing analysis step

Tools: Cadence Silicon Ensemble, Synopsys Apollo, Magma Blast Fusion


RC ExtractionCalculates the resistance and capacitance of interconnects

Based on placement of cellsRouting segments

Calculates capacitive effects of adjacent segments Extracts capacitance between metal segments

RC data is transferred to Static timing analysis (back annotation)Gate level simulationReplaces wire load model used in synthesis

Tools used:Cadence Hyperextract , Magma’s Blast FusionSequence Columbus, Synopsys Star-RC, Mentor X-Calibre


Signal Integrity

SICrosstalk issuesInductanceInterference

Need new toolsCalculate and estimate SINew delay models with SI estimatesSI aware routing


Formal Verification

Compares golden netlist to current netlistLogic equivalence

Comparison of pre- and post-layout netlistSimilar to the formal verification step after synthesis; clock tree insertions, drive strength changes, etc. have been made

Buffer insertion or logic optimization may have been performed


Physical VerificationDRC – Design Rule Check

Polygon/Layer spacing rulesVerifies the design rules (DRC)

LVS – Layout Versus SchematicVerifies that layout and netlist are equivalent at the transistor level

Antenna Manufacturing check for long netsNet can accumulate charge during plasma etch and damage gate oxide

GDSIIFinal merge of layout, routing and placement data for mask production

Example tools:Mentor Graphics Calibre (DRC, LVS)Cadence Dracula, Diva


Release to ManufacturingFinal edits to the layout are madeMetal fill and metal stress relief rules are checkedManufacturing information such as scribe lanes, seal rings, mask shop data, part numbers, logos and pin 1 identification information for assembly are also addedDRC and LVS are run to verify the correctness of the modified database‘Tapeout’ documentation is prepared prior to release of the GDSII to the foundryPad location information is prepared, typically in a spreadsheetCadence’s Virtuoso is used for custom-manual edits of the mask layersManufacturing steps

generation of maskssilicon processing wafer testingassembly and packagingmanufacturing test



Basic flow


•Yesterday 1000nm • Today 130nm • Tomorrow 50nm •Evolution of Design Flow

•Functional•Performance

•Testability•Verification

•SPEC

•Hw/Sw•SW•Logic•Circuit•Place•Wire•other

•Perf.•Timing•Power•Noise•Test•Mfg.•other

•Repository

•Hw/Sw•Data

•Model

•Optimize •Analyze•Comm.

•Cockpit

•Auto-Pilot

•EQ

check

•MASKS

•System •Design

•System •Model

•Perf.•Model

•System •Design

•System •Model

•File

•Synthesis•+ Timing Analysis•+ Placement Opt

•File

•Place/Wire•+ Timing Analysis

•+ Logic Opt

•SW •Opt

•Performance•Testability•Verification

•Functional•Verification

•MASKS

• RTL•SW

•Equivalence checking

•Hw/Sw•Optimization

•Multiple design files are converged into one efficient Data Model•Disk accesses are eliminated in critical methodology loops•Verification of Function, Performance, Testability and other design •criteria all move to earlier, higher levels of abstraction followed by

•equivalence checking and•assertion driven design optimizations

•Industry Standard interfaces for data access and control•Incremental modular tools for optimization and analysis•

•Logic •Design

•Software •Design

•Functional•Verification

•Performance•Verification•File

•Timing Analysis

•File

•Place/Wire

•File

•Synthesis

•File

•Timing Analysis

•RTL

•MASKS

•System •Design

•Testability•Verification


Gate-Level Place & Route

Gate-Level Optimization

DesignConstraintsIP BlocksLibrary

Top-Level Routing

RC Extraction

Timing Analysis

Early Planning

Design Refinement

Chip Assembly

PREDICTABLE HIERARCHICAL DESIGN CONVERGENCE

ARISTO TYPICAL DESIGN FLOW

DesignNetlist

Gate-LevelVerilog

RTL Verilog

Hard Blocks

Concurrent Block Partitioning, Clustering & Placement

Block Shaping, Compaction &Concurrent Port Placement

ConcurrentBlock

Synthesis

Aristo, DAC-2000


GDSII

Timing

Route

Place

logic

Physical Prototyping

IncreasingModeling

Detail

Design Signoff

timing librarystatistical WLM

Behavioral / RTL synthesis

RTL

Monterey, DAC-2000


Design ClosureInput

RT-level HDL + technology + constraints

Output“go”: recipe for invocation and composition of SP&R results“no go”: diagnosis of RTL code problems

Logical and physical hierarchies co-evolvespatial: top-down coarse placement physical hierarchylogic/timing: implementable RTL logical hierarchylimits of human fanout, organizations always have hierarchy

- Have seen a natural sequence of no-floorplanning, physical-floorplanning, RTL-floorplanning... as chip complexities increase

Details (must construct, predict, ignore, eliminate, ...)pin optimizations, interconnect planning, hierarchy reconciliations, budgeting mechanisms, compatibility with downstream SP&R, ...


Logical and Physical HierarchiesTwo hierarchies: logical/functional, and physical

(schematic hierarchy also typical in structured-custom)

RTL design = logical/functional hierarchyprovides valuable clues for physical embedding: datapath structure, timing structure, etc.can be incredibly misleading (e.g., all clock buffers in a single hierarchy block)

Main issues:how to leverage logical/functional hierarchy during embeddingwhen to deviate from designer’s hierarchymethodology for hierarchy reconciliation (buffers, repartitioning / reclustering, etc.)


Functional Partitioning

•Subblocks in A connected with subblocks in B result in•600 top level nets.

Source: ReShape


Physical Partitioning

Physical partitioning reduced the number of top level nets from 600 to 0

Source: ReShape


Unconstrained Placement


Floorplanned Placement


“Thermal” Map of Routing Congestion


“Natural” Block Shapes

1.0

1.0

0.5,0.5

Blk A Blk B

Are not disjoint rectangles, e.g., intersecting timing paths all want to be embedded as “straight paths”

Traditional chip floorplan = dissection into rectangles may not be optimum for wirelength and timing, but has compensating advantages (convenience)


Physical HierarchyPhysical hierarchy = hierarchical, very structured organization of the core layout region

Potentially, little relation to high-quality (e.g., w.r.t. timing, routability) embedding of logic

Some obvious exceptionsregular structures (memories, PLAs, datapaths)hard IP blocks

And, physical hierarchy helps to define and plan global interconnects

Recent trend: try to avoid artifactual physical hierarchy created by top-down recursive bipartitioning-based placement approach


Convergence and PredictabilityWe seek a predictable, estimatable back end (physical implementation after some handoff level of design)

Predictability == regression models? (e.g., wireload models)

Predictability == an enforceable assumption? (“correct by construction”)

constant-delay paradigm (logical effort, DEC, IBM, Magma, ...)

Predictability == fast constructive prediction? (also “correct by construction”)

RT-level (Tera Systems), gate-level flat full-chip (Silicon Perspective Corp. FirstEncounter)

Predictability == remove the need for predictability?GALS, LIS (global-asynchronous/local-synchronous; latency-independent synchronization)“protocol- / communication-based system-level design”Or, just make the loops tighter and easier (“construct by correction”)


Planning TechnologyRTL partitioning

understand interaction b/w block definition and placement qualityrecognize and cure a physically challenged logic hierarchy

Global interconnect planning and optimizationsymbolic route representations to support block plan ECOs

Controllable SP&R back end (including power/clock/scan)

Incremental / ECO optimizations, and optimizations that are “robust” under partial or imperfect design knowledge

Estimators (“initial wireload models”)to account for resource, topological heterogeneityto account for optimizations (placement, ripup/reroute, timing)

“earliest RTL signoff with detailed P&R knowledge”


Extra Slides


SequencePlace

&Route

PrepareDatabase

3D Extraction

True-3DParasitics

DelayCalculation

TimingAnalysisTiming

Analysis

InterconnectDriven

Optimization

InterconnectDriven

Optimization

SynthesisRTL

Timing Sign-off

Driver sizing,topology-based

optimization

Sequence, DAC-2000


Cadence, DAC-2000

Finalize Route/Extract/Back Ann.

Inter-block Routing and Buffering

Communication Logic Synthesis

Concurrent Placement, Synthesis And Route of Cells in Blocks

Block Area/Performance Estimation

Block Placement

RTL, chip constraints

Partitioning & Log/Phys MappingConstraints complete andblock RTLs are feasible

Ensure interblock delaysare accounted for

No iterations from here down


Magma, DAC-2000 “fixed timing”

0.6ns 0.6ns 0.6ns 0.6ns

FF

Actively managing wire delay:

Through automatic sizing (sizing-driven placement)Through buffer insertion


Interconnect ComplexitiesInterconnect effects play a major role in the increasing costs for large hard-block or rectilinear-outline based design stylesProbabilistic wireload models failWithout new capabilities for soft IP design and assembly, interconnect problems will significantly impact performance and cost for emerging IC technologies

Occ

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nce

Rat

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sizediewirelength

_~0.5

Local wires

Global wires

blocks

globalwires

Courtesy Pileggi, MARCO GSRC


Technology ScalingBlock sizes cannot grow as rapidly as chip sizes since block design becomes increasingly more difficult --- each block is a chip design over multiple configurations

If the blocks are inflexible, the global wiring problems begin to dominate all aspects of performance quality and system cost

Occ

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nce

Rat

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sizediewirelength

_~0.5

Larger chip with finer feature sizes



Soft BlocksWith soft, flexible blocks, the system assembly can more thoroughly exploit the available technologyInterconnect problem is controlled via: soft boundaries for area re-shaping; re-synthesis and re-mapping for timing; smart wires; and top-down specified block synthesisCf. “Amoeba” placement, coloring analysis of “good” placements with respect to original logic hierarchy, etc.

Occ

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nce

Rat

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sizediewirelength

_~0.5

Superior timing, power and cost



Taxonomy of Planning / ImplementationCentered on logic design (“logic synthesis drives”)

wire-planning methodology with block/cell global placementglobal routing directives passed forward to chip finishingconstant-delay methodology may be used to guide sizingSynopsys, (Magma)

Centered on physical design (“layout synthesis drives”)placement-driven or placement-knowledgeable logic synthesisCadence, Avant!

Buffer between logic and layout synthesis (“thin layer”)placement, timing, sizing optimization toolsSequence

Centered on SOC, chip-level planninginterface synthesis between blockscommunications protocol, protocol implementation decisions guide logic and physical implementation

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CSE241 VLSI Digital Circuits Winter 2003 Lecture 03: ASIC ... · Lecture 03: ASIC Flow and Design...

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