CSR September October 2013 Digital

7/27/2019 CSR September October 2013 Digital

1/68Chip Scale Review March/April 2012 [ChipScaleReview.com] 1

Volume 17, Number 5 September - October 2013

Acoustic Imaging & Inspection

Metrology for Bumping Processes

Wafer-to-Wafer Bonding for 3D ICs

Thermocompression Bonding (TCB)

Wafer-Level Fan-Out Packaging (WFOP)

INTERNATIONAL DIRECTORY OF BONDING EQUIPMENT FOR 2.5D and 3D ASSEMBLY

Packaging Innovations:

Graphene for Next-Generation Electronics Packaging

P. 20


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Chip Scale Review March/April 2012 [ChipScaleReview.com]2
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1Chip Scale Review September/October 2013 [ChipScaleReview.com]

CONTENTS

The integration of different known good dies from

different wafers, produced in different technologies

and fullling different functions is best done by

Fan-out Wafer Level Packaging technologies like

eWLB. It enables the highest integration density,

thinnest package, smallest die-to-die distance and

shortest interconnections realized substrate-less by

thin-lm redistribution layer. The picture shows

part of a reconstituted 300mm mold wafer with

different dummy dies embedded.

Source: Nanium S.A.

September October 2013Volume 17, Number 5

The International Magazine for Device and Wafer-level Test, Assembly, and Packaging

Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS,

MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.

FEATURE ARTICLES

Volume 17, Number 5 September - October 2013

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Acoustic Imaging & Inspection Metrology for BumpingProcesses Wafer-to-WaferBonding for3D ICs ThermocompressionBonding(TCB) Wafer-Level Fan-Out Packaging(WFOP)

INTERNATIONAL DIRECTORY OF BONDING EQUIPMENT FOR2.5D and 3DASSEMBLY

Packaging Innovations:Graphene for Next-Generation Electronics Packaging

P. 20

Next-Generation Wafer-Level Fan-Out PackageAkio Katsumata, Tomoko Takahashi,J-Devices

Graphene for Next-Generation Electronics PackagingKaustubh Nagarkar, Shakti Chauhan, Faisal Ahmad, Arun Gowda,

GE Global Research

Controlling Bumping Processes with Picosecond Ultrasonic MetrologyJohnny Dai, Priya Mukundhan, Tim Kryman,Rudolph Technologies, Inc.

Bonding Material Properties From a 3D IC PerspectiveMichelle Fowler,Brewer Science

Understanding TSVs, Interim Alternatives and Active InterconnectsDev Gupta,APSTL

17

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26

30

34
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Chip Scale Review September/October 2013 [ChipScaleReview.com]2
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FEATURE ARTICLES

DEPARTMENTS

CONTENTS

40

4

6

9

49

60

64

44

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56

Comparing Coolant Technologies in Semiconductor Wafer TestKlemens Reitinger,ERS electronic GmbH

Thermocompression Bonding (TCB) for Dimensional (2.5D and 3D) AssemblyAndy C. Mackie,Indium Corporation

Acoustic Imaging and InspectionTom Adams, Sonoscan, Inc.

Chip Scale MEMS Vacuum PackagingDouglas Sparks,Hanking Electronics Ltd.; and Jay Mitchell, Sangwoo Lee, ePack Inc.

From the PublisherA Major Milestone for IWLPC!Kim Newman, Chip Scale Review

Industry NewsChip Scale Review Staff

Product NewsChip Scale Review Staff

Advertiser Index, Advertising Sales

International Directory Of Bonding Equipment for 2.5D and 3D Assembly

Guest Editorial Achieving First-Pass Test Success on Flip-Chip and Pillar WafersTerence Collier, CVInc.
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his year marks a major milestone as the 10th Anniversary for theInternational Wafer-Level Packaging Conference (Nov. 5-7, DoubleTreeHotel in San Jose, California). All sponsorships and the 50 exhibit spacesare sold out. Highlights will include the Keynote Breakfast Address with

Paul Wesling (IEEE/CPMT), a 10th Anniversary Celebration Reception, an exclusive 3DPanel hosted by Invensas, plus two days where 50+ exhibitors will bring their top salesteams and executives to meet with prospective customers during the two days of exhibits.

There is an expo pass coupon for free access to the exhibits taking place Nov 6 &7 located in the Industry News section on page 9. Take advantage of the Early Birddiscounted rates in effect now through October 4. Visit http://www.iwlpc.com/register_now.cfm and register today!

Many companies will also be attending IMAPS Microelectronic Symposium (Sept. 30 -Oct. 3, Orlando, Florida) or the SMTA International Conference (Oct. 13-17, Fort Worth,Texas). On the other side of the world, SEMI will be running SEMICON Europa (Oct.8-10, Dresden, Germany). Pick up your copy of CSR during the events scheduled duringthis busy conference season. Visit the Nanium booth at Europa to pick up your copy, orlook for it in the media bins at the show.

This issue brings a broad selection of editorial content to satisfy the industrys hungerfor the latest developments in packaging technology. High on the list is the InternationalDirectory of Bonding Equipment for 2.5D & 3D Assembly teamed with an engagingarticle on thermocompression bonding. You wont want to miss the discussion ofgraphene for next-generation electronics packaging presented by the team at GE GlobalResearch. Wafer Test is covered by ERS, the MEMS Packaging feature is co-authored byePack Inc. and Hanking Electronics Ltd., Metrology for Bumping Processes is addressed

by Rudolph Technologies, and Wafer-to-Wafer Bonding for 3D ICs is covered by BrewerScience. Dev Gupta of APSTL reviews TSV-based 3D technologies, and J-Devicescontributes the latest on Wafer-Level Fan-Out Packaging.

Lastly, we welcome Lin (Leon) Tingyu to Chip Scale Reviews Editorial Advisory Board.

Leon received his PhD from the National University of Singapore and is currently aSenior Manager at the Institute of Microelectronics (IME) in Singapore. His expertiseis in IC manufacturing processes including TSV/ TSI, Cu wire bonding, high powermodules, thermal management, smartphone design and development, product mechanicalreliability, module design (FOWLP), and product failure analysis. Welcome Leo!

Volume 17, Number 5

The International Magazine for Device and Wafer-levelTest, Assembly, and Packaging Addressing

High-density Interconnection of Microelectronic IC'sincluding 3D packages, MEMS, MOEMS,RF/Wireless, Optoelectronic and Other

Wafer-fabricated Devices for the 21st Century.

FROM THE PUBLISHER

STAFF

Kim Newman [email protected] Michaels Managing [email protected]

Debra Vogler Senior Technical [email protected]

Dr. Thomas Di Stefano Contributing Editor

[email protected] Mirabito Contributing Legal [email protected] M. Sakamoto Contributing Editor [email protected] Winkler Contributing Editor

[email protected] ADVISORS

Dr. Andy Mackie (Chair) Indium Corporation

Rolf Aschenbrenner Fraunhofer InstituteDr. Thomas Di Stefano Centipede SystemsJoseph Fjelstad Verdant ElectronicsDr. Arun Gowda GE Global ResearchDr. John Lau Industrial Tech Research Institute (ITRI)Nick Leonardi Premier Semiconductor ServicesDr. Alan Rae Alfred Technology Resources

Dr. Ephraim Suhir ERS Company

Dr. Venky Sundaram Georgia Institute of Technology-3D Systems Packaging Research Center

Fred Taber BiTS Workshop

Dr. Leon Lin Tingyu Institute of Microelectronics (IME)Francoise von Trapp 3D InCitesDr. C.P. Wong Georgia Institute of Technology

SUBSCRIPTION--INQUIRIES

Chip Scale ReviewT 408-429-8585F [email protected]

Advertising Production Inquiries:

Kim Newman

[email protected]

Copyright 2013 Haley Publishing Inc.

Chip Scale Review(ISSN 1526-1344) is a registered trademark of

Haley Publishing Inc. All rights reserved.

Subscriptions in the U.S. are available without charge to qualified

individuals in the electronics industry. Subscriptions outside of the

U.S. (6 issues) by airmail are $100 per year to Canada or $115 per

year to other countries. In the U.S. subscriptions by first class mail

are $95 per year.

Chip Scale Review, (ISSN 1526-1344), is published six times a

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postage paid at Los Angeles, Calif., and additional offices.

POSTMASTER: Send address changes to Chip Scale Review

magazine, P.O. Box 9522, San Jose, CA 95157-0522

Printed in the United States

A Major Milestone for IWLPC!

T

PublisherKim Newman
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Although all statements and information contained herein are believed to be accurate and reliable, they are presented without guarantee or warranty of any kind, express or implied. Information provided herein does not relievthe user from the responsibility of carrying out its own tests and experiments, and the user assumes all risks and liability for use of the information and results obtained. Statements or suggestions concerning the use of materiaand processes are made without representation or warranty that any such use is free of patent infringement and are not recommendations to infringe any patent. The user should not assume that all toxicity data and safetymeasures are indicated herein or that other measures may not be required. 2012 Honeywell International Inc. All rights reserved.
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The Good, the Bad, and the DirtyThe flip-chip process begins at

the wafer fab where cleanliness isparamount. Particle-free wafers mightstill have thin layers of residues on thefinished products. In the subsequentstages, those layers are removed so thewafers can be bumped or pilled. Forthe sake of simplicity and space, thispaper will only review the liquid resist

process. After wafers are received fromthe fab, they are prepped for bumping.To simplify, resist is spun on a waferthat has been coated with a seed layer ofmetal. The resist is processed throughbake prior to alignment and exposure.Some resist brands require a postexposure bake after exposure, whileothers can proceed directly to develop. Adescum might be prepared after developto assure the openings in the resist arecompletely clear for bumping.

The clean and debris-free openingsare the sites where either bumps orpil lars will be formed. The next stepwafer bumping involves electroplatingthe under-bump metallization (UBM)stack (or copper pillar) followed bysolder bump (or caps for pillars). Next,the photoresist is removed to revealUBM metal with an initial pillar ofsolder. This resist removal step is one ofthe two main contamination sources forbumped wafers. Even with the standardfeatureless and almost flat surface of a

CMOS wafer, contaminants can become

igh-density bumps havea higher propensity for

entrapment of contaminants resulting intest failures of known good die. Bumpsand pillars provide nesting sites for bothsurface and subsurface materials that are

not typical of standard CMOS wafers.Building a flip-chip or pillar waferbegins with the addition of a wet or dryresist to a standard CMOS wafer. Theresist is processed and patterned in sucha manner as to leave openings wherea feature will be grown on the wafer.Figure 1 shows an example of openingsin liquid resist that have been spun on thewafer, baked, exposed and developed.While dry resist is applied and processeddifferently, the wafer will look similar

prior to when the lithography process iscomplete. As a result, similar residueswill be trapped on the wafer uponcompletion. While liquid resists area bit easier to remove, the pillars andbumps themselves become traps forholding resist, plating and post-etchresidues. Smaller form factor geometriesadd the additional difficulty of reducedbond strength. Where a large geometryfeature has more surface adhesion forbond strength, this author has notedthat smaller geometry features can bedislodged with the bump and pillarsduring the clean and saw operation.

If the debris remains and can bedislodged with saw coolant streams andspin rinse dryers (SRDs), probing canbecome a higher risk as well becauseprobe needles might exert more forceon individual bumps than either the sawor the SRD. Providing a wafer that isready for probe and that simultaneouslyreduces the necessary force required forgood electrical contact and high yield is

a challenge.

adhered and trapped to thesurface. These contaminantscan be reaction by-products,residues, or particles, andeasily adhere to the surfaceand cavities of small sub-

micron topography.Unders tanding that thefeatures and trap sites on bumped wafersare orders of magnitude larger than thetypical trap sites on standard CMOSwafers, it is easy to imagine the easewith which debris can be trapped. Thesurface of a CMOS wafer is typicallypassivation and aluminum. While thepassivat ion is typically inert (oxidesand nitrides), aluminum is a metal andprovides a catalyst site for contaminants

and corrosion. Aluminum is almost inertto backend processes, but serves as acatalyst for the new layers of Cu, Sn,Ag, Ti, and W, etc., providing for morecomplex contaminants. Adding resistand strippers for resist removal almostguarantees corrosion and contaminationto the final product. The spaces in andaround the pre-reow solder and copperpillars also provide mechanical nestingsites for particles that would be typicallylifted and carried away by gases anduid transfer on a at surface. Once thesolder undergoes reflow, those samelayers can now be chemically attachedto the surface.

Reow is assisted with ux and heat.Of course any material heated onto asurface is difcult to remove. While uxremovers will remove most of the ux,the newly burned on carbon materialsare almost impossible to remove. Thoseresidual amounts of flux can be turnedinto polymers when the wafers arerinsed and dried in organic solvents.

The reaction by-product and residual

Achieving First-Pass Test Success on Flip-Chip andPillar WafersBy Terence Collier [CVInc.]

H

GUEST EDITORIAL

Figure 1: From left to right: a) Original bump with debris, b)

Probe tip after a few touchdowns, and c) Probed bump withdebris transferred to the bump.


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process materials from resist processing,plating, stripping, ash by-products, andfluxing now support very difficult, ifnot impossible, layers to remove. Thequestion remains: were metal oxidesomitted? Neither organic solvents norplasmas remove this native oxide thatoccurs on Cu, Sn, Pb or Ag. Flux willremove the metal oxides, but ux has tobe removed, which promotes regrowthof metal oxide. How is this dilemmaresolved? The answer is no oxide isever completely removed in an oxygen-rich environment. Therefore, while oneprocess removes a set of materials, itmight exacerbate another problem.

TestElectrical test (probe) and assembly

performance will be improved byremoving native and non-native oxides,etch residues, photoresist and otherdebris deposits on the surface of bumps/pi lla rs . Mo st co mm er ci al fl ux andwafer cleaners are moderately effectiveat removing organic contaminants,but not as effective against burned-onorganic residue; most have very limited

capability at removing metal oxides.Cleaning ALL residue is criticalfor stable test yield; proper oxide andresidue removal improves probe cardlife and rst pass test yield. For example,during first pass electrical test,either a sample or 100% of devices areelectrically tested. Failures are groupedin bins as opens/shorts, functional andparametric fails. Some of the failuresare due to contamination on the bump orprobe card that contribute to high contact

resistance (CRES) in the test circuit.Metals have low bulk and surface

resistance - typically less than 50milliohms. The contact area, typicallythe surface of the bump plus theprobe card tip, might have higher thannormal surface resistance because ofcontaminants, oxidation and corrosion.CRES can increase the normally lowresistance between the device undertest (DUT) and the outside world by upto a few megohms. Since the electrical

contact to the outside world is made

at this interface, contact resistance isa critical parameter. Increased CRESimpedes electrical contact betweenthe dev ice and tes te r . Reduc ingCRES improves yield and extendsthe life of hardware and preventivemaintenance costs.

As a r esu l t , CRES can be theroot cause of open/shorts and somepara metri c fails. To re cov er thos efailures, a second pass and even thirdpass electrical test can be required.This author has seen some wafers haveonly a 30% success on first pass andsubsequently require second and thirdpass testing to achieve 50% and 85%,

respectively. Each probe pass picks alittle debris from the bump that thenadheres physically or chemically to theprobe needles. So the probe needles picka small amount of debris from the bumpswith each pass, until false failures beginto occur.

The needles can also deposit some ofthis debris onto the bumps. If the probeneedle contacts a dirty surface, somesmall amount of material adheres to thesurface of the probe tip. The vertical

motion of the probe then causes thatmaterial to deposit on the next bumpuntil enough material accumulates ateither interface where good devicesbegin to fail. Those failures are the diethat require retest to capture knowngood die.

SummaryA significant percentage of known

good devices require multiple test passesbecause of contamination and corrosion

on bumps and pillars. Cleaning probeneedles can temporarily reduce CRES,but if the bumps are not cleaned, theCRES will quickly increase resultingin more false failures. Proper cleaninghelps recover yield loss, reduces cycletime, and extends the life of probeneedles if the needles dont have to becleaned as frequently.

BiographyTerence Collier is President of

CVInc.; email [email protected]
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Distinguished Lecturer, is scheduled

to give an exciting and colorful historyof device technology development andinnovation in his presentation "TheOrigins of Silicon Valley: Why and HowIt Happened Here during the KeynoteBreakfast on November 6.

Additionally, this year the exhibitionwas expanded to include over 50so lu t ions p rov ider s showcas ingeverything from materials to equipment,market research to metrology, andfoundries to OSATs.

The IWLPC Registration is nowavailable on-line and Early Birdconference pricing is in effect untilOctober 4, 2013, after which registrationprices will go up $100.

3D ASIP 2013 Focuses on theTechnology and Market Landscapefor Device and Systems Integrationand Interconnect

Now celebratingits 10th year, 3DArchitectures forSemiconducto r I n t e g r a t i o na n d P a c k a g in g( 3 D A S I P ) ,

which takes place December 11 13,2013, Hyatt Regency San FranciscoAirport Hotel, Burlingame, California,

IWLPC 2013 Program Finalized andRegistration is Open

The SMTA and Chip Scale Revieware pleased to announce the presentationline-up for the 10th Annual InternationalWafer-Level Packaging Conference(IWLPC), which will be held November5-7, 2013 at the DoubleTree by HiltonHotel in San Jose, California.

Four application-oriented tutorialsfocused on Interposers, TSVs, Wafer-Level Packaging (WLP), and ChoosingBetween Technologies are featured onTuesday, November 5, 2013. They will

be instructed by experts in the fieldincluding Rao Tummala, Ph.D., fromGeorgia Institute of Technology, LuuNguyen, Ph.D., from Texas Instruments,John H. Lau, Ph.D., from the IndustrialTechnology Research Institute (ITRI),and Herber t J . Neuhaus , Ph .D . ,TechLead Corporation.

T h e c o n f e r e n c e t a k e s p l a c eNovember 6 and 7, and comprises threetechnical tracks on WLP, 3-D (Stacked)Packaging, and MEMS Packaging. With

a record number of abstracts receivedthis year, the technical committeeadded two technical sessions on 2.5/3DIntegration to help accommodate themany topics. A special session forMetrology and Test was created to focuson this under-served area of technology.From the worlds of 3D and MEMS, aline-up of plenary speakers and panelistswas assembled to provide successstories and offer a glimpse of new andemerging technologies and applications.

Paul Wesling, a CPMT Society

continues to be an ideal venue to meet

with leaders from around the world tolearn and discuss the latest technologyand market insights into 2.5/3D deviceand systems integration and packaging.

E v e r s i n c e t h e f i r s t 3 D A S I Pconference took place a decade ago,the 2.5/3D community and technologyhave progressed considerably, notesconference co-chairs Philip Garrou,IEEE Fellow and Consultant, andRobert Patti, CTO and VP DesignEngineering, Tezzaron. Yet there are stillmany questions remaining about wherethe industry will be 10 years from now,what market applications will lead theway, and how each company can bestcompete in the emerging 2.5/3D deviceand system interconnect world.

The conference fo rmat o f f e r sattendees a platform to gain the latestinformation on technology progressand industry trends that define thissector today and tomorrow. With over20 invited speakers, the conferenceaims to provide information critical toplanning ongoing and future businessand technical efforts impacted by 2.5/3Ddevelopments and opportunities.

3 D A S I P t a r g e t s s e n io r - l e v e ltechnologists, managers, and businessleaders from the worlds foremostcompanies and research institutions, and

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addresses the interests of the entire 2.5D/3D ecosystem, from

technology developers to equipment and materials suppliers todesigners, manufacturers, foundries, packaging providers, andend users.

For more detailed information on this years event, please visitthe conference website at www.3dasip.org. Sponsor and exhibitopportunities are available on a rst-come, rst-serve basis.

European 3D TSV Summit: Application Ready Themeto Focus on Both Business and Technology Aspects

The latest TSV product developments and achievementswill be discussed at the 2nd European 3D TSV Summiton January 21-22, 2014 in Grenoble, France. Buildingon the success of the 1st event that attracted almost 320people from 20 countries, the theme of this years eventis Application Ready, addressing 3D TSV from both abusiness and technology perspective. The latest TSV productdevelopments and achievements including cost, businessmodels, supply chain, manufacturability and technologyaspects will be addressed by executives and experts fromglobal companies.

Executives from design houses, fabless, IDMs, OSATs

as well as equipment and materials suppliers will present

during this unique two-day event. More than 25 speakerswill share their views during the plenary presentations aswell as round table discussions. An exhibition zone willbe located at the heart of the venue, enabling companiesto showcase their products and services to decisionmakers. The event also includes a unique opportunityto visit the CEA-LETI 300mm TSV clean room. Priorthe event, attendees will be able to prepare their Summitschedule on-site meetings by using a specially developedsoftware tool.

New this year, as an introduction to the event, a Pre-Summit Symposium discussing MEMS and TSV will be heldon January 20 in the late afternoon with an invited speaker,roundtable and welcome cocktail.

The event continues to address the hot and controversialtopics related to 3D TSV manufacturing and offersun ique ne twork ing and p romot ion oppor tun i t ies .The European 3D TSV Summit Steering Committeeinc ludes execu t ives f rom: ams AG, BESI , CEA-LETI, EV Group, Fraunhofer-IZM, imec, Multitest,Oerlikon Systems, SPTS, STMicroelectronics, andSUSS Microtec.

64th ECTC Call for Papers and ProfessionalDevelopment Courses

IEEE opened up its Callfor Papers for ECTC 2014,inviting all companies orindividuals interested inpresenting at this yearsevent to submit abstracts

and proposals about new developments and technologyrelated to the following:

Advanced Packaging Applied Reliability Assembly and Manufacturing Technology Electronic Components and RF

Emerging Technologies Interconnections Materials & Processing Modeling & Simulation Optoelectronics Interactive PresentationsThere are mult ip le presentat ion oppor tuni t ies a t

ECTC 2014. Anyone interested in giving oral, interactivepresentations, or students interested in presenting a postersession should submit an original, previously unpublished, andnon-condential abstract to the appropriate program chair.

Additionally, the 2014 conference will have a number

of Professional Development Programs as part of the
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conference. Each educational course

will be 4 hours long and be hosted bya chosen instructor. Those interestedin leading a course should submita 200-word proposal that includesa course object ive, out l ine, anddescription of who should attend to theprogram chairs.

All submissions must be submittedelectronically by October 14, 2013.Selected authors and instructors willbe announced by December 14, 2013.For more information, visit the ECTCwebsite at www.ectc.net

3D InCites and TechSearchInternational Announce the Winnersof the First Annual 3D InCitesAwards

The 3D technology focused onlinecommunity, 3D InCites, and MarketResearch rm, TechSearch International,have announced the winner s o f the first annual 3D InCites AwardsProgram. The program, established torecognize achievements to further thecommercialization of 2.5D and 3D ICtechnologies, benets the IEEE FrancesB. Hugle Engineering Scholarship,which encourages young women to

pursue careers in engineering. A panelof nine industry expert judges and anonline popular vote represented the 10votes to determine the winners from aeld of 25 nominees in ve categories.

Xilinx Virtex 7 H580T won theaward for 3D Products Design/Process.Mentor Graphics swept two awardcategories, winning for 3D DesignTools with its Calibre tool, and the 3DTest and Reliability Tools/Equipmentcategory with its Tessant MemoryBIST

produc t. EV Grou ps EV G850TB /

DB XT won the 3D Manufacturing

Equipment award, and Dow Corning,took home the 3D Materials award withits Temporary Bonding Solution.

Awards were presented at a breakfastceremony hosted by Impress Labs,Thursday, July 11, 2013 at the ImpressLounge during SEMICON West. Duringthe event, Ana Londergan, Senior StaffEngineer at Qualcomm Technologiesthe awards platinum sponsor, presented a$5,000 check on behalf of the 3D InCitesAwards Program to Jan Vardaman,TechSearch International, representingthe donation to the IEEE Frances B.Hugle Engineering Scholarship.

Applied Materials Names Gary E.Dickerson as CEO

Applied Mater ials , Inc. Boardof Directors has appointed Gary E.Dickerson as president and chief executive officer (CEO) and MichaelR. Splinter as executive chairmanof the Board of Directors, effectiveSeptembe r 1, 2013. Additiona lly,

Dickerson will serve on the Boardof Directors. Dickerson is currentlypres iden t of Appl ie d Materi al s andsucceeds Splinter, who has served as theCompany's CEO since 2003.

In a s ta tement , Spl in ter cal ledDickerson an outstanding leaderand partner who is focused on thecompanys growth s trategies . " Iwelcome him to the Board and haveevery confidence that his vision andpersonal drive wil l translate into

remarkable success in leading Applied

Materials as our next CEO, he said.

For his part, Dickerson creditedAMAT with a strong foundation fromwhich to build, noting the companysbroa d te ch no lo gy, de ep tal en t, an dpassion for driving materials innovationthat will provide the device performanceand yield solutions needed to advancetechnology. Our opportunities havenever been greater and I am grateful toMike and the board for the privilege tolead Applied into a new era of growthand success, he said.

A lo n g - t im e in d u s t r y l e a d e r ,Dickerson served for seven yearsas CEO of Varian SemiconductorEquipment Associates, Inc. until itsacquisition by Applied Materials in2011 and spent 18 years at KLA-TencorCorporation where he held a variety ofoperations and product developmentroles before serving as president andchief operating officer. He earned aBS degree in Engineering Managementfrom the University of Missouri, Rollaand an MBA from the University ofMissouri, Kansas City.

Splinter was named president andchief executive officer of AppliedMaterials and a member of its boardof directors in 2003, and becamechairman of the board in 2009. He is a40-year veteran of the semiconductorindustry and has reportedly led Appliedto record revenue and profits duringhis tenure as CEO. This fall, he willreceive the Semiconductor IndustryAssociation's 2013 Robert N. Noyce

Award for his outstanding achievementsand leadership in suppor t of thesemiconductor industry.

GLOBALFOUNDRIES and AppliedMaterials Sign Fab 1 ServiceAgreement

S e m i c o n d u c t o r e q u i p m e n tmanufacturer, Applied Materials, Inc.(AMAT) has signed an enhanced two-year contract with top tier foundry,GLOBALFOUNDRIES Inc., to service

all AMAT equipment at its Fab 1 in

INDUSTRY NEWS
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Dresden, Germany. According to thecompany, this Applied PerformanceService contract ex tends beyondtraditional tool maintenance to supportGLOBALFOUNDRIES in optimizingtechnology ramps, increasing capacity,reducing scrap and improving factoryoutput stability in critical areas.

"GLOBALFOUNDRIES is currently

ramping i ts wor ldwide capaci ty ,including the build-out of the Dresdensite into the largest manufacturingsite in Europe," said Kay-Uwe Weber,Director Global Supply Managementof GLOBALFOUNDRIES Fab 1. "Webelieve the spirit of this contract - tohave both service teams collaborateeven closer using Applied's technicaldepth and Fab1 's manufactur ingexperience - will provide us withcustom-made services to accelerate

our success."Under the agreement, a team of

AMAT certified engineers will provideGLOBALFOUNDRIES Fab 1 with24x7 suppor t in miss ion-cr i t icalareas, using advanced engineeringand logistics technologies, includingAMATs remote diagnostic capabilityand proprietary equipment engineeringand diagnostic software. All the AMATtools covered under the enhancedcontract will receive preventive and

corrective maintenance, spare parts

management , par ts c leaning and

coating, and analytical services." We a r e v e r y p l e a s e d t h a t

GLOBALFOUNDRIES Fab 1 has

chosen us as an important collaborator

and resource in helping to achieve its

aggressive growth and technology

goals in Dresden," said Charlie Pappis,

group VP and general manager of

Applied Global Services. "Together,

we 've ta i lo red a f lex ib le , w ide-

ranging Performance Service program

that focuses Applied 's efforts on

solving high-value manufacturing

c h a l l e n g e s , w h i c h w i l l a l l o w

GLOBALFOUNDRIES Fab 1 to focus

on its core competency of providing

high quality, advanced technology to

its customers."

SUSS MicroTec Honored with SPILsOutstanding Performance Award

E v e r y t w o y e a r s S i l i c o n w a r e

Precision Industries Co., Ltd. (SPIL),

a top tier outsourced semiconductor

assembly and test service (OSATS)

provider headquartered in Taichung,Taiwan, honors its most respected

suppl iers wi th i t s Outstanding

Performance Award.

This year, SPIL honored SUSS

MicroTec, supplier of equipment and

process solutions for the semiconductor

a n d r e l a t e d m a r k e t s , w i t h i t s

Outstanding Performance Award.

Only one other company was selected

out of a eld of 500 suppliers to receive

the 2013 award. The award, established

to acknowledge excellent supplierperformance, is based on criteria such

as quality, price, delivery, support

and technology.

In the fast-moving semiconductor

industry, quality, technology and

support are major distinctive features

of equipment providers, says Frank P.

Averdung, President and CEO of SUSS

MicroTec. We are honored to receive

this distinctive recognition of our work

from SPIL one of our most valued

customers.

Sono-Tek Corp. Expands In-House

Laboratory Testing Facilities

Sono-Tek Corporation, a globalultrasonic spray technology company,announced the complet ion of i tslaboratory testing facility expansion,located at the corporate headquartersin Milton, NY. The recent acquisitionof equipment, including an SEMmicroscope for onsite coatings analysispe rfo rm ed in the lab, led to som ereorganization and physical expansionof the facility to provide a betterworkow for customers and visitors inaddition to some increased elbow room.

Access to equipment such as thisnew SEM is benecial not only to Sono-Tek customers, but to the surroundingcommunity of colleges and otherresearch institutions in New York foradvancing research and manufacturingof future innovations in our area, saidSteve Harshbarger, president, Sono-Tek. We envision our lab continuingto grow in the coming years, as newapplications for ultrasonic spray coatingcontinue to develop.

Sono-Tek reports that the newly

installed equipment, and particularly theSEM microscope, enables the companyto gauge process variables by providingimmediate onsite analysis of coatingsthat require very precise depositioncharacteristics, such as photoresist ontoMEMs, fuel cell coatings, medicalimplantable device coatings and othernanomaterial coatings. Additionally, anew corona surface treatment has beeninstalled to better prepare substrates forimproved surface tension characteristics

prior to coating. The acquisition of at


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least one more surface treatment tool is

planned in the future.

Ultratech/Cambridge NanoTechExpands Operations With New,State-Of-The-Art Facility

Ultratech, Inc., a supplier of lithography,laser-processing and inspection systemsto the semiconductor advanced packagingand related markets, has relocatedUltratech/Cambridge NanoTech toWaltham, MA. After acquiring the assets

of Cambridge NanoTech in December

2012, the company invested in a newfacility to enhance atomic layer deposition(ALD) development.

ALD technology provides coatingsand material features with significantadvantages compared to other existingtechniques for depositing precisenanometer-thin films. This technologyis expected to be in high demand involume manufacturing environmentsfor integrated optics, micro-electro-m e c h a n i c a l s y s t e m s ( M E M s ) ,implantable devices in the biomedicalsector and batteries and fuel cells in theenergy market.

The new state-of-the-art facilitywill reportedly expand its operationsfor next-generation ALD equipmentdevelopment to enable leading-edgescientic research.

The completion of the new facility

marks our successful integration of

the Cambridge NanoTech assets intoUltratech's nanotechnology productgroup, says Arthur W. Zafiropoulo,Chairman and CEO of Ultratech. Byinvesting in the expansion of theseoperations, we expect to generateincreased revenue in new and existingmarkets. Ultratech, and our ALDunit, Ultratech/Cambridge NanoTech,will continue to focus on technologysolutions that support our global

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customers ' advanced product and

technology roadmaps."

Micromirror Technology forSmartphones: The Next Big Thing

With consumers using smartphonesas mobile entertainment centers, theability to project photos and videoson any surface may soon becomethe no rm. A*STAR Ins t i tu te o f Microelectronics (IME) and OPUSMicrosystems Corporation, a Taiwan-based company specializing in Micro-Electro-Mechanical Systems (MEMS)scanning mirror devices, have signedan agreement to refine and develop aMEMS scanning mirror for smartphoneapplications. This would reportedly

enable phones to project photos andvideos on any surface, and with noconstraints on the viewing screen size

of the mobile devices.M E M S s c a n n i n g m i r r o r o r

micromirrortechnology, which isused in light-modulating devices, hasundergone rapid technological progressover the years. This has led high videoand image quality in high-definitiontelevisions and more recently, digitalcinemas. The market demand for suchvisual experience expresses itself inportable consumer electronics, such astablets and mobile phones, in which

gaming, photo, and video applications

have become integral. This technology

is expected to be a major component inthe next generation of smartphones.To meet this demand, OPUS and IME

will work together on the developmentof an optimized MEMS scanning mirror,which will enable a pico-projector forsmartphones applications. Through thisproject, the two parties aim to achievea slimmer, smaller, higher-performanceMEMS micromirror that offers a compactyet high-resolution pico-projectorsolution for smartphones, essentiallyturning any surface into a display.

T h e p r o j e c t s i g n i f i e s O P U SMicrosystems rst research partnershipand project in Singapore and will buildon IMEs experience and knowledge in

the field of MEMS.IME will lead theprocess design anddevelopment whileOPUS Microsystemswill contribute inthe design of thescanning mirror.

We are delightedt h a t O P U SMicrosystems haschosen IME to betheir partner for itsfirst research projectin Singapore, saidP r o f . D i m - L e eKwong, Executive

Director of A*STAR IME. Theinterest in pico-projectors has gainedtraction in recent years, but the industry

challenge remains in achieving a cutting-edge technology that will allow theintegration of a small-scale projectorinto smartphones while maintaining ahigh resolution output. It is an excitingR&D opportunity for IME to be part ofsuch a project that will potentially lead toa technological breakthrough.

Hesse Mechatronics Opens Trainingand Applications Lab in Tempe,Arizona

Hesse Mecha t ron ics , Inc . , the

Americas subsidiary

of Hesse GmbH,manufac tu re r o f h igh-speed f ine-pitch wedge bondersand fully automaticheavy wire bondersf o r t h e b a c k e n ds e m i c o n d u c t o r industry, recentlyopened its newestt r a i n i n g a n dapplications lab in

Tempe, Arizona.The company assigned responsibility

for the new lab to Allan Camp, whojoined the company as technical supportmanager in June 2012. Camp bringsmore than two decades of experience inthe semiconductor industry, includinghis work for Eastman Kodak Companyin microelectronics packaging andXerox Corporation in wafer fabrication.

Camp will oversee technical supportand training on Hesse Mechatronicsfamily of semiconductor packaginge q u ip m e n t b o th a t t h e t r a in in gfacility and at customer sites. Hewill also conduct demonstrations ofHesse Mechatronics' wedge bondingequipment, including thin wire wedgebonders and heavy wire wedge bonders,so customers can validate and qualifythe equipment prior to making aninvestment in new technology.

Allans knowledge in wafer faboperations, microelectronics packaging,and semiconductor process equipment

will serve our customers well as heprovides training that addresses theirspecific equipment and manufacturingrequirements, notes Joseph S. Bubel,president of Hesse Mechatronics, Inc.

Camps role and the new lab aresteps in Hesse Mechatronics strategy toimprove customers experience. Hesseintends for the new lab to increase theconvenience of qualifying and learningabout their wedge bonding equipmentand the convenience of taking advantage

of support services.


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must enable high-speed electricaltransmission, lower thermal resistance,and multi-function capability.

To meet the requirements listedabove, several fan-out packages arebeing developed. There are sometechnical issues, however. First, theembedded dies in the mold resin

shif t their positions because heatproces se s sh rink the resin, and th ealignment accuracy of wire bonding orinterconnect redistribution is thereforelimited. Additionally, in embeddedpackages, dies are covered by resin,so the heat generated by the devicescannot dissipate efficiently. In fan-inpackages , the body size depends onthe die size, so their design rules arenot very flexible. In response to thisproblem, we developed a new type of

fan-out package, called wafer-level fan-out (WFOP). This new package canovercome these issues and has highlyaccurate die placement, lower thermalresistance and is capable of placingballs outside of the die.

The Basic StructureFigure 1 shows the cross section

of the structure and Figure 2 theactual view of the distribution layer.The package is one of the face-down

mounting types that uses a metalplate, such as stainless steel or copper,as the base plate of the redistributedinterconnection layer. The dies are

new package structureand techno logy fo r the next-generation of

wafer-level packaging (WLP) is beingdevelopedcalled wafer-level fan-out package (WFOP). A face-downmounting type, this package uses ametal plate, e.g., stainless or copper,

as the base plate of its redistributedinterconnection layer. The redistributiontraces fan out of the dies, so that thepin count is not limited by die size asin the case with WLP. The redistributedlayer is fabricated using the semi-additive method of copper plating. Bymanufacturing with this large scalepanel substrate, we can achieve higherthroughput than with the conventionalwafer manufacturing method. Moreover,this new package has several additional

benets, including being ultra-thin withexcellent thermal characteristics, anda reduced noise level, which are madepossible by the metal plate. Additionally,the packaging process using this directpatterning method has the potential fornew styles of semiconductor packages.The package structure, process flow,design rules, and package characteristicswill be provided in this article.

Packaging Drivers

Recently, the smart device markethas been dominating the electronicdevice business. Smart devices, suchas mobile phones, tablets of varioussizes, and e-readers, have multiplefeatures and functions, such as imaging,data processing, 3D graphic engines,MPEG engines, cameras, RF, TV andmore. Various system LSI, memoriesand components are used for thosedevices. Requirements being placedon semiconductor packages includeminiaturization, high wiring density,and thinness. Packages, of course,

mounted on the metal p late , andthe resin between the dies acts as astress buffer and insulator for theinterconnections. The distribution layeris fabricated using the semi-additivemethod of copper plating. In Figure 1,there are two layers for the trace, but

it is not limited to two. Three layerstwo layers for signals, and one layer forthe ground planewill be the typicalformat. In Figure 2a, the contactsbetween the die pads and distributionlayer are leaded. Figure 2b shows across section of area pads connectionsand redistribution traces. The solderresist is formed on the interconnectionlayer and the balls are placed on thesolder resist.

Process FlowThe process flow begins when the

Next-Generation Wafer-Level Fan-Out Package

By Akio Katsumata, Tomoko Takahashi [J-Devices]

A

Figure 1:Cross section.

Figure 2:a) Peripheral array distribution traces; b)Area array distribution traces.

a)

b)


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minimum pitch is 150m and30m via holes in the pads arecreated as shown in Figure 2b.

One of the benefits of this newpa ckag e is it s th in ness ; he ig htdata for the package is shown inFigure 3. The nominal height indesign is 960m, and the averageis around 965m. In this package,a 50m die thickness, no core, nobumps and fewer build-up layersare achieved.

Package CharacteristicsFigure 4 shows the simulation

result of thermal resistance to comparethis package and the wire bondingtype plastic fine-pitch ball grid array

(PTFBGA). Two types of the base plateare simulated, one stainless, the othercopper. The x-axis is the die area ratioof the package size. Generally, thesmaller the die size ratio, the higher thethermal resistance. But in all ratios, thispackages thermal resistance is lowerthan that of the PTFBGA, by 5% to 15%in the stainless steel base plate type, andby 22% to 45% in the copper base platetype. The temperature contour diagramin Figure 4 shows that more heat

cannot spread on the die in PTFBGA.This means that the metal plate inthis package functions as an effectiveheat spreader.

dies are attached onto the metal plate.The placement accuracy is less than +/-5m. After that, the resin is laminatedas an insulator for the redistributionlayer. Openings are made in the resin inthe area of the die pads. Next, using the

plating method, traces are formed on theresin layer. In the case of multi-layers,the sequence from resin lamination toplating traces is repeated. The solderresist is laminated on the resin and thetraces, and then patterned for solderballs, and the balls are placed on it .Finally, the metal plate is singulatedinto individual units by dicing, and thepackages are completed.

In the process flow, the size of themetal plate is not limited because the

process starts with placing dies on itand redistributing wires. In other words,those packages can be fabricated notonly by wafer scale, but also by panelscale. This means higher throughput isachieved by leveraging the scale.

Design RulesT a b l e 1 s h o w s s o m e d e s i g n

specification values. There are twooptions for the die pad array. In thecase of the peripheral pad array, the

current minimum pitch is 50m, andwe connect redistribution traces anddie pads as shown in Figure 2a. In thecase of the area pad array, the current

Figure 5 shows the electromagnetinterference (EMI) test method andresults. The models tested were PFBGA,the basic structure of WFOP package(the basic type shown in Figure 5),

and the type with a grounded metal lid(the grounded type shown in Figure 5).Compared to the PFBGA, the outputpower noise of the basic type (of WFOPpackage) is lower by 10dB, and thenoise of the grounded type is lowerby 25dB. The result can be explained

by noting that the metal plate in this

package works effect ively as a noiseshield, even though the metal plate is afloating node. In the grounded type, itworks even better.

Table 2 shows the results of reliabilitytests for the basic structure. Temperaturecycle testing (TCT), pressure cookertesting (PCT), high-temperature storage(HTS) testing, and on-board TCT werecarried out. The electrical connectionand scanning acoustic topography (SAT)images are checked at each lap. There isno problem.

Table 1:Design specications.

Figure 3:Actual package height of the basic structure.

Figure 4:Comparison of thermal resistance.


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cooling can be seenin Figure 7 . Thetotal warpage valueis only around 70m.Most of the warpageh a p p e n s a r o u n d

130C, which is theTg of one resin inthe package. Overand under 130C, themetal plate is stiff

enough to keep the resinfrom warping. Suchstacked-die packagesare required for highspec memories. The

sample shown in Figure6 is for 2CH/4CE. Asa nex t s tep , we a replanning to develop afour die stack and aneight die stack in onepackage as 8CH/8CE.

SummaryIn this article, we

introduced a next-generation fan-outpacka ge a ne w embe dd ed wa fer -level package structure and fabricationtechnology. This structure is a promisingsolution for a thinner package withmore traces, lower thermal resistance,and better electrical characteristics.

Possible applications for this new

package (in both FBGA and FCBGA

3D PackagingFigure 6 shows the cross section of a

stacked-die type of WFOP package. Themanufacturing process for the stacked-

die type is very similar to the basic type.The second die is attached on the resinover the first die, and is covered withresin again, and traces are formed overthe resin. This sequence is repeatedagain for the third and the fourth dies.The TCT result of this package is shownin Table 3. No problems are found inelectrical tests and SAT images.

The warpage under heating and formats) are CPU and MPU peripheralsin smart devices. We are also planningto expand th is d irect pat tern ing

technology to future packages, such asmulti-chip module (MCM), stacked-dies, and package-on-package (POP).These structures will provide thesolution for system-in-package, andbecause this package is less susceptibleto EMI, it will be a promising solutionfor RF devices.

AcknowledgmentThe authors deeply appreciate support

by the staff in cooperating companies.

BiographiesAkio Katsumata received his BS

in Industry Chemistry from ChibaU . a n d i s t h e G e n e r a l M a n a g e r f o r t h e P a c k a g i n g R e s e a r c h &Development Center at J-Devices;email [email protected]

Tomoko Takahashi received her MSin Material Physics from Osaka U.and is the Specialist for the PackagingResearch & Development Center

at J-Devices.Figure 6:Cross section of stacked die package.

Figure 5:Comparison of EMI.

Table 2:Results of reliability tests for the basic structure.

Table 3:TCT result of the stacked die package.

Figure 7:Warpage during heating and cooling.


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currently used materials. Balandin,et al., first reported intrinsic thermalconductivity of 4800-5300W/m-K [1].Most electronic packaging applicationstoday typically deploy metals (Cu 400W/m-K, Ag 430W/m-K, Al 250W/m-K) as heat spreaders or llers,for solid conduction-based heat transfer.

Later studies reported ballistic phononconduction in graphene with thermalconductivity between 2000-4000W/m-K[2, 3]. The upper end of this range isachieved for isotopically pure graphene(


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Optoelectronic Devices. Graphenefinds itself at the center of manyoptoelectronic appl icat ions suchas optical modulators and ultrafastbroadband photo-detectors. The highcarrier mobility would enable such

devices to operate at frequenciesapproaching hundreds of GHz. But theissue of the limited absorption capabilityof a single monolayer (merely 2.3%at 300nm to 2500nm) will need to beaddressed [10]. Graphene could also beintegrated in devices such as high powersemiconductor lasers to extract light,deliver current, and at the same time,spread out the heat, which could have aremarkable impact on devices such asLEDs, vertical external cavity surface

emitting lasers (VECSELs), opticalmodulators and optical amplifiers andtheir packaging.

Interconnects . Transistors andinterconnects are two major areas thatcould utilize the superior electricalpr op ert ies of graph en e. Gr aphene -based on-chip interconnects varyingfrom a few nanometers to microns are actively researched as theyenable miniaturization, compatibilitywi th po ten t ia l beyond CMOS

graphene transistors, and excellentthermal performance. Also, issues ofelectromigration and current densityrelated to todays metallic (typicallyCu) interconnects could be resolved[11]. Graphene nanoribbons (GNRs)have been actively researched for on-chip interconnects because of theircompatible fabrication process. In early

the utilization of graphene as they oftenrely on a combination of properties (suchas thermal, electrical, and mechanical).Graphene-based materials, therefore,can provide a significant leap forwardin the performance and reliability of

electronic devices and systems.

Fabrication Routes and ApplicationsMany processing techniques have

been researched to manufac turegraphene as summarized in Table 1.These can broadly be categorized as top-down or bottom-up approaches [9]. Top-down approaches typically use graphiteas the starting material and exfoliateit to yield graphene. These processes arecapable of producing large quantities

of high-quality graphene in flake orpowder form. On the other hand,bottom-up approaches create layer bylayer of graphene from a carbon source;these are slower but yield continuouslarge area, single or multi-layer sheets.The table also lists potential electronicpackaging applications based on theform achieved by the manufacturingm e t h o d . T h e m o s t p r o m i n e n tapplications include next-generationnano-electronic (beyond CMOS) and

optoelectronic devices, interconnects,and thermal management, ranging fromthe chip, to the system level [Figure 1].The other key areas that are relativelyunexplored include structural (such asencapsulants), shielding, and impactresistance materials. This sectionoutlines the potential of graphene in allthe aforementioned areas.

studies, their resistivity was measuredto be comparable to copper in variousnanometer-width scales [5, 12]. Severalresearchers have already lookedinto the use of CNTs in combinationwith graphene for 2.5D/3D through-

silicon via (TSV) interconnects [11].Researchers have also proposed densevertical and horizontal graphene(DVHG) for TSV lling and horizontalinterconnects [11, 13].

The research on graphene for off-chipinterconnects primarily spans printableinks, transparent conducting layers,electrodes, and fillers in solder. Earlycommercialization of graphene-basedinks have targeted the replacement ofmore expensive silver inks with better

performance tha n carbon inks forflexible electronics [14]. An excitingarea of development is in the use ofgraphene for transparent conductingelectrodes for flexible/stretchableelectronics. Roll-to-roll capable, largearea, multi-layer conducting lms withgreater than 90% transparency and lessthan 125 Ohm/sq sheet resistances havebeen demonstrated using a CVD process[15]. Graphene also has the potential forrobust, low cost anisotropic conducting

films for interconnect applications,especially with transparent conductorsin displays [16]. Efforts to makeanisotropic conductive films (ACF)with graphene encapsulated magneticmicrospheres or graphene-coatedpolymer spheres have shown promisingelectrical results [17]. The potentialof graphene as an additive in soldershas also been explored. Exfoliatedgraphene oxide f lakes ( that weresubsequently converted to graphene)

were incorporated with indium orindium-gallium alloy to form a matrixcomposition that resulted in lower netthermal and electrical resistivity in thematerial [18].

Heat spreading Layers . Severalemerging applications in consumerand military electronics like RF andmicrowave power amplif iers (Si-L D M O S , G a A s M E S F E T s , S i CMESFETs and GaN HEMTs), 2.5Dand 3D integrated Si microprocessors

and memory devices, require theintegration of on-chip cooling strategiesTable 1: Types of processes used to manufacture graphene and related applications.


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enhancements in thermal conductivity,electrical conductivity, mechanicalstiffness and gas barrier properties inpolymeric composites with graphenefillers [22]. Shahil, et al., reported upto 2300% enhancement in a graphene-

epoxy nanocomposite at 10% loadingfor TIM applications, outperformingconventional metallic fillers as well asCNT fillers in similar matrix systems[22]. At just 2% loading, they were ableto enhance the thermal conductivity ofcommercial thermal grease from 5W/m-K to 14W/m-K, while preserving allmechanical properties. For electricallyconductive polymeric systems, graphenellers have shown the lowest percolationthreshold (between 0.1% - 0.37% weight

percent) as compared to conventionalfillers [22]. Similarly, elastic modulusand tensile strength can be enhancedby a factor of 2-8 with


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pho to- detectors . Figure 2b showsa pillared graphene structure thatutilizes CNTs as interlayer connections

multi-layer implementations. Suchsuper-lattice structures could also beused in broadband, high bandwidth

between individual graphene layers[27]. Such a structure could eventuallyyield a 3D material without the highdegree of anisotropy seen in graphiticstructures, while retaining the intrinsicproperties. Simulation results suggest

that the spacing and length of the CNTconnections and the precise natureof CNT-graphene nodes need carefulconsideration [28]. Both heterogeneousand pillared graphene implementationsare inhibited by the lack of a viablefabrication process.

Figure 2c shows a graphene foamstructure, where an unbroken MLGor FLG film can be provided within amacroscopic structure. Early thermalproper ty measurements of graphene

foam structures have shown promisingresults due to the absence of nodesor junctions, which strongly limit theproperties of other 3D manifestations(as in Figures 2a and b) [29]. Petteset al., reported an effective thermalconductivity of ~1.7W/m-K of a FLGfoam structure with only 0.45% volume

Figure 2: Potential architectures to realize macroscopic (3D) structures with graphene lms: a) graphene h-BN heterostructure, b) pillared graphene with graphene-CNT structures, c) 3D graphene foams, and d)graphene nanocomposite.
http://www.emulation.com/


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microelectronic devices and systems.Todays manufacturing techniquescan produce graphene in many forms,at varying scales, as required bypotential target applications. Signicantchallenges, however, exist in the

geometric scalability of graphene, whilepreserving its intrinsic properties forelectronic packaging applications. Thefirst commercial implementations ofgraphene are being realized in the areaof nanocomposites. Meanwhile, other2D materials, such as hexagonal boronnitride (h-BN), whose structures aresimilar to that of graphene, are alreadybeing actively researched [30]. A wholefamily of graphene-like materials haveemerged, which include transition

metal dichalcogenides (TaS2, WS 2,MoS2, MoTe2, NiTe2), graphene oxideand reduced graphene oxide, graphane(double-sided hydrogenated graphene)and f luorographene ( f luor inatedgraphene) [31 ] . The var ied bu tcompatible properties of such materialsmay help ll the gap in the adoption ofgraphene (or like) materials in electronicpackaging applications.

References

1. A. A. Balandin, S. Ghosh, W.Bao, I. Calizo, D. Teweldebrhan,F. Miao, C. Lau, Superior Thermal Conductivity of SingleLayer Graphene, Nano Letters,8, 902907, 2008.

2. A . A . Ba land in , ThermalProperties of Graphene andN a n o s t r u c t u r e d C a r b o nMaterials, Nature Materials, 10,569581, 2011.

3. E. Pop, V. Varshney, A. Roy,

Thermal Properties of Graphene:Fundamentals and Applications,MRS Bulletin, 37, 2012.

4. K. Bolotin, K. Sikes, Z. Jiang, M.Klima, G. Fudenberg, J. Hone, etal., Ultrahigh Electron Mobilityin Suspended Graphene, SolidState Communications, 146,351, 2008.

5. R. Murali, Y. Yang, K. Brenner,T. Beck, J. Meindl, BreakdownCurrent Density of GrapheneNanoribbons, Applied PhysicsLetters, 94, 243114, 2009.

fraction. With further increase in volumefraction, or surface area to volume ratioin such structures, higher effectiveproperties could be attained.

G r a p h e n e N a n o - c o m p o s i t e

Implementations. Another strategy

to make macroscopic structures withgraphene-like properties is throughthe fabrication of graphene-basednanocomposi tes (Figure 2d ) . Asdiscussed earlier, such materials can beused as inks, TIMs, barrier coatings,encapsulants, etc. In this context, top-down approaches to manufacturegraphene-based llers (GNP, akes, etc.)are particularly attractive. While initialresults in this field have been quitepromising, there is sti ll considerable

room for improvement and optimization.The desirable character is t ics for the f illers are large domain size,low defect density and appropriatefunctionalization for interfacial couplingand dispersion. It has been establishedthat production of GNP fillers throughthe oxidation of graphite and thermal orchemical reduction the most attractiveroute for large-scale production ofgraphene-based nanocomposites canalso adversely modify the mechanical

stiffness, electrical transport and thermalproperties of the graphene-fillers. Forinstance, wrinkles and atomic-scaleperforations found in thermally reducedgraphene (TRG) may make the sheetsless stiff, more permeable and reducethermal and electrical conductivity,but may inhibi t restacking , therebyimproving dispersions at higher loading.Alternative cost-effective routes toexfoliate graphene layers need to besought that preserve graphenes intrinsic

properties in the nanocomposite system.These would, as an example, involveeliminating the structural deformationor unnecessary functionalization andpost-t reatments that restore graphiticplanar domains.

SummaryEver since the discovery of graphene

in 2004, there has been a rapid growthin studying its properties, as well asunearthing disruptive applications

(such as sensors). Graphene has thepotential to offer vast improvements in

6. C. Lee, X. Wei, J. Kysar, J. Hone,Measurement of the ElasticProperties and Intrinsic Strengtho f M o n o la y e r G r a p h e n e , Science, Vol. 321 no. 5887, pp.385-388, 2008.

7. R. R. Nair, H. A. Wu, P. N.Jayaram, I. V. Gregorieva, A. K.Geim, Unimpeded Permeationof Water Through Helium-LeakTight Graphene-BasedMembranes , Sc ience , 27 ,335, 2012.

8. Q. Bao, H. Zhang, Z. Ni, Y.Wang, L. Polavarapu, Z. Shen,et al., Monolayer Graphene asSaturable Absorber in Mode-Locked Laser, Nano Res., 4, pp.

297-307, 2011.9. R . Edward s , K . Co lem an ,

G r a p h e n e S y n t h e s i s :Relationship to Applications,Nanoscale, 5, 38, 2013.

10. K. F. Mak, M.Y. Sfeir, Y. Wu,C. H. Lui, J. A. Misewich, T.F. Heinz, Measurement of the Optical Conductivity of Graphene, Phys. Rev. Lett. 101,196405, 2008.

11. M. Nehei, CNT/Graphene

Technologies for AdvancedI n t e r c o n n e c t s a n d T S V s , SEMATECH Symposium Taiwan,October 18, 2012, Hsinchu,http://www.sematech.org

12. R. Murali, K. Brenner, Y. Yang,T. Beck, J.D. Meindl, Resistivityo f G r a p h e n e N a n o r i b b o nInterconnects, IEEE ElectronDevice Letters, Vol. 30, No. 6,June 2009.

13. A. Kawabata, T. Murakami, M.

Nihei, N. Yokoyama, Growth ofDense, Vertical and HorizontalGraphene and I t s ThermalProperties, Japanese Journalof Applied Physics 52 04CB06,2013.

14. http://vorbeck.com15. S. Bae, H. Kim, Y. Lee, X.

Xu, J. Park, Y. Zheng, et al.,Roll- to-roll Production of30-inch Graphene Films forT r a n s p a r e n t E l e c t r o d e s ,

Nature Nanotechnology, 5, 574-578, 2010.


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16. H. Kim, J. Kim, K. Kim, H. Lee, S. Lee, S. Lim, M.Park, Tailored Anisotropic Magnetic ConductiveFilm Assembled from Graphene-encapsulatedMultifunctional Magnetic Composite Microspheres,US8178201B2.

17. J. Shen, Y. Zhu, K. Zhou, X. Yang, C. Li, Tailored

Anisotropic Magnetic Conductive Film Assembledfrom Graphene-encapsulated MultifunctionalMagnetic Composite Microspheres. Jour. of MaterialsChemistry, 22, 545-550, 2012.

18. K. Jagannadham, Thermal Conductivity of IndiumGraphene and Indium-GalliumGraphene Composites,Jour. of Electronic Materials, 40, 1, 25-34, 2011.

19. S. Subrina, D. Kotchetkov, A. Balandin, GrapheneHeat Spreaders for Thermal Management of Nanoel ec tronic Ci rcui ts , IEEE Elec tron DeviceLetters, 30 (12), 1281, 2009.

20. Z. Yan, G. Liu, J. Khan, A. Balandin, Graphene

Quilts for Thermal Management of High-power GaNTransistors, Nature Communications, 3, 827, 2012.

21. I. Jo, M. T. Pettes, J..Kim, K. Watanabe, T. Taniguchi,Z. Yao, L. Shi, Thermal Conductivity and PhononTransport in Suspended Few-Layer Hexagonal BoronNitride, Nano Letters, 13 (2), pp 550554, 2013.

22. H . K i m , e t a l . , G r a p h e n e / P o l y m e r Nano com pos ites, Macrom ol ecules, 43 , 65 15 6530, 2010.

23. X. Li, et al., Large-Area Synthesis of High-Qualityand Uniform Graphene Films on Copper Foils,Science, 324 (5932), 1312-1314, 2009.

24. Z. Li, P. Wu, C. Wang, X. Fan, W. Zhang, X. Zhai,et al., Low-temperature Growth of Graphene byChemical Vapor Deposition Using Solid and LiquidCarbon Sources, ACS Nano, 5(4), pp. 3385-90., 2011.

25. T. Yamada, J. Kim, M. Ishihara, M. Hasegawa, Low-temperature Graphene Synthesis Using MicrowavePlasma CVD, Jour. of Applied Physics, 46, 2013.

26. J. Chen, C. Jang, S. Xiao, M. Ishigami, M. S. Fuhrer,Intrinsic and Extrinsic Performance Limits ofGraphene Devices on SiO2, Nature Nanotechnology 3,206 209, 2008.

27. G. K. Dimitrakakis, E. Tylianakis, G. E. Froudakis,

Pillared Graphene: A New 3-D Network Nanostructurefor Enhanced Hydrogen Storage, Nano Letters, 8 (10),pp. 31663170, 2008.

28. V. Varshney, S. S. Patnaik, A. K. Roy, G. Froudakis, B.L. Farmer, Modeling of Thermal Transport in Pillared-Graphene Architectures, ACS Nano, 4 (2), pp. 1153-1161, 2010.

29. M. T. Pettes, H. Ji, R. S. Ruoff, L. Shi, ThermalTransport in Three-Dimensional Foam Architecturesof Few-Layer Graphene and Ultrathin Graphite, NanoLetters, 12 (6), pp. 29592964 2012.

30. D. Pacile, J. C. Meyer, C. O. Girit, A. Zettl, Two

Dimensional Phase of Boron Nitride: Few-atomicLayer Sheets and Suspended Membranes, Applied

Physics Letters, 92, 133107, 2008.31. B. Radisavljevic, A. Radenovic, J. Brivio, V.

Giacometti, A. Kis, Single-layer MoS2 Transistors,Nature Nanotechnology, 6, pp. 147-150, 2011.

BiographiesKaustubh R. Nagarkar received a BE in Mechancal

Engineering from the U. of Mumbai, India, and MS and PhDdegrees in Electronics Packaging from the State U. of NewYork at Binghamton. He is a Senior Electronic PackagingEngineer at GE Global Research, Niskayuna, NY; [email protected]

Shakti S. Chauhan received a BE in MechanicalEngineering from the U. of Pune, India, and MS and PhDdegrees in Mechanics/Materials Science from Iowa State U.;he is a Mechanical Engineer at GE Global Research Center.

Faisal R. Ahmad has a BSc ARCS in Theoretical Physicsfrom Imperial College, London; and a PhD in Physics from

Cornell U.; he is a Physicist at GE Global Research Center.Arun V. Gowda received a BE in Mechancal Engineering

from the U. of Bangalore, and MS and PhD degrees inElectronics Packaging from the State U. of New York atBinghamton. He is Manager of the Electronic Packaging &Miniaturization Laboratory at GE Global Research.
http://www.winwayglobal.com/


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The bumps themselves are comprised ofa multilayered stack of various metalswith the mechanical and electricalper formance of the in terconnectdetermined by the physical dimensionsand metallurgical characteristics of theindividual layers.

As these advanced packag ingprocesses move from development tohigh-volume production, manufacturers

r equ i r e au tomated measu remen tcapability with the speed and precisionto control the process, thus maintainingboth yield and throughput. Automatedmeasurements improve repeatabilityand reduce labor costs. Given thatpackaging often occurs at an outsourcedsemiconductor assembly and test(OSAT) facility using expensive, knowngood die, a comprehensive interconnectmetrology is becoming widespread byOSATs and IDMs who have in-house

packaging facilities.Figure 2 shows the typical layers used

in a copper pillar bump interconnect.Each metal layer in a copper pillar bumpcontributes to the specific mechanicaland electrical characteristics of theinterconnect. A copper pillar bump mayconsist of an Al or Cu conductive padfollowed by a Ti or TiW barrier layerto prevent diffusion of copper into thepad, a Cu seed layer to ensure properadhesion, the plated Cu pillar, a Ni or

NiV diffusion barrier, possibly Pd over

d v a n c e d p a c k a g in gprocesses cont inue tofollow a developmentpa th simi lar to front-

end processes, with increasing processcomplexity and decreasing feature sizedemanding greater attention to inspectionand metrology to control processes andmaintain yields. In addition, the highvalue of the known good die beingpackaged multiplies the cost of scrapand the benefit of increasing yield. Theadoption of advanced packaging hasdriven an increase in interconnect densitywith more I/O connections in smallerform factors. Bumps used in fine-pitch,high-density interconnects are now assmall as 15m diameter at a 40m pitch.Importantly, the plating processes usedto create these bumps and interconnectsexhibit pattern dependent variations thatrequire direct measurements on product

wafers to ensure adequate process control.Bumping p rocesses came in to

widespread use with the adoption ofip-chip packaging processes. Flip-chipprocesses generally use solder bumpsand can create bumps with pitches downto 150m. In response to the demandfor higher interconnect densities,manufacturers have developed advancedpack ag in g proces se s tha t in te rposecomplex structures between the chip(s)and the package to route electrical

signals and secure the chip mechanicallyto the package (Figure 1). Althoughthere are many different schemes forthese interconnects, (commonly referredto as 2.5D packaging) most use someform of bumping to create mechanicaland electrical connections betweenstacked components , i .e . , ch ips ,interposers and packages. Typically,these bumps are made of copper andcreated using a plating process. Copperpillar bumps have reached diameters as

small as 15m with 40m pitch in-line.

the Ni to prevent oxidation, and toppedoff by either a Au ash or a SnAg soldercap. All of these materials are opaque tovisible light and thus require non-opticaltechniques for thickness measurementand proper process control.

Picosecond UltrasonicMeasurements

Picosecond ultrasonic measurementis a non-contact, non-destructivetechnology that uses an extremely short

pulse of intense laser light to heat a verysmall spot on the sample surface. Theexpansion that results from the nearlyinstantaneous heating generates anacoustic wave that travels down throughthe various layers of the sample. Ateach interface between layers, the waveis partially reflected back toward thesurface. By precisely measuring the timeelapsed between the initial pulse and thereturning reections from each interface,one can accurately measure the thickness

of each layer in a multilayer stack.Metal films ranging in thickness froma few tens of Angstroms to greater than10m can be measured. Measurementsare based on first principles and do notrequire daily calibrations or referencewafers. The small spot size (5m 7m)allows for measurements directly onproduct wafers.

Picosecond ultrasonic metrology iswell established for metal lm thicknessmetrology and qualified as a process-

of-record tool at all top ten IDMs and

Controlling Bumping Processes with PicosecondUltrasonic Metrology

By Johnny Dai, Priya Mukundhan, Tim Kryman [Rudolph Technologies, Inc.]

AFigure 1: Advanced packaging techniques usecomplex structures to route signals between thechip and the package, allowing more connections

in less space. The structures are typically createdwith wafer-level processing using processessimilar to front-end fabrication processes.

Figure 2: Bumps provide the mechanical andelectrical connections between stacked components.The bumps are themselves complex stacks ofmultiple layers. The performance of the connectiondepends on the physical and metallurgicalcharacteristics of the lms in the stack.


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on selected examples of characterizingmicrobumps and describe some of thepattern-dependent plating effects that wehave observed.

Characterizing MicrobumpsOn an advanced packaging wafer,

our foundry customer was interestedin measuring the thickness of 15mdiameter microbumps. The stack wasnominally described as Au/Pd/Ni/Cu on oxide. A metrology pad wasalso identified for measurements todetermine if there was any differencein the process between the bump andthe pad. A full wafer map along withrepeatability measurements wererequested to understand

the capab i l i t i es o f thet e c h n o l o g y f o r s u c hmeasurements and alsoto help characterize thewithin-wafer uniformity.

Figure 3 shows the rawsignal obtained from the padand the microbump. Using

foundries in front-end semiconductormanufacturing. Recently, we have beenworking with foundries and OSATs toqualify this technology for advancedpackaging. To meet the needs of ourpackaging customers, improvements

have been made to the hardwaresconfiguration to extend the upperthickness limits of the films measured,while reducing the measurement sitesize capability to measure directly onmicrobumps. Optical techniques existthat can measure physical characteristics,such as bump height, plot uniformity,and coplanarity across the wafer, butpicosecond ul tr asonic me trology isunique in its ability to measure in sites assmall as 15m and provide multi-layer

film specific information. Picosecondultrasonics is therefore capable ofprov id ing th e me tr ology needed tocontrol advanced bumping processes.Measurements of under bump metalstacks (UBM) and redistribution layers(RDL) are routine from a measurementstandpoint. In this article we will focus

a)

b)

c)

Figure 3: Raw data for the a) Pad, b) Microbump, and c) Example ofmodeled t to measured data. The echo positions correspond to Au,Pd, Ni and Cu, respectively.
http://www.icproto.com/http://www.icproto.com/


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F i g u r e 7 s h o w s a s c h e m a t i crepresentation of the structures identiedfor measurements. Six different sites,ranging in size from 20m-40m wereselected on a nine-wafer skew. The stackwas nominally Ni/Cu. Using picosecond

ultrasonics, we measured the thicknessof the Ni and Cu layer simultaneously.

picosecond ultrasonics, we were able tomeasure the thickness of all the layerssimultaneously. The echo positionscan be identied unambiguously in thegraph and correspond to the variouslayers of the stack. Using standard

speed of sound in the materials, we cancalculate the thickness of the films asThickness=velocity*echo position/2.

The within-wafer (WIW) uniformityprof iles for al l the layers measuredon both the microbump and pads areshown in Figures 4 and 5. The filmswere nominally measured at 200Au/400 Pd/4m Ni/1m Cu. The 1 standard deviation for WIW uniformityon the pad was ~7% for Au, 3% for Pd,0.5% for Ni and 3% for Cu. The bump

measurements, in general, showed morevariations and the WIW uniformity weremuch higher than the pad: ~9% for Au,~9% for Pd, 1% for Ni, and 5% for Cu.The variation in thickness between thepad and the microbump is signicant anddemonstrates the need for monitoringdirectly on the microbump instead ofthe pads in order to get an accuraterepresentation of process variations. Inhigh-volume manufacturing, the abilityto consistently and reliably measure

these small structures is very important.Precision (30 repeats at wafer center) aswell as stability (load/unload, ve days,two times a day) measurements weremade on both the structures.

Precision measurements for all thelayers for both the pad and the bumpwere


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allows for full wafer characterizationat production-worthy throughputs andprovides excellent stabi lity for high-volume manufacturing.

BiographiesT im K r y m a n r e c e iv e d h i s B S

from Lock Haven U. and an MBAfrom DeSales U. and is a Director ofMetrology Product Management atRudolph Technologies, Inc.; [email protected]

Priya Mukundhan received her PhDfrom Stevens Institute of Technology andis a Director of Technology Developmenta n d A p p l i c a t i o n s a t R u d o l p hTechnologies, Inc.

Johnny Dai received his PhD from

Fudan U. and is a Sr. ApplicationScientist at Rudolph Technologies, Inc.

SummaryAs the advanced packaging process

become s more complex, metr ologyrequirements are also becomingvery stringent. Microbumps are nowapproaching diameters as small as

15m with a pitch less than 50m.The materials and thicknesses used inthe bumping process are critical to themechanical and electrical performanceof the final package. In this study, wehave demonstrated the use of picosecondultrasonics for the measurement ofmicrobumps (15m diameter) andthe value in measuring directly on thebumps instead of a metrology pad. Thenon-contact, non-destructive technique

Figure 6: Pad and microbump stability plots.

Figure 8: Ni and Cu thickness proles across the different sites on nine different die that were measured.

Figure 7: Schematic representation ofmeasurement sites.

Table 1: Summary of ve-day stability datacollected on both pad and microbump.Summaryof ve-day stability data collected on both pad andmicrobump.

1 Std. Dev

Stability Au Pd Ni Cu

Pad 0.03% 0.05% 0.01% 0.03%

Microbump 0.02% 0.09% 0.05% 0.05%

IWLPC, November 5-7, 2013,

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topography and flowinto vias and trenches.Known as the polymerm e l t r h e o l o g y o r melt viscosity, thisp r o p e r t y a l l o w sth e t h e r m o p la s t i cbondin g ma te rial topl ana ri ze th e wa fe rsurface when the filmis baked above the

melt temperature ofthe polymer. The totalthickness variation(TTV) is a measure of the lm thicknessuniformity across the wafer (maximumfilm thickness minus minimum filmthickness), which is typically reducedduring the baking process (Figure 1).

For todays 3D IC devices, severeor extreme topography is drivingthe need for thicker bonding films.Thermoplastic bonding materials

capable of achieving film thicknessesof 50m or thicker have become thenew standard. When coated using aspin-apply process, the thermoplasticbonding material must cover a substrate200-300mm in diameter at reasonablespin speeds (


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bonding lm is no longer fully exposedto the outside environment; the waferedge is the only exposed area. Bondfailures at the wafer edge can occurwhen the bonding material absorbsmoisture or other contaminants which,

when subjected to vacuum or heat, canvolatilize and cause failures within thebond line (Figures 4 and 5).

For processes where dry-etch removalis possible, a thermoset material offers

of film uniformity li

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