1. 2014 CUI Inc 2014 APEC Industry Session Solus Power Topology Applied in a Point-of-Load Dc-Dc Converter Fariborz Musavi, PhD Director of Engineering, Novum Advanced Power CUI Inc.

2. Agenda What is POL? Applications CPU power dissipation POL converter topologies Limitations of existing topologies Solus Power Topology Advantages Experimental results 3. What is a POL Converter? A step down converter Commonly buck / synchronous buck topology Very low voltage, and high current 0.6V, 1V, 1.2V, 1.6V, 1.8V, 3.6V 12A, 25A, 50A, 60A, 90A, 100A, 120A Constant output voltage independent of load Fast transient response 4. Application of PoLs Networking solutions Telecommunications Data-communications Computing applications Space technologies Defense applications 5. CPU Power Dissipation Pcpu = Pdyn + Psc + Pleak Psc : Short-circuit power consumption Pleak : Power loss due to transistor leakage currents Pdyn : Dynamic power consumption due to logic-gate activities in the CPU Pdyn = CV2f C : Capacitance inside logic-gate V : CPU supply voltage f : Clock frequency 6. Existing Topologies Synchronous Buck Converter Q2 Lo Co L O A D Vin Q1 Control Synch Vout 7. Limitation of Existing Topologies High side, low side drivers Cross conduction / shoot through Low efficiency at light loads Operation in its continuous conduction mode (CCM), versus the discontinuous conduction mode (DCM) for a conventional buck converter at light load: More conduction losses 8. Limitation of Existing Topologies Slow transient response: 1. Controller must wait until the succeeding clock pulse before the control switch is turned on again. 2. Due to the finite bandwidth of the linear compensator, it is shown that the control voltage vcon cannot increase at a sufficient rate. 9. Limitation of Existing Topologies Physical limitations of semiconductor devices 10. Solus Power Topology SEPIC-Fed Buck Converter Q1SB L1A Co L O A D Vin Vout C1 Cin L1B Q2B L1C Q2S 11. SEPIC-Fed Buck Topology Advantages Lower conduction losses Lower switching losses Increased switching frequency Increased bandwidth Better transient response Higher power density Switching Loss Comparison 12. SEPIC-Fed Buck Topology Advantages Two Current path to feed output Better transient response Reduced hold-up capacitor Inductor at the input Smaller input current ripple Reduced input filter capacitor No shoot-through issues 13. NDM3ZS-60, Experimental Results 76% 78% 80% 82% 84% 86% 88% 90% 92% 94% 5 10 15 20 25 30 35 40 45 50 55 60 65 Efficiency(%) Output Current(A) Efficiency: Vin = 12V, Vo = 1V NDM3ZS-60, Converter Efficiency vs. Output Current 14. NDM3ZS-60, Experimental Results Transient response: Output Caps: 3000 F Current Slew Rate: 2A/s Step change(s): 45A to 15A 15A to 45A Peak Deviation: