Current Steering DAC

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Linkping Studies in Science and Technology

Dissertation No. 944

MODELING AND IMPLEMENTATION OFCURRENT-STEERING DIGITAL-TO-ANALOG

CONVERTERS

K Ola Andersson

Department of Electrical Engineering

Linkpings universitet, SE-581-83 Linkping, Sweden

Linkping, May 2005


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Modeling and Implementation of Current-Steering

Digital-to-Analog Converters

Copyright 2005 K Ola Andersson

Department of Electrical Engineering

Linkpings universitet

SE-581 83 Linkping

Sweden

ISBN 91-85297-96-8 ISSN 0345-7524

Printed in Sweden by UniTryck, Linkping, 2005


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i

AbstractData converters, i.e., analog-to-digital converters (ADCs) and digital-to-analogconverters (DACs), are interface circuits between the analog and digital domains.

They are used in, e.g., digital audio applications, data communication applica-

tions, and other types of applications where conversion between analog and digi-

tal signal representation is required. This work covers different aspects related to

modeling, error correction, and implementation of DACs for communication

applications where the requirements on the circuits in terms of speed and linear-

ity are hard. The DAC architecture considered in this work is the current-steeringDAC, which is the most commonly used architecture for high-speed applications.

Transistor-level simulation of complex circuits using accurate transistor models

require long simulation times. A transistor-level model of a DAC used in a sys-

tem simulation is likely to be a severe bottleneck limiting the overall system sim-

ulation speed. Moreover, investigations of stochastic parameter variations require

multiple simulation runs with different parameter values making transistor-level

models unsuitable. Therefore, there is a need for behavioral-level models with

reasonably short simulation times. Behavioral-level models can also be used tofind the requirements on different building blocks on high abstraction levels,

enabling the use of efficient top-down design methodologies. Models of different

nonideal properties in current-steering DACs are used and developed in this

work.

Static errors typically dominates the low-frequency behavior of the DAC. One of

the limiting factors for the static linearity of a current-steering DAC is mismatch

between current sources. A well-known model of this problem is used exten-

sively in this work for evaluation of different ideas and techniques for linearityenhancement. The high-frequency behavior of the DAC is typically dominated by

dynamic errors. Models of two types of dynamic errors are developed in this


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ii

work. These are the dynamic errors caused by parasitic capacitance in wires and

transistors and glitches caused by asymmetry in the settling behavior of a current

source.

The encoding used for the digital control word in a current steering DAC has a

large influence on the circuit performance, e.g., in terms static linearity and

glitches. In this work, two DAC architectures are developed. These are denoted

the decomposed and partially decomposed architectures and utilize encoding

strategies aiming at a high circuit performance by avoiding unnecessary switch-

ing of current sources. The developed architectures are compared with the well-

known binary-weighted and segmented architectures using behavioral-level sim-

ulations.

It can be hard to meet a DAC design specification using a straightforward imple-

mentation. Techniques for compensation of errors that can be applied to improve

the DAC linearity are studied. The well-known dynamic element matching

(DEM) techniques are used for transforming spurious tones caused by matching

errors into white or shaped noise. An overview of these techniques are given in

this work and a DEM technique for the decomposed DAC architecture is devel-

oped. Inmodulation, feedback of the quantization error is utilized to spec-trally shape the quantization noise to reduce its power within the signal band. A

technique based on this principle is developed for spectral shaping of DAC non-

linearity errors utilizing a DAC model in a feedback loop. Two examples of utili-zation of the technique are given.

Four different current-steering DACs implemented in CMOS technology are

developed to enable comparison between behavioral-level simulations and mea-

surements on actual implementations and to provide platforms for evaluation of

different techniques for linearity improvement. For example, a 14-bit DEM DAC

is implemented and measurement results are compared with simulation results. A

good agreement between measured and simulated results is obtained. Moreover,

a configurable 12-bit DAC capable of operating with different degrees of seg-mentation and decomposition is implemented to evaluate the proposed decom-

posed architecture. Measurement results agree with results from behavioral-level

simulations and indicate that the decomposed architecture is a viable alternative

to the commonly used segmented architecture.


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iii

AcknowledgmentsFirst of all, I would like to thank my supervisor, Prof. Mark Vesterbacka for hisguidance and enthusiasm. I would also like to thank all my colleagues at Elec-

tronics Systems, Linkping University, for contributing to a pleasant working

environment. Special thanks go to Lic. Eng. Robert Hgglund, Lic. Eng. Henrik

Ohlsson, and Ph.D. Oscar Gustafsson for interesting discussions on research and

life in general.

My former colleagues at Ericsson Microelectronics also deserve my gratitude.

Specifically, I would like to thank Ph.D. J. Jacob Wikner, M.Sc. Niklas U.

Andersson, and Ph.D. Mikael Karlsson Rudberg. I also thank Ph.D. Gunnar

Bjrklund and M.Sc. Magnus Hgglund for supporting my work during the years

I spent doing research at Ericsson Microelectronics.

Finally, I thank my wonderful family, especially my wife Helena and my daugh-

ter Elin, for always believing in me and supporting me.

The work was supported by the Microelectronics Research Center (MERC) at

Ericsson Microelectronics and the Center for Industrial Information Technology(CENIIT) at Linkping University.


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vii

3.3 Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3.1 1-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3.2 Multi-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . 98

3.3.3 Properties of Decomposed DACs . . . . . . . . . . . . . . . . . . . 99

3.4 Partially Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . 1003.5 Other Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.6 Comparison of Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.6.1 Influence of Matching Errors . . . . . . . . . . . . . . . . . . . . . 105

3.6.2 Influence of Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.6.3 Simulation Result Summary . . . . . . . . . . . . . . . . . . . . . . 114

3.7 Encoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

3.7.1 Decomposition Encoder Implementation . . . . . . . . . . . . 114

3.7.2 Binary-to-Thermometer Encoder Implementation . . . . . 115

Chapter 4

Correction and Compensation of Errors . . . . . . . . . 1174.1 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.1.1 Generalized DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.1.2 DEM Utilizing Switching Trees . . . . . . . . . . . . . . . . . . . 120

4.1.3 Mismatch-Shaping DEM . . . . . . . . . . . . . . . . . . . . . . . . 1224.1.4 DEM in Decomposed DACs . . . . . . . . . . . . . . . . . . . . . 123

4.2 Distributed Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.3 Modulation of Expected Errors . . . . . . . . . . . . . . . . . . . . . . . 129

4.3.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.3.2 Spectral Shaping of Output Impedance Related Errors . 131

4.3.3 Yield Enhancement of Binary-Weighted DACs . . . . . . 132

Chapter 5

Test-Chip Implementations . . . . . . . . . . . . . . . . . . . . 1395.1 Design and Measurement Strategies . . . . . . . . . . . . . . . . . . . 139

5.1.1 Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

5.1.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.2 A 14-bit Segmented DAC in 0.35m CMOS . . . . . . . . . . . . 1445.2.1 Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

5.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3 A 14-bit PRDEM DAC in 0.35m CMOS . . . . . . . . . . . . . . 1475.3.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148


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5.3.2 Simulations and Comparison with Measurements . . . . . 148

5.4 A 14-bit Dual DAC in 0.25m CMOS . . . . . . . . . . . . . . . . . 1525.4.1 Architecture and Implementation . . . . . . . . . . . . . . . . . . 152


5.5 A 12-bit Configurable DAC in 0.35m CMOS . . . . . . . . . . 1555.5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.5.2 Pcell-Based Design Approach . . . . . . . . . . . . . . . . . . . . 156

5.5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165


Chapter 6

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175


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1 IntroductionData converters, i.e., analog-to-digital converters (ADCs) and digital-to-analogconverters (DACs), are interface circuits between the analog and digital domains.

They are used in, e.g., digital audio applications, data communication applica-

tions, and other types of applications where conversion between analog and digi-

tal signal representation is required. This thesis covers different aspects related to

modeling, error correction, and implementation of DACs for communication

applications. This chapter is an introduction to the thesis providing relevant back-

ground information and an overview of the thesis and the authors contributionsto the different areas.

1.1 Digital-to-Analog Conversion

An overview of fundamental theories for digital-to-analog conversion is provided

in this section. The concepts of sampling and reconstruction are discussed in

Sec. 1.1.1, and reconstruction using pulse-amplitude modulation is overviewed in

Sec. 1.1.2. Ideal reconstruction using sinc pulses and reconstruction using square

pulses are presented in Sec. 1.1.3 and Sec. 1.1.4, respectively, followed by a dis-

cussion on the ideal DAC in Sec. 1.1.5.

1.1.1 Sampling and Reconstruction

Let denote time and let denote an analog signal, which is uniformly sam-

pled to a discrete-time signal according to

, (1.1)

t z t( )

x n( )

x n( ) z nT( )=


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Introduction

2

where is the sequence index and is the sample period. If is band limited,

having no spectral content above a frequency , and the sampling frequency

has the property

, (1.2)

then the analog signal can be reconstructed from the discrete-time signal

according to the sampling theorem [1].

1.1.2 Pulse-Amplitude Modulation

The reconstruction of a signal can be performed using pulse-amplitude modula-

tion (PAM), in which case the reconstructed signal is given by

, (1.3)

where is a pulse. A model system for constructing is shown in Fig. 1.1.

An intermediate signal given by

(1.4)

is constructed, where is the unit impulse. Let denote angular frequency

and let and denote the Fourier transforms of and , respec-

tively. can be expressed as [2]

. (1.5)

Further, is filtered with a filter having the impulse response , resulting

in the reconstructed output . Hence, the Fourier transform of is

, (1.6)

where is the Fourier transform of . Different choices of the pulse

are discussed in the following sections.

n T z t ( )

f0fs 1 T=

fs 2 f0>z t( )

x n( )

y t( )

y t( ) x n( )p t nT( )

n =

=

p t( ) y t( )

y0t( )

y0t( ) x n( )t nT( )n =

z t( ) t nT( )

n =

= =

t( ) Z( ) Y0( ) z t( ) y0t( )Y0( )

Y0( ) 1

T--- Z k2

T------( )

k =

fs Z k2fs( )k =

= =

y0t( ) p t( )

y t( ) y t( )

Y( ) P( )Y0( ) P( ) fs Z k2fs( )k =

= =

P( ) p t( ) p t( )


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Digital-to-Analog Conversion

3

1.1.3 Ideal Reconstruction

In ideal reconstruction, . Hence,

. (1.7)

This is obtained if the filter in Fig. 1.1 is an ideal low-pass filter with bandwidth

, i.e.,

. (1.8)

The shape of the pulse for ideal reconstruction can be found by performing

an inverse Fourier transform on (1.8), resulting in [2]

. (1.9)

1.1.4 Reconstruction with Square Pulses

Because the sinc pulse, , has infinite extension in time, it is not practi-cally possible to use the sinc pulse for signal reconstruction. Therefore, other

pulse shapes are used in practice. The most commonly used pulse shape is the

square pulse

, (1.10)

resulting in a piecewise constant reconstructed signal

Figure 1.1 Model system for signal reconstruction.

y t( ) z t( )=

Y( ) P( ) fs Z k2fs( )k =

Z( )= =

fs 2

P( ) T for fs x1 x2>

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0.4

0.30.2

0.1

0

0.1

0.2

0.3

0.4

Input code (x)

INL

INL curve, nonideal DAC

DNLx( ) y x( ) y x 1( )

K---------------------------------- 1=

x 1 x

DNLx( ) INLx( ) INLx 1( )=

DNLx( ) 1< x


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Introduction

14

Sinusoidal test signals are often used for DAC characterization. A typical power

spectral density (PSD) plot of the output from a DAC with a single-tone input is

shown in Fig. 1.9. The largest peak in Fig. 1.9 represents the signal, whereas the

spectral content at other frequencies are unwanted signal impurities. These signal

impurities are usually divided into noise and distortion, even if it can be difficult

to make a clear distinction between the two. Noise is independent of the signal,

whereas distortion is signal dependent [12]. In the frequency domain, noise isoften characterized by a smooth spectral density, whereas (nonlinear) distortion

is visible as distinctive peaks in the output spectrum. There are, however, gray

zones present in the analysis. For example, quantization errors are clearly signal

dependent, but are often considered as sources of noise.

Figure 1.8 DNL curve for the nonideal 4-bit DAC.

Figure 1.9 Single-tone output spectrum for a nonideal 14-bit DAC.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0.70.60.50.40.30.20.1

00.1

0.20.3

Input code (x)

DNL

DNL curve, nonideal DAC

0 0.1 0.2 0.3 0.4 0.5

120

100

80

60

40

20

0

SFDR

Normalized frequency (f/fs)

PSD[dB]

Single-tone output spectrum, nonideal DAC


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Performance Metrics

15

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is used to characterize how well the signal can be

distinguished from the noise. SNR is defined as

, (1.27)

where is the signal power and is the noise power.

Signal-to-Noise-and-Distortion Ratio

If a large amount of distortion is present in the output, the signal quality is better

characterized with the signal-to-noise-and-distortion ratio (SNDR, in some litera-

ture abbreviated SINAD). SNDR is defined as

, (1.28)

where is the total power for the noise and the distortion.

Effective Number of Bits

If a full-scale sinusoid is applied at the input of an ideal -bit DAC, for which

the only errors are caused by quantization, the SNDR is approximately [11]

. (1.29)

Using (1.29) as a starting point, the effective number of bits (ENOB) for a noni-

deal DAC is defined as

. (1.30)

Spurious-Free Dynamic Range

Nonlinearities in the DAC give rise to harmonic distortion. The spurious-free

dynamic range (SFDR) measures the linearity of a DAC according to

, (1.31)

where is the power of the largest spurious tone at the DAC output. The SFDR

is indicated in Fig. 1.9.

SNRPsignalPnoise----------------=

Psignal Pnoise

SNDRPsignal

Pnd----------------=

Pnd

N

SNDR 6.02N 1.76 dB+

ENOB SNDR 1.76

6.02--------------------------------=

SFDRPsignal

Pls----------------=

Pls


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Introduction

16

Multi-Tone Power Ratio

Nonlinear systems, as opposed to linear systems, cannot be fully characterized by

their response to single-tone signals [13]. Therefore, the single-tone performance

metrics described above are insufficient if the DAC is used in a multi-carrier

application. The multi-tone power ratio (MTPR) measures the linearity of a DAC

when subject to a multi-tone input. A multi-tone signal

(1.32)

for belonging to some interval , is used as an input. and are chosen

such that the signal becomes a relevant test signal for a given application. The

amplitudes are chosen equal for all but one, for which the amplitude is set

to zero. Intermodulation caused by the DAC nonlinearities give rise to a spurious

tone at the frequency for which the amplitude was set to zero. The MTPR is

defined as the power ratio between one of the wanted tones and this spurious

tone, as indicated in the multi-tone spectrum in Fig. 1.10.

In a single-tone test, the only relevant parameters are the amplitude and the fre-

quency of the test tone. In an MTPR test, however, the degrees of freedom are

higher. Besides the amplitude, the resulting MTPR is depending on which tone

that has zero amplitude, and also the mutual phase differences between the other

tones. Hence, it is easier to set up and interpret the result from a single-tone test.

Therefore, the single-tone performance metrics are often used, even if they giveinsufficient information. In this work, multi-tone tests are used to some extent,

but not as much as single-tone tests.

Figure 1.10 Multi-tone output spectrum for a nonideal 14-bit DAC.

x n( ) ck k0n k+( )sink=

k 0

ck

k

0 0.1 0.2 0.3 0.4 0.5

100

80

60

40

20

0

MTPR

Normalized frequency (f/fs)

PSD[dB]

Multi-tone output spectrum, nonideal DAC


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Converter Architectures

17

1.4 Converter Architectures

An overview of some different DAC architectures is given in this section. The

differences between Nyquist-rate and oversampled DACs are outlined in

Sec. 1.4.1. The current-steering, charge-redistribution, R-2R ladder, and resistor-string DAC architectures are discussed in Sec. 1.4.2-Sec. 1.4.5. Common to these

architectures is that they perform a memory-less mapping from the digital input

to the analog output. They are commonly referred to as flash or parallel convert-

ers [14], since the conversion of an input sample is performed during one clock

cycle. In DACs, outlined in Sec. 1.4.6, noise-shaping techniques are usedtogether with oversampling to allow the signal to be reconstructed with a flash

DAC having fewer input bits than the input signal. Due to the noise shaping, most

of the quantization noise caused by the additional quantization appears outside of

the signal band and can, hence, be filtered out.

1.4.1 Nyquist-Rate and Oversampled Converters

According to the sampling theorem, it is required that

, (1.33)

where is the bandwidth of the signal. A data converter with just a small

fraction larger than is commonly referred to as a Nyquist-rate converter

[9, 11], whereas a data converter with considerably larger than is

referred to as an oversampled converter [9, 11]. The oversampling ratio (OSR) is

defined as

. (1.34)

There are several reasons for using oversampling. If the number of bits in a con-

verter is large, the quantization noise is approximately white. Hence, the PSD ofthe quantization noise is approximately constant, i.e.,

. (1.35)

From (1.35), it is evident that the total noise power within the signal band

( ) is decreased if is increased. Hence, an oversampled converter has

less quantization noise power within the signal band than a Nyquist-rate con-

verter with the same .

fs 2f0>

f0 fs2f

0 fs 2f0

OSRfs2f0---------=

PSDQ f( ) 2

12------

fs2-----

f f0 fs


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Introduction

18

Another reason for using oversampling is that it simplifies the design of the (ana-

log) anti-aliasing filters for ADCs and image-rejection filters for DACs. The

unfiltered output spectra for a Nyquist-rate DAC and a DAC with are

shown in Fig. 1.11(a) and (b), respectively (the desired spectrum is plotted in

Fig. 1.2(a)). The spectral images that appear around multiples of are betterseparated for the oversampled converter, since its sampling frequency is higher

than that of the Nyquist-rate DAC. Further, the output of the oversampled con-

verter is less distorted by the sinc weighting within the signal band, and the spec-

tral images are better attenuated by the sinc weighting. Hence, requirements on

the filters for attenuation of the spectral images is lower for the oversampled con-

verter than for the Nyquist-rate converter. The relaxed filter requirements a

allows for larger design margin and/or a reduced filter order compared with the

Nyquist-rate case.

1.4.2 Current-Steering DACs

The current-steering DAC, which is based on the switched-current technique

[15], is suitable for high-speed applications [9, 14, 16] and, therefore, the most

frequently used DAC architecture in wideband communication applications. A

differential current-steering DAC is shown in Fig. 1.12. It consists of a number of

weighted current sources, a number of switches, and two load resistors. Bit of

a digital control word controls a switch that steer the current from the current

source to one of the two load resistors. With ideal switches and current sources,the positive output current is

(1.36)

and the negative output current is

, (1.37)

where denotes the complement of . The differential output current is

. (1.38)

There are also positive, negative, and differential output voltages, which are the

corresponding currents multiplied with the load resistance . In an ideal cur-

rent-steering DAC, each current is given by

, (1.39)

OSR 2=

fs

bll:th

I+ blIll

=

I

bl

Ill

Ill

bl

Ill

= =

bl bl

Idiff I+ I 2 blIll

Ill

= =

RLIl

Il wlIunit=


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19

where is the integer weight of the current source and is the unit current.

If the digital control word represents the DAC input , i.e.,

, (1.40)

(a)

(b)

Figure 1.11 Output spectra from (a) Nyquist-rate DAC and (b) oversampled DAC.

Frequency

|Y(2f)|

Output spectrum, Nyquistrate DAC

8f0

6f0

4f0

2f0 0

2f0

4f0

6f0

8f0

0

A

Frequency

|Y(2f)|

Output spectrum, OSR = 2

8f0

6f0

4f0

2f0 0 2f0 4f0 6f0 8f0

0

A

wl Iunitx

x blwll=


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21

for proper operation. This operational amplifier limits the speed of the circuit,

making the charge-redistribution DAC less suited for wideband applications than

the current-steering DAC. The charges in Fig. 1.13 are given by

(1.44)

and

. (1.45)

The total charge, , on all capacitor plates connected to the negative input of

the operational amplifier is constant over time. is given by

, (1.46)

which, together with (1.44) and (1.45), yields

. (1.47)

In an ideal charge-redistribution DAC, each capacitance is given by

, (1.48)

where is the integer weight of the capacitor and is the unit capacitance.

If the digital control word represents the input as in (1.40), then

Figure 1.13 Charge-redistribution DAC architecture.

Ql VrefblCl=

QL VoutCL=

QtotQtot

Qtot QL Qll+=

Vout

QtotCL---------- Vref bl

ClCL-------

l=

Cl

Cl wlCunit=

wl Cunitx


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CMOS Technology

25

polycrystalline silicon (poly), which is separated from the substrate with a thin

layer of silicon dioxide (oxide). Free electrons in the substrate can be attracted to

the region under the gate and form a conducting channel between the drain and

the source by applying a proper voltage at the gate. The principle of a PMOS

transistor is similar, but the type of doping used is opposite to that of the NMOS

transistor.

The DAC circuits in this work have all been implemented in CMOS technology.

A brief overview of the characteristics of CMOS transistors is given in this sec-

tion.

1.5.1 Large-Signal Models

Simple large-signal models for CMOS transistors [11], assuming long-channel

devices, are presented in this section to illustrate the basic behavior of the

devices. These models are similar to that presented by Shichman and Hodges in

1968 [21]. As device sizes decrease, these models become less accurate. There-

fore, circuit simulators often make use of more elaborate models to obtain results

with higher accuracy, such as the BSIM3 model [22].

(a) (b)

(c) (d)

Figure 1.16 (a) Generalmodulator and (b)modulator with quantizer modeled with anadded error signal. The spectra for the 8-bit input and the 1-bit output of a first-

ordermodulator (OSR = 128) are shown in (c) and (d), respectively.

100

50

0

f0

fs/2

Frequency (log scale)

P

SD[dB/Hz]

Modulator input

100

50

0

f0

fs/2

Frequency (log scale)

P

SD[dB/Hz]

Modulator output


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Introduction

26

A symbol for an NMOS transistor is shown in Fig. 1.17(a). It has four terminals;

gate (G), source (S), drain (D), and bulk (B). In all implementations presented in

this work, the bulk terminal is connected to ground for all NMOS transistors. In

that case, the symbol in Fig. 1.17(b), where the bulk terminal is omitted, can be

used instead. Similar symbols for PMOS transistors are shown in Fig. 1.17(c) and(d), where the omitted bulk terminal in Fig. 1.17(d) implies that the bulk is con-

nected to the supply voltage ( ).

In the simple model, the transistors have three different regions of operation; the

cut-off region, the linear region, and the saturation region. The approximate cur-

rent-voltage relationships for NMOS and PMOS devices are listed in the follow-

ing sections. The model parameters, e.g., carrier mobility and body-effect

constants, for NMOS and PMOS transistor typically have different values. How-

ever, we use the same notation for the two transistor types in order to avoid the

use of additional indices.

NMOS Devices

An NMOS transistor operates in the cut-off region if

, (1.55)

where is the threshold voltage of the transistor. In the transistor model used

here,

(a) (b)

(c) (d)

Figure 1.17 Device symbols for (a) four-terminal NMOS transistor, (b) NMOS transistor

with the bulk connected to ground, (c) four-terminal PMOS transistor, and (d)PMOS transistor with the bulk connected the supply voltage.

VDD

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