VLSI Design & Test Seminar 3/21/2007

Cypress Programmable System-on-Chip (PSoC)

VLSI Design & Test Seminar 3/21/2007

Typical SoC Implementations

Standard microcontrollerLimited configurability of on-chip hardware

Custom ICBuild around hard or soft cores

FPGA with “soft” coresSynthesize CPUs and support functions to target gate array

FPGA with embedded processorsSynthesize support functions to gate array

VLSI Design & Test Seminar 3/21/2007

Freescale MC68HC812A4 microcontroller

Peripheralfunctions are“fixed”, withprogrammablefeatures

VLSI Design & Test Seminar 3/21/2007

Custom PSoC

Functions oftensynthesizedfrom IP “cores”

VLSI Design & Test Seminar 3/21/2007

FPGA SoC implementation with “soft macros” (Xilinx “Picoblaze” uController)

VLSI Design & Test Seminar 3/21/2007

SoC implementation using Xilinx Virtex 4FPGA with embedded PowerPC

VLSI Design & Test Seminar 3/21/2007

Cypress “Programmable System on Chip”(PSoC)

Mixed-Signal Array with On-Chip ControllerM8C 8-bit CPUFlash, RAM & ROM memories (programs, data)Configurable I/O pinsProgrammable interconnects to on-chip modulesSome fixed functions (MACs, I2C, USB/WUSB)Configurable blocks of digital circuitsConfigurable blocks of analog circuits

Lies between fixed-function microcontroller and ASIC/FPGA solutions

VLSI Design & Test Seminar 3/21/2007

PSoC top-level block diagram

ROM & FlashSRAM

Global digital/analoginterconnects

Programmableanalog blocks

Programmabledigital blocks

ProgrammableI/O pins

M8C CPU

Fixed functions

VLSI Design & Test Seminar 3/21/2007

PSoC devices

CYWUSB6953 = CY821x34 PSoC + WUSB6935 Radio

VLSI Design & Test Seminar 3/21/2007

Supervisory ROM (SROM)

Code for booting, flash programming, calibration

VLSI Design & Test Seminar 3/21/2007

PSoC static RAM

RAM organized in pages of 256 bytesCPU has 8 address bitsPage register provides upper address bits

VLSI Design & Test Seminar 3/21/2007

General-purpose I/O pins

Eightprogrammabledrive modes(each pin)

VLSI Design & Test Seminar 3/21/2007

Device pins

Digital blocks

System bus(4 x 8-bit buses)

Digital interconnect

1-to-4 rows ofdigital blocks,4 blocks/row

PSoCDigitalSystem

VLSI Design & Test Seminar 3/21/2007

Digital block architecture

Configure for 5 functions:Timer, CounterPWM generatorCyclic redundancy checkPseudo-random seq. gen.

Digital communications blocks:Master/slave SPIFull-duplex UART

Chainblocks forfunctionwidth > 8.

VLSI Design & Test Seminar 3/21/2007

Digital block data & control registers

Data registers Controlregister

7 function types

VLSI Design & Test Seminar 3/21/2007

Timer & counter functions

Data registers:DR0 = synchronous down-counterDR1 = period register DR2 = capture/compare register

Basic timer: Count down until terminal count; reset & repeat

Input capture: capture time of an event on an input pin (DR0->DR2)

Output compare: trigger an event at a designated time (DR0=DR2)

Counter functionsimilar to timer, except input = “gate” from an input pin

VLSI Design & Test Seminar 3/21/2007

Pseudo-Random Sequence (PRS)/Cyclic Redundancy Check (CRC)

Registers:DR0 = linear feedback shift register (LFSR)DR1 = polynomial for PRS/CRCDR2 = seed value for LFSR

VLSI Design & Test Seminar 3/21/2007

Serial peripheral interface (SPI) function

MOSI MOSIMISO

MISO

SS_ SS_

SCLK SCLK

SPI Master SPI Slave

DR0 = shifterDR1 = TX bufferDR2 = RX buffer

VLSI Design & Test Seminar 3/21/2007

UART functionTransmitter

DR0 = shifter, DR1 = TX bufferReceiver

DR0 = shifter, DR2 = RX buffer10 or 11-bit frame (start + 8 data + parity + stop bits)

VLSI Design & Test Seminar 3/21/2007

Global Digital Interconnect(48-pin pkg)

Input buses: GIE/GIO(pin to core logic)

Output buses: GOE,GOO(core logic to pin)

Even buses connect to pins in P0,P2,P4Odd buses connect to pins in P1,P3,P5

One-to-many mapping.GIO[1]->P1[1],P3[1],P5[1], etc.

VLSI Design & Test Seminar 3/21/2007

Digital block row structure

VLSI Design & Test Seminar 3/21/2007

Digital block row grouping (4 bocks/row)

basic blocks digital communication blocks

VLSI Design & Test Seminar 3/21/2007

Array digitalinterconnect

Interconnects rowsof digital blocks

1 to 4 rows, depending on PSoC device.

Not configurable.

VLSI Design & Test Seminar 3/21/2007

PSoC Programmable Analog Functions

A/D converters, D/A convertersDelta-sigma, successive-approximation, incremental

AmplifiersComparatorsSample & holdFiltersAmplitude modulation/demodulation, FSK modulatorSine-wave generators, DTMF generatorAudio driveEmbedded modem

VLSI Design & Test Seminar 3/21/2007

PSoC Analog System

Continuous-time (CT) blocks

Switched-capacitor(SC) blocks

Referencevoltages

Global analoginterconnect

Input mux

VLSI Design & Test Seminar 3/21/2007

Analog interface system

One per column

16possiblefunctions

For ADC

VLSI Design & Test Seminar 3/21/2007

Analog inputs to SC/CT blocksFrom I/O pins

VLSI Design & Test Seminar 3/21/2007

Analog reference voltages3 internally-fixed reference voltages: RefHi, RefLo, AGND (programmable levels)

Use for ADC. DAC, Comparators, etc.

VLSI Design & Test Seminar 3/21/2007

Continuous Time (CT) PSoC BlockProgrammablegain/attenuationop amp circuits

Instrument amps(with 2 blocks)

Comparators Low-noise/low-offsetop amp

Programmableresistor string

Comparator

To analog bus

Comparatorbus

Local output

Local output

Local output

VLSI Design & Test Seminar 3/21/2007

Example: instrumentation amp(2 CT blocks)

VLSI Design & Test Seminar 3/21/2007

Example: instrumentation amp(2 CT blocks, one SC block)

VLSI Design & Test Seminar 3/21/2007

Switched-Capacitor Blocks

3 arrays of binary-weighted switched capacitors

control movement of charge

Applications:Successive-approximation A/DSigma-delta A/DIncremental A/DCapacitor D/AFilters Switch settings programmed in registers

VLSI Design & Test Seminar 3/21/2007

Analog switched-capacitor block (type C)Feedback pathcap array

User-selectablecap arrays.

To otheranalog blocks

Comparatorbus

Local output

VLSI Design & Test Seminar 3/21/2007

PSoC System Resources

VLSI Design & Test Seminar 3/21/2007

Multiply-Accumulate (MAC)

8 x 8

VLSI Design & Test Seminar 3/21/2007

I2C (Inter-IC) Bus Block

2-wire communication linkSerial data (SDA), serial clock (SCK)

Supports simple networkingMultiple-master with fixed-priority arbitrationSpeeds of 100kbps, 400Kbps, 3.4 MBps

VLSI Design & Test Seminar 3/21/2007

PSoC Designer – Device Editor (select blocks)

VLSI Design & Test Seminar 3/21/2007

PSoC Designer - Interconnect View

VLSI Design & Test Seminar 3/21/2007

PSoC Designer – Application View