Date post: | 17-Jan-2016 |
Category: |
Documents |
Upload: | lora-clarke |
View: | 215 times |
Download: | 0 times |
CYPRESSSEMICONDUCTOR
2 Cypress Confidential
QDR Class vs DDR III (DRAM)
88
88
DDR3SDRAMDDR3
SDRAMQDR2+SRAM
QDR2+SRAM
99
99
99
99
99
99
99
99
14 Multiplexed Address Bus (Row & Col) 14 Multiplexed Address Bus (Row & Col)
3 Address Bus (Bank) 3 Address Bus (Bank)
20 Address Bus (Broadside) 20 Address Bus (Broadside)
Data
In Data
In Data Out Data Out
Common I/O Common I/O
QDR2 supports simultaneous Reads and WritesBoth at Double Data Rate for 4.3GB/s/Port x 2 Ports = 9.6GB/s @533MHz
QDR2 supports simultaneous Reads and WritesBoth at Double Data Rate for 4.3GB/s/Port x 2 Ports = 9.6GB/s @533MHz
DDR3 supports separate Read and Writeat Double Data Rate for 2.13GB/s/Port x 1 Port = 2.13GB/s @533MHz
DDR3 supports separate Read and Writeat Double Data Rate for 2.13GB/s/Port x 1 Port = 2.13GB/s @533MHz
Broadside addressing offers same access time from anywhere in the memory core
Broadside addressing offers same access time from anywhere in the memory core Multiplexed addressing causes variable
access times in the memory core
Multiplexed addressing causes variable access times in the memory core
3 Cypress Confidential
Stratix IV FPGA Memory ComparisonQDR vs DDRIII DRAM
• 2X Pin Bandwidth Improvement• 2X Pin Bandwidth Improvement
• 4X Data Rate Improvement• 4X Data Rate Improvement
Source Altera Stratix IV Data SheetSource Altera Stratix IV Data Sheet
Memory Type Maximum Data Rate (Per Pin) Maximum Clock Frequency
DDR3 SDRAM 1067Mbps 533MHz
QDRII+ SRAM 1400Mbps 350MHz
QDRII+ SRAM @65nm 1800Mbps 450MHz
QDRII+ SRAM @65nm 2132Mbps 533MHz
Stratix IV QDR interface can run at 533MHz if QDR runs at 533MHz
Stratix IV FPGA Maximum Clock Rate Support for External Memory Interfaces
Memory Type Bandwidth Comparison Maximum Clock Frequency
DDR3 SDRAM (x16) 2.13GBs 533MHz
QDRII+ SRAM (x36) 6.3GBs 350MHz
QDRII+ SRAM @65nm 8.1GBs 450MHz
QDRII+ SRAM @65nm 9.6GBs 533MHz
4 Cypress Confidential
• (2) DDR3 x16 + (1) DDR3 x8)• DIMM Module Socket• (1) QDRII+ x36
• 4.4 x Latency Improvement
Stratix IV FPGA Memory ComparisonQDR vs DDRIII DRAM (cont)
Memory Type Power Comparison Maximum Clock Frequency
DDR3 SDRAM (x16) 290ma x 2= 580ma 533MHz
QDRII+ SRAM (x36) 1420ma 533MHz
Memory Type Package Comparison
DDR3 SDRAM (x16) 100-Ball FBGA(9 x 13.3 x 1.1mm)
QDRII+ SRAM (x36) 165-Ball FBGA(15 x 17 x 1.4 mm)
Reduced Board Space
Memory Type Latency
DDR3 SDRAM (x16) For 6-6-6 TAA 20nsQDRII+ SRAM (x36) For 2.5 TAA= 4.53ns
5 Cypress Confidential
•SRAM Access is Deterministic
Stratix IV FPGA Memory ComparisonQDR vs DDRIII DRAM (cont)
Memory Type Deterministic Data
DDR3 SDRAM (x16) No (Due to Refresh)QDRII+ SRAM (x36) Yes
SER Logical Single Bit Upset (LSBU) 400(FIT/Mb) Logical Multi Bit Upset (LMBU) 0(All temp.) Physical Single Bit Upset (SBU) 280
Physical Multi Bit Upset (MBU) <20% of SBU<0.1SEL (FIT/Mb) (All temp.)
144Mb QDRII+ SRAM
6 Cypress Confidential
Additional Features to Compare “Cost of Ownership”
• 1 Chip vs Multi Chip Module (Units, sockets)• Added cost for Module Printed Circuit Board • Cost of High Frequency Socket• Soldering vs Socket
• Support for system level Error Correction (ECC) to improve reliability to field related failures• Soft error detection and correction• Self Healing for some Hard and Soft bit errors• 1 SRAM supports 36b• 3 DRAM required for 36b (16+16+4)