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1. VHDL Code For Half Adder By Data Flow Modelling library ieee; use ieee.std_logic_1164.all; entity half_adder is port(a,b: in bit;s,c: out bit); end half_adder; architecture half_adder of half_adder is begin s<=(a xor b); c<=(a and b); end half_adder; 2. VHDL Code For Full Adder By Data Flow Modelling library ieee; use ieee.std_logic_1164.all; entity full_adder is port(a,b,c: in bit;sum,carry: out bit); end full_adder; architecture full_adder of full_adder is begin sum<=((a xor b) xor c); carry<=((a and b) or (b and c) or (c and a)); end full_adder; 3. (a) VHDL Code For Half Subtractor By Data Flow Modelling library ieee; use ieee.std_logic_1164.all; entity half_subtractor is port(a,b: in bit; difference,borrow: out bit);
