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decoder implementation with Ladder Logic

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Indudtrial Electronics
3
ABBOTTABAD Lab Assignment#10 Subject: Industrial Electronics Submitted By: Naveed Mazhar FA09-BEE-143 Submitted To: Sir Muhammad Sajjad Durani Date: 15 th November, 2012
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Page 1: decoder implementation with Ladder Logic

ABBOTTABAD Lab Assignment#10

Subject: Industrial Electronics

Submitted By:

Naveed Mazhar FA09-BEE-143

Submitted To:

Sir Muhammad Sajjad Durani

Date: 15th

November, 2012

Page 2: decoder implementation with Ladder Logic

DECODER A decoder is a combinational circuit which converts binary information from n input

lines to 2ⁿ unique output lines.

Truth Table: Logic table for 3 to 8 decoder is given by:

Inputs Outputs X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

GATE LEVEL IMPLEMINTATION (3 to 8 Decoder): The circuit diagram of 3 to 8 decoder is:

Page 3: decoder implementation with Ladder Logic

LADDER DIAGRAM: Ladder logic diagram of 3 to 8 decoder is given by:


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