Design and Implementation of a Voltage Step Down DC DC...

Design and Implementation of a

Modular Low-Voltage Step-Down DC-to-DC Transformer

with Galvanic Isolation

by

Keegan Speidel

Eric Collett

Jordan Lucht

Shujin Qiu

Final report submitted in partial satisfaction of the requirements for the degree of

Bachelor of Science

Electrical and Computer Engineering

University of Manitoba

Faculty Supervisor:

Dr. Carl Ho

Spring 2018

© Copyright by Keegan Speidel, Eric Collett, Jordan Lucht and Shujin Qiu, 2018

DC TO DC STEP DOWN TRANSFORMER

i

Abstract

The purpose of this project was to design a modular system for stepping

down input voltage while simultaneously providing galvanic isolation. To accomplish this,

the project needed to consist of multiple modules connected each containing a 1:1

transformer. The reason for this design was to make a system that can be expanded or

modified as necessary to meet various input/output voltage ratios. An application of this

project is high-speed charging of electric vehicles by connecting to a high voltage source. By

reducing the voltage from the source to the rated voltage of the vehicle, the current can be

increased, allowing for faster charging times. To accomplish these tasks, the project was

divided into multiple sections: transformer design, PET (Power Electronics Transformer)

design, DSP (Digital Signal Processor) programming and PCB (Printed Circuit Board)

design. Circuitry was designed around the transformer, including a current sensor to shut

down the circuit if high current was encountered, opto-couplers to isolate electrical

components from each other and boost converters to change input voltages to those

required by the system. All components would be integrated together on a PCB to make a

single module, and multiple modules are connected together based on the desired voltage

ratio. At time of writing, we cannot comment on the results of this approach due to the late

arrival of our PCBs.


ii

Acknowledgements

We would like to specially thank the following people who provided guidance and

contributions to this project.

We especially want to thank Dr. Carl Ho as our wonderful supervisor of this project.

We would not be able to reach our project’s accomplishments without your sincerity and

suggestions.

We would like to thank the PHD students Dong Li and King Man Siu in the Power

Systems group for supporting us and providing guidance for this project.

We also would like to thank Ms. Aidan Topping for providing technical writing advice

for our projects.

We would like to thank Professor Daniel C. Card for project design assistance.

We would like to thank Kenneth Beigun and Zoran Trajkoski for guiding us in the

PCB design process of this project.

We would like to thank Mr. Sinisa Janjic for supplying the components from the

Electrical and Computer Engineering technical shop as well as for ordering components we

required for the projects.

Lastly, we like to thank VITEC Electronics Corporation for providing us the half-

bridge transformers and inductors.


iii

Contributions

Shujin Qiu: Transformer designer and final report editor (Section 1)

Jordan Lucht: PET module designer (Section 2)

Keegan Speidel: DSP programmer (Section 3)

Eric Collett: PCB design and final report editor (Section 4)

All team members were involved in the testing of individual modules and the full

project.


iv

Table of Contents

Abstract ................................................................................................................................ i

Acknowledgements ............................................................................................................. ii

Contributions...................................................................................................................... iii

List of Tables ...................................................................................................................... vi

List of Figures ................................................................................................................... vii

Nomenclature ................................................................................................................... viii

Project Summary ................................................................................................................. 1

Module Design Summary ................................................................................................... 2

Section 1: Transformer Design Procedure .......................................................................... 4

1.1: Specification of Design Parameters ......................................................................... 4

1.2: Calculation of Volt-Amp Rating, S .......................................................................... 5

1.3: Selection of Core Material, Shape and Size ............................................................ 5

1.4: Core Flux Density and Saturation Current .............................................................. 8

1.5: Magnetic Reluctance ................................................................................................ 9

1.6: Determining Losses ................................................................................................11

1.7 Testing: .................................................................................................................... 13

1.8 Inductance Measurements: ...................................................................................... 14

1.9: Performance ........................................................................................................... 16

Section 2: PET Cell Design Process: ................................................................................ 17

Description of Section and Requirements ..................................................................... 17

2.1: Initial Plan .............................................................................................................. 17

2.2: Changes Made ........................................................................................................ 18

2.3: Part Selection ......................................................................................................... 21

2.4: Power Requirements .............................................................................................. 22

2.6: Results .................................................................................................................... 27

Section 3: DSP Programming ........................................................................................... 28

3.1: DSP Requirements and Selection .......................................................................... 28

3.2: DSP Design Considerations ................................................................................... 29

3.3: Current Sensor Design ........................................................................................... 34


v

3.4: Final Remarks ........................................................................................................ 36

Section 4: PCB Design...................................................................................................... 36

4.1: Board Layout ......................................................................................................... 36

4.2: Input and Output of PCB Modules ........................................................................ 39

4.3: PCB Trace Calculations ......................................................................................... 42

4.4: PCB Design Software Used ................................................................................... 45

4.5: Final Remarks ........................................................................................................ 45

Conclusion: ....................................................................................................................... 46

References: ........................................................................................................................ 47

Appendix A: Final Project Cost Breakdown ..................................................................... 52

Appendix B: Full Project Schematic................................................................................. 54

Appendix C: Testing Proto Board Setup ........................................................................... 55

Appendix D: DSP Code .................................................................................................... 56


vi

List of Tables

Table S - 1 Proposed Performance Metrics ................................................................................................. 1

Table 1 - 1: Core Characteristics ...................................................................................................................... 7

Table A - 1: G08 final project cost breakdown ........................................................................................ 53


vii

List of Figures

Figure S - 1: System Configuration ................................................................................................................. 1

Figure 1 - 1: Relative core loss versus flux density ............................................................................... 12

Figure 1 - 2: Transformer equivalent circuit ........................................................................................... 14

Figure 1 - 3: Transformer equivalent circuit-2 ....................................................................................... 14

Figure 1 - 4: Primary side voltage ................................................................................................................ 16

Figure 2 - 1: Connection scheme for PET cells. ....................................................................................... 17

Figure 2 - 2: Initial design of the PET cell. ................................................................................................ 18

Figure 2 - 3: Design change to reduce current stress on resonant capacitor. [26] ................... 19

Figure 2 - 4: IR2110 datasheet gate driver implementation [21] ................................................... 19

Figure 2 - 5: DSP Output/Opto-coupler Input ......................................................................................... 24

Figure 2 - 6: Opto-coupler Output/IR2110 Input .................................................................................. 24

Figure 2 - 7: Top(yellow) and bottom(blue) MOSFET gate signals ................................................. 25

Figure 2 - 8: MOSFET load voltage, 100 V square wave ...................................................................... 26

Figure 2 - 9: Measured voltage of transformer primary and secondary winding ..................... 26

Figure 2 - 10: Rectified waveform ................................................................................................................ 27

Figure 3 - 1: Main Code Flowchart .............................................................................................................. 31

Figure 3 - 2: DSP Pin Diagram ....................................................................................................................... 32

Figure 3 - 3: Current sensor test ................................................................................................................... 33

Figure 3 - 4: Current sensor electrical diagram [28] ............................................................................ 35

Figure 4 - 1: Final PCB layout ........................................................................................................................ 36

Figure 4 - 2: Module connection diagram ................................................................................................. 41

Figure 4 - 3: Top Copper Layer ...................................................................................................................... 43

Figure 4 - 4: Bottom Copper Layer .............................................................................................................. 44

Figure B - 1: Full Project Schematic ............................................................................................................ 54

Figure C - 1: Testing Proto Board Setup .................................................................................................... 55


viii

Nomenclature

List of symbol types used in equations.

Symbol Description Use

Acore core cross-section area core parameter for transformer

Ae effective magnetic cross section design parameter for transformer

AL inductance factor design parameter for transformer reluctance

AN Winding cross section design parameter for transformer

AR Resistance Factor design parameter for transformer

Aw winding window area core parameter for transformer

B Flux Density design parameter for transformer

Bsat Saturated Flux Density core parameter for transformer

d Diameter copper wire parameter

f Operating frequency design requirement

F magnetic field force design parameter for transformer reluctance

H magnetic field Strength design parameter for transformer saturation situation

IL operating current design parameter for calculating losses of transformer

Ipri Rated rms primary current design parameter for transformer

Jrms current density in the conductor design parameter for transformer

kcu copper fill factor design parameter for transformer conductor

L inductance design parameter for transformer reluctance

le Effective magnetic path length core parameter for transformer

lN average length of the turn design parameter for calculating losses of transformer

LN Average length of the turn design parameter for transformer

n Transformer turns ratio design requirement

N Transformer winding turns design parameter for transformer

N87 Core Material Core material for transformer design

Pcu copper loss design parameter for the losses of transformer

Pv Relative Core Loss core parameter for transformer

R Reluctance design parameter for calculating losses of transformer

Rac ac effective resistance of the conductor design parameter for transformer conductor


ix

Rc core reluctance core design parameter for transformer

Rcu conductor resistance design parameter for calculating losses of transformer

Rdc dc effective resistance of the conductor design parameter for transformer conductor

Rg reluctance of the air gap design parameter for calculating losses of transformer

Rtot total reluctance design parameter for calculating losses of transformer

S The Volt-Amp rating design parameter for transformer

Ta ambient temperature design parameter

Ts body temperature design parameter

Vpri Rated rms (root-mean squared) primary voltage

design parameter for transformer

ϕ magnetic flux design parameter for transformer reluctance

𝛺𝑇𝑂𝑇 total resistance

design parameter for calculating losses of transformer

𝜇𝑟 , 𝜇𝑒 Relative effective permeability

design parameter for transformer reluctance

𝜂 PET cell efficiency design parameter for PET cell

𝑃𝑖𝑛 Power input to PET cell measured power input to PET cell

𝑃𝑜𝑢𝑡 Power output of PET cell measured power output of PET cell

𝑉𝑜𝑢𝑡 Voltage output of PET cell measured voltage out of PET cell

𝑅𝑙𝑜𝑎𝑑 Resistance of load resistance of load

List of special characters used for physical constants.

Symbol Description Value

𝜇0 permeability of free space 4π * 10-7 H/m

DC TO DC STEP DOWN TRANSFORMER 1

Project Summary

The goal of this project was to design and implement a low voltage, modular, DC-to-

DC step-down transformer with galvanic isolation. The system steps down 300 Volts at

1 kW power input to 100 Volts with a 90% power transfer efficiency. The system consists of

three identical one to one DC transformer modules. The inputs of the modules are

connected in series, and the outputs are connected in parallel. With this configuration, it is

possible to modify the system to add additional cells for different input voltage levels.

Figure S - 1: System Configuration

Performance Metrics

Table S - 1 Proposed Performance Metrics

Single Module

Proposed

Metric Revised Metric Tested Metric

Power Rating 333 W 166 W 56 W

Efficiency 90% 90% 81%

Input Voltage 100 V 100 V 100 V

Output Voltage 100 V 50 V 44.3 V

Temperature Range 50°C to -

30°C 50°C to -30°C 50°C to -30°C

Input Current 3.33 A 1.66 A 0.561 A

Output Current 3.33 A 3.33 A 1.036 A

PET Cell 1

PET Cell 2

PET Cell 3

+

𝑉𝑆,1

+

𝑉𝑆,2

+

𝑉𝑆,3

+

𝑉𝑂,1

+

𝑉𝑂,2

+

𝑉𝑂,3

+

𝑉𝑆

+

𝑉𝑂


2

Module Design Summary

All modules are identical and consist of 5 parts: a DSP (Digital Signal Processor)

controller, a resonant invertor, a high frequency transformer, and a full bridge rectifier.

These are all designed and integrated together on a PCB (Printed Circuit Board).

The resonant convertor switches the input DC signal and feeds the switched signal

into a resonant tank to produce a high frequency AC signal that can then be transformed by

the transformer. This signal has a frequency of 100 kHz, based on the recommended

transformer operating frequency (also 100 kHz). The MOSFETS used for switching the

signal require a gate driver circuit to increase the switching signal to a voltage level capable

of switching the MOSFETS.

The transformer included in each module is a 1:1 ferrite core transformer. This

transformer is used due to the low core losses at a frequency of 100 kHz. Each transformer

takes a 100 kHz AC wave as an input and outputs an almost identical wave to the full bridge

rectifier.

The full bridge rectifier receives the high frequency AC voltage wave from the

transformer and converts it to a DC voltage with some slight ripple. The ripple of this

rectifier is controlled by a large smoothing capacitor, further smoothing the output signal.


3

The DSP controls two main functions of the circuit; the switching signals for the

MOSFETS and the current sensor. The DSP outputs two PWM (pulse-width modulated)

square waves that are connected to the MOSFETS via opto-couplers. The opto-couplers

protect the DSP from any shorts in the power circuit. The DSP also monitors the current

entering the primary side of the transformer. A Hall Effect sensor is used to isolate the DSP

from the power circuit. If the measured current enters a dangerous operating range, the

DSP will disable the switching signals, thereby terminating all power input into the

transformer.

The PCB integrates all the above systems together and connects appropriate

modules closely together to reduce noise in the circuitry. The PCBs in each module consist

of two layers, with most copper traces placed on the top layer of the board. Components are

placed to minimize the total distance of copper traces on the PCB.


4

Section 1: Transformer Design Procedure

The magnetic transformer is an indispensable part of most power electronic

converter designs. Due to flux density being inversely proportional to frequency, the

operating frequency can be increased to reduce transformer size. High frequency power

electronic transformers are used in power grids to carry out voltage transformation;

isolating loads from the power grid and improving overall power quality. For this project

the main purpose of the power electronic transformer is to achieve galvanic isolation [1]

between electrical subsystems by which non-direct current can flow and possess different

ground potentials. In summary, this allows for galvanic isolation of a DC source from its

load.

Transformer design considerations [2] consisted of the magnetic material selection,

electrical loss calculations and performance testing. The high frequency transformer was

designed and built based on the procedure summarised in this section.

1.1: Specification of Design Parameters

The design parameters for the transformer are the following:

a. Rated rms (root-mean squared) primary voltage: 𝑉𝑝𝑟𝑖= 100 V

b. Rated rms primary current: 𝐼𝑝𝑟𝑖 = P/V = 333.33 W/100 V = 3.33 A

c. Transformer turns ratio: n = 1:1

d. Operating frequency: f = 100 KHz

e. Maximum body temperature, Ts of the transformer and the maximum ambient

temperature (Ta = 50°C)

The first four parameters were determined through design calculations for the power

electronic converter circuit where the transformer is used. The maximum temperatures

were determined by the other temperature-limited components, the diodes and MOSFETs


5

that are used in the circuit. The operating temperature range of the transformer [3] is -40°C

to 125 °C.

1.2: Calculation of Volt-Amp Rating, S

The Volt-Amp rating, S, of the transformer is defined as the product of rated rms

voltage 𝑉𝑝𝑟𝑖 and current 𝐼𝑝𝑟𝑖 .

𝑆 = 𝐼𝑝𝑟𝑖 ∗ 𝑉𝑝𝑟𝑖 (1.1)

The Volt-Amp rating of the transformer is S= (100 V)*(3.33 A) = 333.33 VA.

Voltage in equation (1.1) can be expressed in terms of transformer design

parameters such as flux density, frequency, core area and number of turns in the primary

winding. Current can be expressed in terms of current density and primary conductor cross

sectional area if the influence of the skin effect is neglected. Taking the winding area and

copper fill factor (kcu) into consideration, the Volt-Amp rating can be expressed as shown

below [4]:

𝑆 = 𝐼𝑝𝑖𝑟 ∗ 𝑉𝑝𝑟𝑖 = 𝑁𝑝𝑟𝑖 ∗ 𝐴𝑐𝑜𝑟𝑒 ∗𝑤∗𝐵

√2∗ 𝐽𝑟𝑚𝑠 ∗ 𝐴𝑐𝑢 (1.2)

𝑆 = 𝐼𝑝𝑟𝑖 ∗ 𝑉𝑝𝑟𝑖 = 2.22 ∗ 𝑘𝑐𝑢 ∗ 𝑓 ∗ 𝐴𝑐𝑜𝑟𝑒 ∗ 𝐴𝑤 ∗ 𝐽𝑟𝑚𝑠 ∗ 𝐵 (1.3)

1.3: Selection of Core Material, Shape and Size

• Core Material

Based on the operating frequency of 100 kHz high frequency, a ferrite material was

chosen for the core. Ferrite materials are oxide mixtures of iron and other magnetic

elements that have large electrical resistivity but low saturation flux densities [5]. Due to


6

the high electrical resistivity, there is no significant eddy current loss and only hysteresis

loss in the core needed to be considered. Therefore, a ferrite core was chosen for operating

at high frequencies (greater than 10 kHz).

• Core Shape

Two “E” shaped cores were selected to make up the transformer core based on prior

experience with those shapes, their cost and availability.

• Wire Type

The conductor windings for the transformer are made from copper. Selection of the

conductor type in a transformer depends on the operating frequency and the importance of

the eddy current losses (winding loss) in the windings. The reason why copper conductors

are the first choice for the most inductors and transformer windings is due to the high

ductility of the copper, which makes it easy to bend into tight windings around the

magnetic core. Additionally, the high conductivity helps minimize the total copper volume

and mass required for these windings. The copper fill factor can be calculated from the

copper cross-section and winding window area. The copper fill factor is used for selecting

the core size and calculating the winding losses. The volume of the copper windings and

the operating temperature also affect the copper winding losses and magnetic losses. This

is explained in more detail in Section 1.6.

• Core size

Core size is chosen based on the Volt-Amp rating of the desired transformer. A table of

core characteristics involved in transformer design is summarized in Table 1-1 shown

below. These can be found in the datasheet of the transformer core [6].


7

Table 1 - 1: Core Characteristics

Characteristics Symbols Value Units

Coil Former

Winding cross-section AN 315.6 mm2

Average length of the turn LN 96 mm

Resistance factor AR = 𝑅𝑐𝑢

(𝑁)2 10.5

Bobbin bw bw 8.6 mm

Bobbin height hw 36.8 mm

Core

Material N87

Maximum core flux density B = 0.8𝐵𝑠𝑎𝑡 320 mT

Effective magnetic path length 𝑙𝑒 127 mm

Effective magnetic cross section 𝐴𝑒 280 mm2

Inductance factor (ungapped) AL = 𝐿

(𝑁)2 4450 nH

Relative effective permeability (ungapped) 𝜇𝑒 1600

Relative core loss (ungapped) 𝑃𝑣 < 3.20

(100 mT, 100

kHz, 100 °C)

W/set

Inductance factor (1.0 ±0.05 gapped) AL 393 nH

Relative effective permeability

(1.0 ±0.05 gapped)

𝜇𝑒 141

Copper wire 18 AWG MW 35-C HY [7]

Diameter d 1.024 mm

The selected core ensures the value of S computed by equation (1.3) is larger than

the designed Volt-Amp rating of 333.33 VA.


8

From equation (1.3),

𝑆 = 𝐼𝑝𝑟𝑖 ∗ 𝑉𝑝𝑟𝑖 = 2.22 ∗ 𝑘𝑐𝑢 ∗ 𝑓 ∗ 𝐴𝑐𝑜𝑟𝑒 ∗ 𝐴𝑤 ∗ 𝐽𝑟𝑚𝑠 ∗ 𝐵 = 2.78 ∗ 104 ∗ √𝑘𝑐𝑢 ∗ 𝑅𝑑𝑐

𝑅𝑎𝑐

The copper fill factor kcu can be determined based on the core and copper wire

selection (0.136 unitless). Thus, the selection of the core and copper wire meet the

requirements since the calculated 𝑆𝑀𝐴𝑋 is greater than required S.

1.4: Core Flux Density and Saturation Current

Transformer performance is constrained by the magnetic flux limitation of the core.

For ferromagnetic core transformers to work properly, the flux needs to be continuously

changing. This change in flux induces a voltage in the secondary winding. However,

ferromagnetic materials cannot handle infinite magnetic flux densities. The flux tends to

saturate at a certain level, meaning that a further increase in the magnetic field does not

lead to proportional increase in magnetic flux [8]. Furthermore, the flux stops increasing

with increasing primary “magnetic current”. When the primary winding receives excessive

applied voltage the “magnetic current”, the flux in the core reaches saturation level of a

peak AC sine wave cycle. Hence, voltage induced in the secondary winding does not remain

sinusoidal due to harmonics created in the secondary side of the transformer. These

undesired harmonics will cause problems in the power system including overheating,

power loss, reduced efficiency and even damage to the transformers. Therefore, it is

important to eliminate the saturated magnetizing current during transformer design to

ensure the transformer is able to function properly under the operating current.

The equations used to determine the transformer core saturation magnetizing

current are shown below. Choosing an air gap length of 1mm ± 0.05mm and the number of

the turns actually wound of N = 52 for both the primary and secondary side of the

transformer.


9

𝑀𝑎𝑔𝑛𝑒𝑡𝑖𝑐 𝐹𝑖𝑒𝑙𝑑 𝑆𝑡𝑟𝑒𝑛𝑔𝑡ℎ: 𝐻 =𝐵

𝜇𝑒 ∗ 𝜇0= 1806.07

𝐴

𝑚 (1.4)

𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡: 𝐼 = 𝐻 ∗ 𝑙𝑒

𝑁= 4.41 𝐴 (1.5)

The saturation current can also be calculated from the effective magnetic cross

section 𝐴𝑒 and inductor factor AL, found in the data sheet of the core, as shown below. The

saturation current calculated is the same as the current calculated above based on the

magnetic field strength.

𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡: 𝐼 = 𝐵 ∗ 𝐴𝑒

𝐴𝐿 ∗ 𝑁= 4.41 𝐴 (1.6)

The calculations for the saturation current indicate that this transformer can

support a 4.41 A current with a 1.0 mm air gap. This current meets the requirements of a

3.33 A operating current required for the design.

1.5: Magnetic Reluctance

Magnetic reluctance is defined as the ratio of the magnetic field force (F) in a

magnetic circuit to the magnetic flux in both AC and DC fields. The definition can be

expressed as follows:

𝑅 =𝐹

𝛷 (1.7)

The reluctance of a uniform magnetic circuit can be calculated as:

𝑅 =𝑙

𝜇0 ∗ 𝜇𝑟 ∗ 𝐴 (1.8)


10

Multiple different sized air gaps [9] can be used in the core of the transformer to

reduce the effects of saturation [10]. However, an air gap increases the total magnetic

reluctance. This enables it to store more energy before N2 core saturation becomes

dominant, which effects transformer efficiency.

From equation (1.8), the core reluctance is:

𝑅𝑐 =𝑙𝑒

𝜇0 ∗ 𝜇𝑟 ∗ 𝐴𝑒 = 2.56 ∗ 106

1

𝐻

With an air gap, 𝑙𝑔, of 1 mm the reluctance of the air gap is:

𝑅𝑔 =𝑙𝑔

𝜇0 ∗ 𝐴𝑒 = 2.84 ∗ 106

1

𝐻

The total reluctance is:

𝑅𝑡𝑜𝑡 = 𝑅𝑐 + 𝑅𝑔 = 5.4 ∗ 106 1

𝐻

Hence, the magnetic inductance of the transformer can be calculated:

𝐼𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒: 𝐿 = 𝑁2

𝑅𝑡𝑜𝑡= 500.5 𝜇𝐻 (1.9)

The magnetic inductance can be calculated instead using the inductance factor given

in the datasheet of the core. The AL value of a core configuration is supplied by the

manufacturer. The relationship between inductance and AL in the linear portion of the

magnetization curve is defined to be:

𝐼𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒: 𝐿 = 𝐴𝐿 ∗ 𝑁2 (1.10)

The inductance if no air gap is present is calculated using the following.

𝐼𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒: 𝐿 = 𝑁2

𝑅𝐶= 𝐴𝐿 ∗ 𝑁2 = 12.03 𝑚𝐻


11

1.6: Determining Losses

The two main components for power electronic transformer losses that need to be

considered are no-load losses and load losses [11].

No-load losses occur in the transformer core whenever the transformer is energized,

it is also called iron losses or core losses. The no-load losses are composed of hysteresis

losses and eddy current losses.

Hysteresis losses are associated with hysteresis in the transformer core. It is caused

by the movement of magnetic domains in the core being magnetized and demagnetized by

alternation of the magnetic field where not all the energy of the magnetic field is returned

to the power circuit when the magnetic field force is removed [12]. This energy is normally

dissipated in the core as heat. These losses depend on the type of the material used to build

a core, the AC flux density and the operating or switching frequency.

When the core is energized, the changing magnetic fields induce circulating loops of

current called eddy currents. As these current loops flow perpendicular to the magnetic

axis and produce the I2R losses in the magnetic material known as eddy current losses [13].

The eddy currents cause the secondary magnetic field produced to oppose the applied

primary magnetic field. These opposing fields tend to screen the interior of the core from

the applied primary field, resulting in the total magnetic field in the core decays

exponentially with distance towards the centre of the core, also known as skin effect

limitations [14]. Similar to the hysteresis loss, eddy current loss also increase the

temperature of the magnetic material. The magnitude of the current can be reduced by

splitting the solid core into thin laminations in the plane parallel to the magnetic field. Eddy

current loss can also be reduced by using a magnetic material with high resistivity such as

silicon, steel, or ferrite. For this reason, most magnetic cores tend to be made of ferrite for

power electronics applications.


12

Core manufacturers provide detailed information about core losses [15], usually in

the form of graphs of specific loss type as a function of flux density at a given frequency and

temperature as shown in the Figure 1-1.

Figure 1 - 1: Relative core loss versus flux density

The core loss specified in the data sheet of the core is smaller than 3.2 W for an un-

gapped core under 100 kHz operating frequency and 100 mT flux density.

Load losses include heat loss and eddy current loss in the primary and secondary

conductors of the transformer. These losses are commonly called copper losses since most

transformers use copper as the conductor [16]. The heat loss in the transformer windings is

caused by the resistance of the copper conductors. These losses can be reduced by

increasing the cross-section area of conductor or by reducing the winding length. However,

the skin effect also occurs in the conductors used in transformer windings similar to the


13

skin effect limitation for the core. Eddy currents flow in the opposite direction to the

applied current, resulting in the current density being highest at the surface and decaying

exponentially inside of the conductor. This unequally distributed current under high

frequency operation increases the effective resistance, thereby causing eddy current losses

in the windings.

The copper loss can be calculated from the resistance factor located in the data

sheet. The relationship between resistance per unit length of conductor and resistance

factor AN is defined as below:

𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒: 𝑅𝑐𝑢 = 𝐴𝑁 ∗ 𝑁2 (1.11)

The total resistance of the copper windings can be calculated using the average

length of the turn lN, also called mean turn length.

𝑇𝑜𝑡𝑎𝑙 𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒: 𝛺𝑇𝑂𝑇 = 𝐴𝑁 ∗ 𝑙𝑁 ∗ 𝑁 = 0.142 𝛺 (1.12)

Hence, the copper loss can be determined from the operating current.

𝐶𝑜𝑝𝑝𝑒𝑟 𝐿𝑜𝑠𝑠: 𝑃𝐶𝑢 = 𝐼𝐿2 ∗ 𝛺𝑇𝑂𝑇 = 1.57 𝑊 (1.13)

Copper losses can be reduced by using materials with higher electrical

conductivities like copper, using Litz wire to avoid the skin effect, increasing the cross-

sectional area of the conductor and improving the winding technique.

1.7 Testing:

The main testing for the transformer to confirm it is functioning properly for use in

the design can be divided into two parts. One part is testing the leakage inductance and

magnetizing inductance of the primary side. These two inductances affect the design of the


14

resonant converter. The other part is testing the power transfer efficiency of the

transformer.

1.8 Inductance Measurements:

The transformer equivalent circuit is shown in figure 1-2.

Figure 1 - 2: Transformer equivalent circuit

This can be simplified to a transformer with leakage inductance and magnetizing

inductance (primary and secondary inductances) for testing purposes.

Figure 1 - 3: Transformer equivalent circuit-2


15

The equipment for testing the inductance was the HM8118 Programmable LCR

bridge. First, the primary winding was tested with the secondary winding open. The

secondary winding open means the primary winding was in series with the mutual

inductance. The measured inductance is Ll1 + Lmp. Next, test the primary winding with the

secondary winding short-circuited. The secondary winding shorted means secondary

winding is shorted with mutual inductance, therefore the measured inductance is just the

primary inductance, Ll1.

When the first transformer was wound, the primary winding was wound first, then

the secondary winding was wound on the outside of the primary winding. This resulted in

the measured magnetic inductance being very large. A possible reason for this is the

winding technique used created parallel wire, which caused the magnetizing inductance to

behave more like a capacitor.

When winding the second transformer, it was wound in a way to ensure the primary

winding and the secondary winding were side-by-side. The un-gapped leakage inductance

value measured was 219.8 H and the magnetizing inductance was 14.71 mH, which

matched the calculated values of the core.

In order to get a reasonable inductance value for the resonant converter design, our

group received a sponsor from VITEC Electronics Corporation, which supplied us with the

transformers and inductors [17]. This was due to multiple failed trials using our own hand-

wound transformers. The inductance values from the hand-wound transformers were not

suited for the project. The sample transformers from VITEC were successfully tested, and

our group decided to use this transformer for the system integration. The leakage

inductance value measured was 2.6 H and the magnetizing inductance was 268.5 H

using same measurement method described above.


16

1.9: Performance

The two key tests for transformer performance are testing and verifying the ratio of

the transformer turns and transformer performance with an AC source at our design

frequency. The equipment used for testing the inductance was a function generator and AC

amplifier. The function generator generated an AC sinusoidal signal that changed from low

frequency to the specified design frequency, 100 kHz. The signal enters the amplifier, is

amplified and enters the transformer. The output of the amplifier is seen as an AC source

and is connected to the primary side of the transformer. By attaching a load to the

secondary side of the transformer, the performance can be tested.

Figure 1 - 4: Primary side voltage

In Figure SF4, the signal input from the function generator is in yellow. The signal for

the transformer primary side voltage is in blue. The signal for the transformer secondary

side voltage is in pink. Based on these testing results, we can say that the transformer turns

ratio is 1:1. During testing, it was observed that the transformer can properly transfer

power between primary and secondary sides of the transformer with 1 A between 60 Hz

and 100 kHz.


17

Section 2: PET Cell Design Process:

Description of Section and Requirements

The power electronic transformer (PET) circuit for our project required a modular

topology capable of increasing the step-down ratio by increasing the number of cells. Each

cell needed to be connected in series on the input side and in parallel on the output side.

Figure 2 - 1: Connection scheme for PET cells.

The PET cells were constructed identically and were designed around four

requirements: 100 V DC input, 100 V DC output, 3.33A input/output current and 100 kHz

resonant frequency. The efficiency goal for each cell was 90%.

2.1: Initial Plan

Our initial design for the PET cell was a MOSFET half bridge inverter, resonant tank,

hand-wound one-to-one high frequency transformer, full bridge rectifier, and a DSP

controller. A diagram is included below.

PET Cell 1

PET Cell 2

PET Cell 3

+

𝑉𝑆,1

+

𝑉𝑆,2

+

𝑉𝑆,3

+

𝑉𝑂,1

+

𝑉𝑂,2

+

𝑉𝑂,3

+

𝑉𝑆

+

𝑉𝑂


18

Figure 2 - 2: Initial design of the PET cell.

A half bridge inverter was the simplest way to create a 100 V square waveform,

which would be smoothed into a 100 V AC waveform by the resonant tank circuit. An AC

waveform would be induced on the secondary side of the transformer and converted back

to DC by the full bridge rectifier. A full bridge rectifier was chosen to reduce output voltage

ripple as much as possible.

2.2: Changes Made

There was one change made to the initial design of the PET cell in figure 2-2. After

preliminary testing at high current, module efficiency was discovered to be significantly

below expected performance. Upon further research, it was discovered that a different

topology could increase our efficiency [26]. An additional resonant capacitor was

connected between the source and transformer primary winding. This reduced current

stress on the resonant tank circuit. By reducing the size of capacitors by 50%, the resonant

frequency was not affected. [26]

+

𝑉𝑆,1

+

𝑉𝑂,1

Inverter RectifierHF Transformer

Controller


19

Figure 2 - 3: Design change to reduce current stress on resonant capacitor. [26]

The control system was also changed and required multiple iterations. Initially, the

inverter MOSFETS were controlled directly by a micro controller which was programmed to

output two square waves with a 180⁰ phase difference and 50% duty cycle. There were

multiple problems with this design.

The first issue encountered was that the top MOSFET could not be driven properly

during conduction. As soon as conduction begins, the source voltage becomes ~100 V,

meaning the gate signal of the top MOSFET must be Vth + 100V. This introduced a need for a

gate driver circuit capable of supplying ~110 V to the top MOSFET, which we found in the

IR2110 [21] with a boost-trap-cap configuration.

Figure 2 - 4: IR2110 datasheet gate driver implementation [21]


20

The IR2110 chip is supplied by 15 V DC (VCC) and 5 V DC (VDD) supplies, high and

low control signals, and a common (COM) signal. The capacitors (a 100 uF electrolytic

capacitor and 0.1uF ceramic capacitor in parallel) between VB and VS charge to 15 V,

boosting VB to 115 V during top MOSFET conduction. HO will pulse voltage VB reference to

COM when HIN receives a pulse. Using this technique, the top MOSFET can be controlled

regardless of the source voltage.

We also realized that using a gate driver circuit could address the difference in

ground voltages across multiple modules. For example, in the third (top) module, the power

ground is 200 V. By setting the COM pin on the IR2110 to 200 V, the HO pin can pulse the

required 315 V to the top MOSFET.

In addition to the gate driver circuit, the difference in ground voltages made an

isolation circuit a requirement. Connecting the DSP controller to a non-zero ground was not

an option for our choice of controller, therefore we needed to design a circuit that would

allow us to reference the DSP to any of our power grounds. The Fairchild FODM8071 opto-

couplers [22] were used for both high and low MOSFETs to accomplish this. The five-pin

device is supplied with 5V logic signal and zero ground from the DSP, along with 5 V DC and

a reference voltage (power ground). The output is a 5 V logic signal referenced to power

ground, which is then sent to the gate driver circuit.

The addition of the gate driver circuit and isolation circuit also added a requirement

for lower voltage supplies. Three converters were implemented to meet the voltage

requirements: a 100 V DC to 15 V DC converter, a 15 V DC to 5 V DC converter, and a 120 V

AC to ±15 V DC converter. The gate driver circuit requires 15 V DC and 5 V DC, the isolation

circuit requires 5 V DC, and the current sensor circuit requires ±15 V DC, referenced to

absolute ground.


21

2.3: Part Selection

The requirements of 100 V DC, 3.33 A, and 100 kHz resonant frequency were the

main constraints which the parts of the PET cell were picked around.

MOSFETs:

The MOSFETs selected needed to be able to handle 100 V DC, 3.33 A, and switch at

minimum 100kHz without significant losses. We selected the Infineon IPW60R07C6, which

exceeds requirements in all three metrics. It is rated for 650 V DC, 34 A continuous

operation, and can switch at a rate of 50 V/ns, or a 2ns switching time in our application.

With each switching period being 10 us, this gives us negligible switching time. [18]

Resonant Tank:

The resonant capacitor value of 15 nF [19] was selected based on typical

configuration schematics provided by VITEC, the manufacturer for the transformer

windings. VITEC also provided the inductor which has a value of 52 uH. Combined with the

transformer magnetic inductance value of 275 uH, the resonant tank has a total inductance

of 327 uH.

Diodes:

To construct the full bridge rectifier, four diodes were used. The diodes selected

were required to handle 100 V and 3.33 A at 100 kHz operation. The diode we selected was

the PI LXA20T600, which exceeds each metric. It can handle a peak repetitive reverse

voltage of 600 V, and average currents of 20 A. The reverse recovery time is 26.5 ns at 25⁰C,

much shorter than our 5 us half period. The LXA20T600 was also used in our gate driver

circuit. [20]


22

Gate Driver Chip:

The requirements for our gate driver circuit were the ability to pulse 15 V with a

changing reference at 100 kHz. As mentioned above, the IR2110 with a boost-trap-

capacitor configuration can achieve this. The chip can handle up to 500 V, much greater

than our 100 V requirement. A worst-case rise time of 35 ns is acceptable [21].

Opto-coupler:

The isolation device selected needed to be able to receive logic signals referenced to

zero ground (DSP ground) and output logic signals referenced to power ground with

minimal delay. The FODM8071 met our requirements with a minimal but not negligible

worst-case propagation time of 55 ns [22].

2.4: Power Requirements

The PET has three different power requirements; a 100 V DC source input, 5 V DC

for the opto-couplers and gate driver chip, and 15 V DC for the gate driver. The 5 V DC and

15 V DC are stepped down from the 100 V DC source using DC to DC converters.

First 100 V DC is converted down to 15 V DC, referenced to power ground. This was

achieved by using the XP Power RDD08110S15 DCDC converter. This device was chosen

due to its relatively low price compared to other 100 V DC step down converters ($63) and

acceptable efficiency (83%). Although this efficiency is not ideal, the power requirements of

the gate driver circuit are comparatively low [23].

To meet the 5 V DC requirement, the converted 15 V DC was again converted, this

time down to 5 V DC. The XP Power 1205SA was used to accomplish this. Converting from

15 V DC instead of 100 V DC was desirable due to the excessive cost and poor efficiency of

100 V DC to 5 V DC converters. The XP Power 1205SA has a rated efficiency of 72%, which


23

is acceptable for this application. Like the 100 V DC to 15 V DC converter, the power used is

negligible [24].

Compared to the power circuit, the power consumption of the gate driver circuit is

negligible (less than 1%). The measured power consumption by the gate driver and opto-

couplers combined was 45 mW.

To power the overcurrent protection circuit, ±15 V DC was required. The

overcurrent protection circuit is covered in depth in section 3. Due to it being connected

directly to the DSP, it must be isolated from the power circuit. The sensor selected [28] is an

isolated hall effect sensor which prevents high power from flowing to the DSP. The sensor is

grounded to neutral (DSP ground), not power ground. The sensor is powered by the Recon

Powerline 120 V AC ±15 V DC converter. This converter was chosen because of the

availability of 120 V AC, the acceptable efficiency of 76%, and ease of use compared to

other converters [25].

2.5: Testing

Breadboard testing was conducted to ensure each stage of the design was

functioning properly. After the DSP was tested to be supplying switching signals as

intended, the gate driver circuit could be tested and verified. The first testing conducted

was to verify the functionality of the opto-couplers. The opto-couplers receive two inverted

3.3 V PWM signals from referenced to DSP ground, with a 660 ns rest time to prevent

simultaneous conduction of the MOSFETS. The opto-couplers output 5 V PWM signals

referenced to power ground.


24

Figure 2 - 5: DSP Output/Opto-coupler Input

Figure 2 - 6: Opto-coupler Output/IR2110 Input

The next step was to verify the gate driver chip was sending the correct signals to

the MOSFETs. The gate driver receives the two 5 V inverted PWM signals from the opto-


25

couplers and sends the appropriate pulsed threshold voltage to each MOSFET gate. The top

MOSFET receives pulsed ~110 V and the bottom MOSFET receives pulsed ~15 V. This

creates a 100 V square wave as shown below.

Figure 2 - 7: Top(yellow) and bottom(blue) MOSFET gate signals

After verifying the gate signals were correct, the output voltage was measured.


26

Figure 2 - 8: MOSFET load voltage, 100 V square wave

After confirming a square wave of amplitude 100 V, we could begin testing the

resonant tank circuit and transformer windings.

Figure 2 - 9: Measured voltage of transformer primary and secondary winding

Our created resonant waveform was not ideal and therefore contributed to the low

efficiency of the PET cell. The poor performance of the resonant tank circuit contributed to

the variation in the output waveform. This variation was the primary limiting factor for

being unable to reach the efficiency performance metric set at the start of the project.

Possible modifications to the resonant tank include changing components used and setup

of the resonant tank circuit. After confirming an alternating waveform, the functionality of

our rectifier was tested. Testing was done using four 171Ω resistor banks in parallel, for a

load of 42.75Ω.


27

Figure 2 - 10: Rectified waveform

As seen in the above figure, the rectifier is able to properly rectify the input signal.

2.6: Results

We calculated our PET cell’s efficiency during testing:

𝜂 = 𝑃𝑜𝑢𝑡

𝑃𝑖𝑛=

𝑉𝑜𝑢𝑡2

𝑅𝑙𝑜𝑎𝑑⁄

56.2=

44.12𝑉42.75Ω⁄

56.2= 81% (2.1)

Due to the resonant tank’s poor performance, we did not meet our original

performance metric of 90%. In addition to the resonant tank, the lack of PCB testing likely

decreased efficiency. We also decided to reduce the PET cells’ output current to 1 A due to

heat dissipation issues in several components.


28

Section 3: DSP Programming

3.1: DSP Requirements and Selection

The DSP fulfills 2 purposes in the design. The first purpose is supplying switching

signals to the MOSFETS, the second purpose is to monitor current in the power circuit. Each

module contains 2 MOSFETS, each requiring a switching signal and the project consists of 3

modules. This requires the DSP to output 6 switching signals, 2 to each module. Should this

system be expanded to include additional modules, each new module would also require 2

switching signals. The DSP requires an analog to digital convertor port to monitor the each

transformer, requiring 3 ports total to monitor all modules. When the monitored current

exceeds a dangerous operation level (4.7 A) the DSP stops switching the MOSFETs, thus

stopping the power flow to the transformer.

Based on the requirements, Dr. Ho recommended the TI Launchpad F28377S board.

The F28377S board has 4, 20 pin connector banks, a 200 MHz clock, a 12 Bit Digital to

Analog convertor, PWM output, and 1 MB flash memory. These features are sufficient for

the power control system for the design [27].

The current sensor must be able to accurately measure the high frequency AC

current passing through the transformer, and output a readable signal to the DSP.

Additionally, the current sensor must also isolate the DSP from the power circuit. Initially

we chose the LAH-25 NP Hall Effect current sensor. The LAH-25 NP current sensor fit all the

requirements necessary for the design. After further investigation, we switched to the

L18P005D15 current sensor instead. When comparing the 2 sensors the L18 current

sensor performed similarly to the LAH-25 current sensor; our decision to change the

sensor was based on cost. Per unit cost of the L18 was $13.40/sensor whereas the LAH unit

cost was $32.50/sensor. Due to the need to purchase multiple sensors, the L18 was chosen


29

due to similar performance to the LAH while costing sufficiently less (Digikey prices as of

Feb 21 2018).

The combination of the TI Launchpad board and L18 current sensor allow for

proper monitoring of the circuit at the 100 kHz design frequency.

3.2: DSP Design Considerations

There were several considerations made regarding commutation failure of the

MOSFET switching circuit. The switching signals output from the DSP are square waves

with a frequency of 100 kHz. Each module requires 2 switching signals, requiring the 2

signals to have a phase difference between them. Due to the nature of the circuit, the phase

difference is ~180 degrees. Similarly, the duty cycle of the square wave should be ~50% to

allow for alternating between which MOSFET is active. The final duty cycle ended up being

less than 50% due to several practical limitations. Firstly, the gate driver signal has rise and

fall times, meaning a 50% duty cycle would result in times when both MOSFETS were

active, which is undesired. Secondly, the software used for programming the DSP, Code

Composer Studio had limitations in the PWM code. CCS is a free C++ compiler included with

the DSP. Due to these limitations, the duty cycle was chosen to be 43.75%. This allows for a

resting time between signals of 4.375 μs, with commutation time for the MOSFETs of 83 ns

[18]. By incorporating a phase shift between signals and a modification to the duty cycle,

the chance of MOSFET commutation failure is significantly reduced.

By isolating the DSP from the power circuit through the use of opto-couplers, the

DSP can be powered externally by either a USB port or a 120 V AC supply. The F28377S

board has a micro USB port that can be used to provide power. Another method of

powering the DSP was through the use of a 3.3 V DC source. This possibility was explored

using the input voltage source and some additional components to reduce the 100 V DC

input to 3.3 V. This approach was not implemented for 2 reasons: 1. The need to power the

DSP from input voltage was not deemed a high priority 2. The additional components were


30

incredibly costly. The choice to power the DSP externally was based on reduced cost and

the ability to ensure isolation using our opto-couplers.

Use of the opto-couplers in the circuit required additional changes to be made to the

duty cycle of the switching signals. The opto-couplers used are active low, meaning when

supplied with a high signal, the opto-couplers output a low signal. A similar situation

applies when the opto-couplers are supplied with a low signal. For an opto-coupler to

output a 43.75% duty cycle, the DSP must supply a 56.25% duty cycle signal. This was

implemented in the DSP PWM code, due to the relative ease of modification compared to

additional circuitry to handle the change.

TI (Texas Instruments) Code Composer studio was used for programming the

Launchpad F28377S board, and compiled using a C++ compiler. The base code used in this

project was modified based on the examples provided by TI in the Power Suite program.

When the 6 PWM signals are being output from the DSP, the blue LED on the F28377S is lit.

When the blue LED is not lit, the PWM signals are not being transmitted, and the DSP needs

to be reset before further use. A flowchart for the main code is provided below.


31

Figure 3 - 1: Main Code Flowchart

The functions and methods used to program the DSP were modified from the code

supplied by TI to fit the design parameters of the project. Examples of code used in this

project are based on the PWM_Trip_zone, ADC_soc, and LED_blink examples. Pin

assignment for the DSP was based off recommended pins included in the F28377S

datasheet. Due to the sample code from TI using specific pins, the decision was made to

connect the recommended pins to the rest of the system. This decision was made so that

the supplied code was changed as little as possible.


32

Figure 3 - 2: DSP Pin Diagram

The PWM signals output from the DSP are generated using interrupts. As the

interrupts are being processed, all connected current sensors are polled. The resolution of

the analog to digital convertor included in the DSP is 12 bits. Time required for polling a

current sensor is 75 ns, with polling of all 3 current sensors taking 225 ns. This results in a

worst-case scenario shut-off time of 225 ns. An alternative solution was to use a 16-bit

resolution analog to digital convertor, however the time required for each ADC cycle

increased to 320 ns, resulting in a worst-case conversion time of 960 ns. This time was

deemed acceptable when compared to the alternative circuitry which could be used as a

fuse in the event over currents occurred.

When using the ADC, time between samples had to be taken into account. In order to

accurately sample the signal, the sampling frequency had to be twice the frequency of the

highest frequency component (Nyquist Sampling Theorem). The frequency of the AC

TOP

J1 J3 J4 J2

1 3.3V 5v 21 40 0V Gnd 20

2 0V Gnd 22 39 19

3 23 38 EPWM 2A 18

4 ADCIN 4 24 37 17

5 25 36 EPWM 3A 16

6 26 35 15

7 ADCIN 1 27 34 EPWM 3B 14

8 ADCIN 2 28 33 13

9 ADCIN 3 29 32 12

10 30 31 11

J5 J7 J8 J6

41 3.3V 5v 61 80 Epwm 1A 0V Gnd 60

42 0V Gnd 63 79 59

43 63 78 Epwm 1B 58

44 64 77 57

45 65 76 Epwm 2B 56

46 66 75 55

47 67 74 54

48 68 73 53

49 69 72 52

50 70 71 51


33

voltage was 100 kHz, meaning that the sampling had to occur at a frequency greater than

200 kHz. From our worst-case scenario of 225 ns, the sampling frequency was found to be

4.44 MHz, much more than necessary to satisfy the Nyquist theorem.

Figure 3 - 3: Current sensor test

From Figure 3-3, we can see the DSP ADC inputted with a step function to represent

an over current. The PWM continues for one cycle before shutting off. This gives a

measured shutoff time of 11.6 micro seconds which is deemed acceptable for the project

application.

The PWM interrupt is based off the internal clock on the F28377S board. By

modifying the code, the interval between consecutive clock triggers can be changed. To

generate the 100 kHz signal, the internal 200 MHz clock on the F28377S must be divided by

pre-scalars.

𝐹𝑜𝑠𝑐 = 200𝑀𝐻𝑧

16∗4∗2∗𝑁𝑢𝑚 (3.1)

To achieve an oscillation frequency close to 100 kHz, the Num is chosen to be 16.

This choice of Num results in an oscillation frequency of 97.656 kHz. The PWM interrupt


34

counts up and outputs a high signal if the counter is above a certain threshold. If the

counter is below that same threshold, a low signal will be output. The flowchart for the

interrupts can be seen below.

As discussed prior, each pair of PWM signals on each board has a 180 degree phase

difference to generate a sine wave as input to the transformer. Once the output of the

transformer is rectified, some slight ripple is produced. If all 3 pairs of switching signals

were in phase with each other, the resultant ripple at the output would be tripled. To

minimize the ripple at the output, each pair of switching signals is offset from the other

switching signals by 120 degrees. This changes reduce the output ripple of the system by a

factor 1.71.

The code used to program the DSP is included in the appendix of this report.

3.3: Current Sensor Design

The current sensor consists of 2 sides that are electrically isolated from each other.

The primary side of the sensor is placed on the primary side of the transformer. The

secondary side of the current sensor is powered by an external ± 15 V source and is

connected to the same ground as both the DSP and ADC.


35

Figure 3 - 4: Current sensor electrical diagram [28]

The initial placement of the current sensor was on the secondary side of the

transformer. The theory was that since the transformer turns ratio was 1:1, the

secondary current would be the same as the primary current. The change in location

was made upon realizing that the transformer had some loss, reducing the current

on the secondary side compared to the primary side. Moving the current sensor to

the primary side ensured 2 things: full galvanic isolation between primary and

secondary sides of the circuit and true measurement of current entering the

transformer.

The output from the current sensor ranges from 0 to 4 V, which is based off

the measured current from 0 to 5 Amps. The ADC scales this voltage to a value

between 0 and 4095, with 0 representing 0 Amps and 4095 representing 5 Amps.

The DSP reads this converted number and shuts down the circuit if the number

exceeds 3860 which represents a 4.7 A peak current. Should the current reach this

level, the DSP disconnects the input power from the transformer since we deemed

this current unsafe for operation. The current sensor requires 15 mA to operate.

Total power consumed by the current sensor when powered by ± 15 V is

0.225 Watts per module. This power loss will be considered in the final efficiency

calculation due to the sensor being powered manually.


36

3.4: Final Remarks

The choice of DSP and current sensor are sufficient for the tasks they are

required to perform.

Section 4: PCB Design

4.1: Board Layout

The PCB in our project was required to have dimensions less than or equal to

an 8.5 x 11 inch sheet of paper. The final dimensions of our PCB were 241 x 174 mm

(9.49 x 6.85 inches), well within our stated design parameters. The final PCB is

shown below.

Figure 4 - 1: Final PCB layout


37

The colour coding in the above diagram is explained below. Red lines are

copper traces on the top layer of the PCB. Green lines are copper traces on the

bottom layer of the PCB. Note: due to image size, some of the smaller traces may not

be visible. Red patches are surface mount areas for surface mounted components.

Yellow rings describe the size and position of through holes for mounting through

hole components. Thin blue lines approximate the physical size of a component on

the PCB. Finally, the yellow holes in each corner of the PCB are mounting holes for

attaching casings or supports to.

Component placement and trace widths will be discussed in detail later in

this section. In brief, components were placed to minimize total copper trace length

on the PCB while remaining as close as possible to their neighboring components.

During the project, our group discussed whether we would place all three

identical modules on a single PCB or on multiple PCBs, and then connect the PCBs

together to achieve the desired result. Our final decision was to use multiple PCBs

and connect them together. Upon choosing multiple PCBs, a method of connecting all

modules together to achieve our design specifications was required. To connect all

modules together, the decision was made to use screw terminals. This will be

discussed in further detail later in this report.

The main advantage of this decision was the ability to print multiple identical

PCBs. This allowed us to print smaller PCBs thereby distributing the weight from

heavier components such as the transformer across multiple PCBs. In addition to

weight concerns, the minimum number of PCBs we could order for printing was five.

If we had decided to use one PCB for all three modules, the extra four PCBs would

not have been used and the cost of printing them would be wasted. One of the

driving factors for this choice was the time constraint, as the project was nearing

completion. Due to the changes made throughout the project, our PCB was finalized

later in the project than initially planned in our project timeline.


38

The disadvantage of printing multiple identical PCBs and connecting them

together was isolating the different power grounds on each PCB from each other.

This was due to the different ground levels required in each PCB. Each PCB requires

a high voltage power ground, and an absolute ground power ground. The high

power ground is required for components not referenced to absolute ground, to

ensure that the input terminals on each PCB for stepping down our voltage could be

connected together in series.

At the time of writing, the PCBs have arrived, however due to their late arrival

they could not be tested in time for this report.

The physical layout of components on each board was designed around the

gate driver chip. The reason for this was that the gate driver had the most

components connected to it of all components in the circuit. Minimizing the distance

from the gate driver to the components connected to it helps minimize total trace

distance. The larger components on the board (the DSP, transformer and inductor)

also required special considerations for where they were placed. The result of this

approach was a reduction in total copper trace length on the PCB. This ensured

more intact copper layers on both sides of the PCB.

When placing the DSP, which pins were being used in our design had to be

taken into account. Similar to the rest of the circuit, the DSP was oriented in such as

way as to minimize the total trace lengths on the board. All modules of the project

were driven by a single DSP. In order to connect the DSP to all modules, all PCBs

must be identical and allow for selection of which pins were needed on each module.

Our solution to this problem was to connect like pins together (such as the pins

driving the opto-couplers), then placing a resistor between the copper trace and

DSP. This allowed for selection of which pin was in use by soldering a low impedance

resistor to the proper trace, and open-circuit the other paths to prevent mixed


39

signals. An added benefit of this approach was reducing the number of traces on the

board, making it easier to read.

The transformer and its accompanying inductor could unfortunately not be

placed close together. The reason for this was that the inductor had connections to

other components on the board, and placing the inductor close to the transformer

would cause these other traces to become much longer than their final version.

Therefore the decision was made to place the inductor farther away from the

transformer in order to minimize trace lengths for components connected to the

inductor.

4.2: Input and Output of PCB Modules

As part of the project, our group had to determine how to connect a voltage

source to the circuit and obtain the output signal. To do this, we had to determine

what input signals were required and how to supply them. We concluded that 2

input voltage levels were required to power all components in our circuit. These

voltage levels were selected based on output voltage to input voltage ratio of each

module (1:1), and the external source required to power additional circuitry. The 2

voltage levels we decided on using were 100 V DC and 120 V DC. The 100 V input

was used to supply the input voltage to be transformed, and the 100 V to 15 V boost

convertor. Similarly, the 120 V input was used to power our 120 V to +- 15 V boost

convertor. This second boost convertor is used specifically to power the overcurrent

sensor while isolating it electrically from the rest of the circuit. The boost convertors

isolate their input voltage from output voltage, allowing us to decouple a voltage

source from its input ground level.

In order to connect the DSP to the rest of the circuit, we needed to add

connectors for the DSP. The DSP has a total of 80 pins spread between 4 banks of 20

pins each. There are other pins on the DSP that are not in the banks of 20 pins, but


40

due to their positioning they did not need to be incorporated into the PCB footprint.

A total of 10 pins were used in our design, specified in the above DSP section. Each

of the connector banks on the DSP was connected to the PCB by a corresponding

open-top, 20 pin male-to-male connector. This allows the DSP to sit on top of one

PCB, so that all components on our PCB would be visible at one time. The DSP is

connected to other modules through additional wires and cabling. The DSP footprint

in particular had to be created based on physical measurements taken by the group,

since the manufacturer datasheet did not include a spacing diagram showing the

spacing of pin banks on the DSP. This was the only component where the footprint

was not based on readily available supplier data.

To connect external sources to the circuit on our PCB, we needed to decide

which type of terminals to use. There were 2 different types of connectors we

considered using: coax connectors and screw terminal connectors. The screw

connector was chosen for this project.

A major benefit of the coax connector was that it allowed for easier

connection to external sources, since the voltage sources we were using had coax

connectors on them. In the case of a single PCB containing all 3 modules of our

transformer unit, the coax connector would have been the ideal choice. This is

because the coax connectors would not require any intermediary connectors, and

would reduce the complexity of input and output connections. However, since we

decided on separate PCBs for each module we decided against using the coax

connector. Connecting multiple modules together would be more difficult using coax

connectors compared to screw terminals within the context of this project. To

connect multiple modules together using coax connectors, multiple coax connectors

would be required for input and output from each module.

Using screw terminals allowed for easier connection of multiple modules

together, since screw terminals can be connected together by use of wires. Therefore

we could easily connect the inputs of our modules in series by running a wire from


41

the bottom of one screw terminal on one module to the top of the screw terminal of

the next module. Use of these terminals allowed for similar connection of our PCB

outputs in parallel. A module connection diagram is included below.

Figure 4 - 2: Module connection diagram

As shown in figure EF2, the input terminals on each module are connected

together in series, so that each module takes in 1/3 of the total input voltage (300 V

in this project). The outputs are connected in parallel to provide 100 V output.

However, the change in ease of connecting modules together meant that extra

circuitry was required to change the input signal (carried by coax cable) into a form

that could be run through wires.

Both of the types of connectors we considered had advantages, but we

ultimately decided on using the screw terminals. We made this choice based on

perceived ease of connecting modules together within the limited time remaining on

the project.


42

4.3: PCB Trace Calculations

An important design choice during this project was determining the proper

trace width for all current paths in our circuit. The maximum current allowable in

our circuit is 4.7 A, and the high current trace widths were calculated based on this.

We decided that wide traces were not required throughout the whole circuit, since

only certain paths would use high current (such as the current sensor). Note that 1

mil = 0.00254 mm.

The trace widths chosen were 3.5 mm for high current paths and 0.5 mm for

lower current paths. These widths were based on the following equations [29]:

𝐴𝑟𝑒𝑎(𝑚𝑖𝑙𝑠2) = (𝐶𝑢𝑟𝑟𝑒𝑛𝑡(𝑎𝑚𝑝𝑠)

𝑘∗(𝑇𝑒𝑚𝑝𝑟𝑖𝑠𝑒[𝑑𝑒𝑔𝑟𝑒𝑒𝑠 𝐶𝑒𝑙𝑠𝑖𝑢𝑠])𝑏)

1

𝑐 (4.1)

Where k = 0.048, b = 0.44, and c = 0.725 for IPC-2221 PCB board material.

Using this area, width was found based on the equation:

𝑊𝑖𝑑𝑡ℎ[𝑚𝑖𝑙𝑠] =𝐴𝑟𝑒𝑎[𝑚𝑖𝑙𝑠2]

𝑇ℎ𝑐𝑘𝑛𝑒𝑠𝑠[𝑜𝑢𝑛𝑐𝑒𝑠]∗1.378[𝑚𝑖𝑙𝑠

𝑜𝑧] (4.2)

These calculations were made under the assumption that the thickness of the

copper used in our PCB was going to be 1 oz/square foot, a 60 °C ambient trace

temperature and a maximum increase in trace temperature of 10 °C. Based on these

constraints, our minimum trace thickness in air was calculated to be 2.03 mm

(80.0 mils) for our high current traces. Upon recommendation from Daniel Card, our

traces were made approximately equal to 1 mm per Amp. This was to protect from

possible over-currents in the circuit, and to reduce temperature increase under

normal operation modes. Wider traces also have lower resistance and contributed

inductance than thinner traces, so wider traces help reduce copper loss due to

traces.


43

The layout of the circuit was designed to limit the total trace length on the

PCB. However, not all components could be placed close to their neighbors, so traces

were placed to try and minimize the amount of power ground they cut up.

Figure 4 - 3: Top Copper Layer


44

Figure 4 - 4: Bottom Copper Layer

Figures 4-3 and 4-4 show the copper coverage on the top and bottom layers

of the PCB. White areas are locations where no copper is placed, and black areas are

where copper is placed. When comparing the two layers, the bottom copper layer

has fewer traces placed on it, allowing it to stay more intact than the top copper

layer.

This choice was made based on the recommendation of Daniel Card to keep

one ground plane as intact as possible. In order to achieve this, the majority of traces

were placed on the top layer of the PCB. In cases where traces would cross each

other, one of the traces was placed through a via to run on the bottom layer of the

board. The choice of which trace would be run on the bottom layer of the board was

based on which trace would take less space on the bottom layer.


45

4.4: PCB Design Software Used

The software used in the design of our PCB was Kicad, a free, open source

development package including a circuit simulator, PCB layout environment, and a

Gerber file generating component. The reason for using Kicad as opposed to another

premium PCB design software such as Altium was the inability to make Altium work

properly on a virtual machine. An attempt was made to install and run Altium on a

Mac running a virtual machine, but various issues with this approach caused it to be

unsuccessful. Kicad was chosen due to ease of use and setup, and potential to run on

any operating system in case the PCB files needed to be passed between group

members.

As part of the design process, the footprints of almost all components needed

to be modified to match their manufacturer specifications. In order to make these

changes, a footprint was chosen that most closely matched the required component

and the spacing and size of through holes or surface mounts were modified to most

closely match manufacturer recommended layout. This was a disadvantage of using

Kicad, the component library was not as comprehensive as other premium PCB

design packages so component footprints were left up to the discretion of the PCB

designer.

4.5: Final Remarks

With the aforementioned details about the design process of the PCB, the

resultant PCB is not the ideal PCB for this circuit. There are several reasons for this,

including extensive use of modified component footprints, and non-ideal location of

components in the circuit. Future work to optimize the PCB could include the use of

design algorithms to place components and lay traces. By doing this, the PCB could

be made smaller, and closely connected components could be located closer

together, helping to improve the coherence of the PCB.


46

Conclusion:

In conclusion, we were unable to meet the original specified performance

metrics. Due to the current limiting characteristics of some components, we were

unable to meet the original current specification. Based on our preliminary testing,

we observed that the circuit did not perform as intended when supplied with

greater than 1 A. A possible improvement to the project includes placing all

components on the PCB as initially planned. Due to the time of PCB arrival in

relation to the time of report submission, testing the circuit on a PCB was not

feasible. Additionally, overall module efficiency could be improved through changes

to the resonant tank components and topology. The approach used during this

project indicates that this design is capable of power transformation with galvanic

isolation.


47

References:

[1] Jason A. Zengel. (2003, June). DC-DC Power Conversion with Galvanic Isolation, Naval

Postgraduate School, Monterey, California [Online]. Available:

http://www.dtic.mil/dtic/tr/fulltext/u2/a417701.pdf [Feb. 12, 2018].

[2] N. Mohan, T. M. Undeland and W. P. Robbins. (2003) “Design of Magnetic Components” in

Power Electronics Converters, Applications, and Design, 3rd ed. B. Zobrist, C. Cervoni, Eds.

U.S: John Wiley & Sons. Inc. 2003. pp.744 - 793.

[3] VITEC Electronics Corporation. “Half-Bridge Transformer 75P8113”. Carlsbad: VITEC

Electronics Corporation, 2018.

[4] “Magnetic Component - Design and Optimization” Class note for ECE7440, Department

of Electrical and Computer Engineering, University of Manitoba, 2015.

[5] “Magnetic core” in Wikipedia, Magnetic core [Online]. Available:

https://en.wikipedia.org/wiki/Magnetic_core [Feb. 12, 2018].

[6] EPCOS AG. (2017). " Ferrites and accessories ETD54-28-19 Core and accessories" [Online].

Available: https://en.tdk.eu/inf/80/db/fer/etd_54_28_19.pdf [October 20, 2017]

http://www.dtic.mil/dtic/tr/fulltext/u2/a417701.pdf

https://en.wikipedia.org/wiki/Magnetic_core

https://en.tdk.eu/inf/80/db/fer/etd_54_28_19.pdf


48

[7] “American wire gauge” in Wikipedia, American wire gauge [Online]. Available:

https://en.wikipedia.org/wiki/American_wire_gauge [Feb. 12, 2018].

[8] “Saturation (magnetic)” in Wikipedia, Saturation (magnetic) [Online]. Available:

https://en.wikipedia.org/wiki/Saturation_(magnetic) [Feb. 12, 2018].

[9] J.O. Aibangbee and S.O. Onihaebi. (2017, August. 24). Improving Current Transformers

Transient Response and Saturation Effects Using Air-Gapped Core, Bells University of

Technology, Ota, Nigeria [Online]. Available:

http://www.ajer.org/papers/v6(08)/U0608163169.pdf [Feb. 12, 2018].

[10] R. Clarke. (2011, May. 26). Air Gap Magnetic core [Online]. Available:

http://info.ee.surrey.ac.uk/Workshop/advice/coils/gap/index.html [Feb. 12, 2018].

[11] A. Bagglni. (2016, August). Power Transformers - Introduction to measurement of losses.

INTAS, European [Online]. Available: http://www.intas-

testing.eu/storage/app/media/INTAS_trasformers_descr.pdf [Feb. 12, 2018].

[12] K. Daware. Transformer - Losses and Efficiency [Online]. Available:

http://www.electricaleasy.com/2014/04/transformer-losses-and-efficiency.html [Feb. 12,

2018].

https://en.wikipedia.org/wiki/American_wire_gauge

https://en.wikipedia.org/wiki/Saturation_(magnetic)

http://www.ajer.org/papers/v6(08)/U0608163169.pdf

http://info.ee.surrey.ac.uk/Workshop/advice/coils/gap/index.html

http://www.intas-testing.eu/storage/app/media/INTAS_trasformers_descr.pdf

http://www.intas-testing.eu/storage/app/media/INTAS_trasformers_descr.pdf

http://www.electricaleasy.com/2014/04/transformer-losses-and-efficiency.html


49

[13] Types of Losses in Transformer. Circuit globe [Online]. Available:

https://circuitglobe.com/types-of-losses-in-transformer.html [Feb. 12, 2018].

[14] H. Lloyd. (2003) Eddy Current Losses in Transformer Windings and Circuit Wiring. Texas

Instruments Incorporated, Texas, Dallas [Online]. Available:

http://www.ti.com/lit/ml/slup197/slup197.pdf [Feb. 20, 2018].

[15] EPCOS AG. (2013). " EPCOS DATA BOOK 2013 - Ferrites and accessories" [Online].

Available: https://en.tdk.eu/download/519704/069c210d0363d7b4682d9ff22c2ba503/fe

rrites-and-accessories-db-130501.pdf [October 20, 2017]

[16] “Copper loss” in Wikipedia, Copper loss [Online]. Available:

https://en.wikipedia.org/wiki/Copper_loss [Feb. 12, 2018].

[17] VITEC Electronics Corporation. “Inductor 51P5368”. Carlsbad: VITEC Electronics

Corporation, 2018.

[18] Infineon. (2010, Feb. 9). “600V CoolMOS C6 Power Transistor IPW60R070C6” [Online].

Available: https://www.infineon.com/dgdl/Infineon-IPW60R070C6-DS-v02_01-

en.pdf?fileId=db3a30432313ff5e01232862aa644ac5 [Nov. 25, 2017].

[19] Nichicon. (No date available). “QXP Metallized Polypropylene Film Capacitor” [Online].

Available: http://nichicon-us.com/english/products/pdfs/e-qxp.pdf [Jan. 12 2018].

https://circuitglobe.com/types-of-losses-in-transformer.html

http://www.ti.com/lit/ml/slup197/slup197.pdf

https://en.tdk.eu/download/519704/069c210d0363d7b4682d9ff22c2ba503/ferrites-and-accessories-db-130501.pdf

https://en.tdk.eu/download/519704/069c210d0363d7b4682d9ff22c2ba503/ferrites-and-accessories-db-130501.pdf

https://en.wikipedia.org/wiki/Copper_loss

https://www.infineon.com/dgdl/Infineon-IPW60R070C6-DS-v02_01-en.pdf?fileId=db3a30432313ff5e01232862aa644ac5

https://www.infineon.com/dgdl/Infineon-IPW60R070C6-DS-v02_01-en.pdf?fileId=db3a30432313ff5e01232862aa644ac5

http://nichicon-us.com/english/products/pdfs/e-qxp.pdf


50

[20] Power Integrations. (2010, Jan.). “LXA20T600” [Online]. Available:

https://www.power.com/sites/default/files/product-docs/qspeed/lxa20t600.pdf [Nov. 25,

2017].

[21] International Rectifier. (2005, Mar. 23). “IR2110” [Online]. Available:

https://www.infineon.com/dgdl/ir2110.pdf?fileId=5546d462533600a4015355c8033316

7e [Dec. 4, 2017].

[22] Fairchild. (2014, Dec.). “FODM8071” [Online]. Available:

https://www.fairchildsemi.com/datasheets/FO/FODM8071.pdf [Dec. 28, 2017]

[23] XP Power. (2017, Oct.). “RDD Series” [Online]. Available:

http://www.xppower.com/Portals/0/pdfs/SF_RDD08.pdf [Jan. 24, 2018]

[24] XP Power. (2011, Jan.). “IW Series” [Online]. Available:

http://www.digikey.ca/scripts/DkSearch/dksus.dll?Detail&itemSeq=253835013&uq=636

558539316763235 [Jan. 24, 2018]

[25] Recom. (2015). “Powerline AC/DC Converter” [Online]. Available:

https://www.recom-power.com/pdf/Powerline-AC-DC/RAC05-S_DC.pdf [Jan. 24, 2018]

[26] ST Microelectronics. (2008, Sept.). An introduction to LLC resonant half-bridge

converter. ST Microelectronics. [Online]. Available:

http://www.st.com/content/ccc/resource/technical/document/application_note/de/f9/1

https://www.power.com/sites/default/files/product-docs/qspeed/lxa20t600.pdf

https://www.infineon.com/dgdl/ir2110.pdf?fileId=5546d462533600a4015355c80333167e

https://www.infineon.com/dgdl/ir2110.pdf?fileId=5546d462533600a4015355c80333167e

https://www.fairchildsemi.com/datasheets/FO/FODM8071.pdf

http://www.xppower.com/Portals/0/pdfs/SF_RDD08.pdf



https://www.recom-power.com/pdf/Powerline-AC-DC/RAC05-S_DC.pdf

http://www.st.com/content/ccc/resource/technical/document/application_note/de/f9/17/b7/ad/9f/4d/dd/CD00174208.pdf/files/CD00174208.pdf/jcr:content/translations/en.CD00174208.pdf


51

7/b7/ad/9f/4d/dd/CD00174208.pdf/files/CD00174208.pdf/jcr:content/translations/en.

CD00174208.pdf

[27] Texas Instruments (2014, Aug.) “TMS320F2837xS Delfino Microcontrollers”. [Online].

Available: http://www.ti.com/lit/ds/sprs881d/sprs881d.pdf [Jan. 24, 2018]

[28] TAMURA. (2012, Mar.). “Hall Effect Current Sensors” [Online].

Available: https://www.mouser.com/ds/2/397/L18PXXXD15-33262.pdf [Jan. 24, 2018]

[29]: “Advanced Circuits,” PCB Printed Circuit Board File Creation Calculator | Advanced

Circuits. [Online]. Available: http://www.4pcb.com/trace-width-calculator.html. [Feb. 17,

2018].



http://www.ti.com/lit/ds/sprs881d/sprs881d.pdf


52

Appendix A: Final Project Cost Breakdown

The final cost breakdown of the project is specified in table B-1 included on the

following page. A total of $945.67 was spent for the project, which is within the original

proposed budget. Of the $945.76, $400 was supplied by the Department of Electrical and

Computer Engineering and $545.67 was sponsored by Dr. Carl Ho. The changes to the

budget were associated with changes to design topology and the testing procedures used.

The microcontroller and material for transformer windings were borrowed from

Dr. Carl Ho. The transformer and inductors were sponsored by the VITEC Electronics

Corporation. All sponsored components will be returned to Dr. Carl Ho after the final

demonstration on March 23, 2018.


53

Table A - 1: G08 final project cost breakdown


54

Appendix B: Full Project Schematic

Figure B - 1: Full Project Schematic


55

Appendix C: Testing Proto Board Setup

Figure C - 1: Testing Proto Board Setup


56

Appendix D: DSP Code

//#############################################################################

// // FILE: device.c // // TITLE: Device setup for examples. // //############################################################################

# // $TI Release: F2837xS Support Library v3.02.00.00 $ // $Release Date: Sat Sep 16 15:30:24 CDT 2017 $ // $Copyright: // Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################

# // // Included Files // #include "device.h"


57

#include "driverlib.h" //****************************************************************************

* // // Function to initialize the device. Primarily initializes system control to

a // known state by disabling the watchdog, setting up the SYSCLKOUT frequency, // and enabling the clocks to the peripherals. // //****************************************************************************

* void Device_init(void) { // // Disable the watchdog // SysCtl_disableWatchdog(); #ifdef _FLASH // // Copy time critical code and flash setup code to RAM. This includes the // following functions: InitFlash(); // // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols // are created by the linker. Refer to the device .cmd file. // memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); // // Call Flash Initialization to setup flash waitstates. This function must // reside in RAM. // Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE,

DEVICE_FLASH_WAITSTATES); #endif #ifdef CPU1 // // Set up PLL control and clock dividers // SysCtl_setClock(DEVICE_SETCLOCK_CFG); // // Make sure the LSPCLK divider is set to the default (divide by 4) // SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); // // These asserts will check that the #defines for the clock rates in // device.h match the actual rates that have been configured. If they do // not match, check that the calculations of DEVICE_SYSCLK_FREQ and // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as // expected if these are not correct. // ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);


58

ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); #endif // // Turn on all peripherals // Device_enableAllPeripherals(); } //****************************************************************************

* // // Function to turn on all peripherals, enabling reads and writes to the // peripherals' registers. // // Note that to reduce power, unused peripherals should be disabled. // //****************************************************************************

* void Device_enableAllPeripherals(void) { SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3);


59

SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); } //****************************************************************************

* // // Function to disable pin locks on GPIOs. // //****************************************************************************

* void Device_initGPIO(void) { //


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// Disable pin locks. // GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); // // Enable GPIO Pullups // Device_enableUnbondedGPIOPullups(); } //****************************************************************************

* // // Function to enable pullups for the unbonded GPIOs on the 176PTP package: // GPIOs Grp Bits // 95-132 C 31 // D 31:0 // E 4:0 // 134-168 E 31:6 // F 8:0 // //****************************************************************************

* void Device_enableUnbondedGPIOPullupsFor176Pin(void) { EALLOW; HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; EDIS; } //****************************************************************************

* // // Function to enable pullups for the unbonded GPIOs on the 100PZ package: // GPIOs Grp Bits // 0-1 A 1:0 // 5-9 A 9:5 // 22-40 A 31:22 // B 8:0 // 44-57 B 25:12 // 67-68 C 4:3 // 74-77 C 13:10 // 79-83 C 19:15 // 93-168 C 31:29 // D 31:0 // E 31:0


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// F 8:0 // //****************************************************************************

* void Device_enableUnbondedGPIOPullupsFor100Pin(void) { EALLOW; HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; EDIS; } //****************************************************************************

* // // Function to enable pullups for the unbonded GPIOs on the 100PZ or // 176PTP package. // //****************************************************************************

* void Device_enableUnbondedGPIOPullups(void) { // // bits 8-10 have pin count // uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> SYSCTL_PARTIDL_PIN_COUNT_S); /* * 5 = 100 pin * 6 = 176 pin * 7 = 337 pin */ if(pinCount == 5) { Device_enableUnbondedGPIOPullupsFor100Pin(); } else if(pinCount == 6) { Device_enableUnbondedGPIOPullupsFor176Pin(); } else { // // Do nothing - this is 337 pin package // } }


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//*****************************************************************************

// // Error handling function to be called when an ASSERT is violated // //****************************************************************************

* void __error__(char *filename, uint32_t line) { // // An ASSERT condition was evaluated as false. You can use the filename

and // line parameters to determine what went wrong. // ESTOP0; } //############################################################################

# // // FILE: device.h // // TITLE: Device setup for examples. // //############################################################################

# // $TI Release: F2837xS Support Library v3.02.00.00 $ // $Release Date: Sat Sep 16 15:30:24 CDT 2017 $ // $Copyright: // Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY


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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################

# // // Included Files // #include "driverlib.h" //****************************************************************************

* // // Defines for pin numbers and other GPIO configuration // //****************************************************************************

* // // LEDs // //#define DEVICE_GPIO_PIN_LED0 12U #define DEVICE_GPIO_PIN_LED1 13U // GPIO number for LD2 #define DEVICE_GPIO_PIN_LED2 14U // GPIO number for LD3 #define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 #define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 // // SCI for USB-to-UART adapter on FTDI chip // #define DEVICE_GPIO_PIN_SCIRXDA 85U // GPIO number for SCI RX #define DEVICE_GPIO_PIN_SCITXDA 84U // GPIO number for SCI TX #define DEVICE_GPIO_CFG_SCIRXDA GPIO_85_SCIRXDA // "pinConfig" for SCI RX #define DEVICE_GPIO_CFG_SCITXDA GPIO_84_SCITXDA // "pinConfig" for SCI TX // // CANA // #define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA #define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA // // CAN External Loopback // #define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX #define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX #define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX #define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX //****************************************************************************

* // // Defines related to clock configuration


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// //****************************************************************************

* // // LaunchPad Configuration // #ifdef _LAUNCHXL_F28377S // // 10MHz XTAL on controlCARD. For use with SysCtl_getClock(). // #define DEVICE_OSCSRC_FREQ 10000000U // // Define to pass to SysCtl_setClock(). Will configure the clock as follows: // PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) // #define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) |

\ SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |

\ SYSCTL_PLL_ENABLE) // // 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the // code below if a different clock configuration is used! // #define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) // // ControlCARD Configuration // #else // // 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). // #define DEVICE_OSCSRC_FREQ 20000000U // // Define to pass to SysCtl_setClock(). Will configure the clock as follows: // PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) // #define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) |

\ SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |

\ SYSCTL_PLL_ENABLE) // // 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the // code below if a different clock configuration is used! // #define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2)


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#endif // // 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default // low speed peripheral clock divider of 4. Update the code below if a // different LSPCLK divider is used! // #define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) //****************************************************************************

* // // Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro // will convert the desired delay in microseconds to the count value expected // by the function. \b x is the number of microseconds to delay. // //****************************************************************************

* #define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L /

\ (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) /

5.0L) //****************************************************************************

* // // Defines, Globals, and Header Includes related to Flash Support // //****************************************************************************

* #ifdef _FLASH #include <stddef.h> extern uint16_t RamfuncsLoadStart; extern uint16_t RamfuncsLoadEnd; extern uint16_t RamfuncsLoadSize; extern uint16_t RamfuncsRunStart; extern uint16_t RamfuncsRunEnd; extern uint16_t RamfuncsRunSize; #define DEVICE_FLASH_WAITSTATES 3 #endif //****************************************************************************

* // // Function Prototypes // //****************************************************************************

* extern void Device_init(void); extern void Device_enableAllPeripherals(void); extern void Device_initGPIO(void); extern void Device_enableUnbondedGPIOPullupsFor176Pin(void);


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extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); extern void Device_enableUnbondedGPIOPullups(void); extern void __error__(char *filename, uint32_t line); // // End of file // //############################################################################

# // // FILE: driverlib.h // // TITLE: C28x Driverlib Header File // //############################################################################

# // $TI Release: F2837xS Support Library v3.02.00.00 $ // $Release Date: Sat Sep 16 15:30:24 CDT 2017 $ // $Copyright: // Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################

# #ifndef DRIVERLIB_H #define DRIVERLIB_H


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#include "inc/hw_memmap.h" #include "adc.h" #include "asysctl.h" #include "can.h" #include "cla.h" #include "cmpss.h" #include "cpu.h" #include "cputimer.h" #include "dac.h" #include "dcsm.h" #include "debug.h" #include "dma.h" #include "ecap.h" #include "emif.h" #include "epwm.h" #include "eqep.h" #include "flash.h" #include "gpio.h" #include "hrpwm.h" #include "i2c.h" #include "interrupt.h" #include "mcbsp.h" #include "memcfg.h" #include "pin_map.h" #include "sci.h" #include "sdfm.h" #include "spi.h" #include "sysctl.h" #include "upp.h" #include "version.h" #include "xbar.h" #endif // end of DRIVERLIB_H definition // // End of file // ;//########################################################################### ;// ;// FILE: F2837xS_CodeStartBranch.asm ;// ;// TITLE: Branch for redirecting code execution after boot. ;// ;// For these examples, code_start is the first code that is executed after ;// exiting the boot ROM code. ;// ;// The codestart section in the linker cmd file is used to physically place ;// this code at the correct memory location. This section should be placed ;// at the location the BOOT ROM will re-direct the code to. For example, ;// for boot to FLASH this code will be located at 0x3f7ff6. ;// ;// In addition, the example F2837xS projects are setup such that the codegen


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;// entry point is also set to the code_start label. This is done by linker ;// option -e in the project build options. When the debugger loads the code, ;// it will automatically set the PC to the "entry point" address indicated by ;// the -e linker option. In this case the debugger is simply assigning the

PC, ;// it is not the same as a full reset of the device. ;// ;// The compiler may warn that the entry point for the project is other then ;// _c_init00. _c_init00 is the C environment setup and is run before ;// main() is entered. The code_start code will re-direct the execution ;// to _c_init00 and thus there is no worry and this warning can be ignored. ;// ;//########################################################################### ;// $TI Release: F2837xS Support Library v3.02.00.00 $ ;// $Release Date: Sat Sep 16 15:30:24 CDT 2017 $ ;// $Copyright: ;// Copyright (C) 2014-2017 Texas Instruments Incorporated -

http://www.ti.com/ ;// ;// Redistribution and use in source and binary forms, with or without ;// modification, are permitted provided that the following conditions ;// are met: ;// ;// Redistributions of source code must retain the above copyright ;// notice, this list of conditions and the following disclaimer. ;// ;// Redistributions in binary form must reproduce the above copyright ;// notice, this list of conditions and the following disclaimer in the ;// documentation and/or other materials provided with the ;// distribution. ;// ;// Neither the name of Texas Instruments Incorporated nor the names of ;// its contributors may be used to endorse or promote products derived ;// from this software without specific prior written permission. ;// ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;// $ ;//########################################################################### *********************************************************************** WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 .ref _c_int00 .global code_start


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*********************************************************************** * Function: codestart section * * Description: Branch to code starting point *********************************************************************** .sect "codestart" code_start: .if WD_DISABLE == 1 LB wd_disable ;Branch to watchdog disable code .else LB _c_int00 ;Branch to start of boot._asm in RTS library .endif ;end codestart section *********************************************************************** * Function: wd_disable * * Description: Disables the watchdog timer *********************************************************************** .if WD_DISABLE == 1 .text wd_disable: SETC OBJMODE ;Set OBJMODE for 28x object code EALLOW ;Enable EALLOW protected register access MOVZ DP, #7029h>>6 ;Set data page for WDCR register MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD EDIS ;Disable EALLOW protected register access LB _c_int00 ;Branch to start of boot._asm in RTS library .endif ;end wd_disable .end ;// ;// End of file. ;// //############################################################################

# // // FILE: epwm_ex1_trip_zone.c // // TITLE: ePWM Using Trip-Zone Submodule. // //! \addtogroup driver_example_list //! <h1>ePWM Trip Zone</h1> //!


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//! This example configures ePWM1 and ePWM2 as follows //! - ePWM1 has TZ1 as one shot trip source //! - ePWM2 has TZ1 as cycle by cycle trip source //! //! Initially tie TZ1 high. During the test, monitor ePWM1 or ePWM2 //! outputs on a scope. Pull TZ1 low to see the effect. //! //! \b External \b Connections \n //! - ePWM1A is on GPIO0 //! - ePWM2A is on GPIO2 //! - TZ1 is on GPIO12 //! //! This example also makes use of the Input X-BAR. GPIO12 (the external //! trigger) is routed to the input X-BAR, from which it is routed to TZ1. //! //! The TZ-Event is defined such that ePWM1A will undergo a One-Shot Trip //! and ePWM2A will undergo a Cycle-By-Cycle Trip. //! // _____________ __________________ // | | | | // GPIO12 -----| I/P X-BAR |-----TZ1-----| ePWM TZ Module |-----TZ-Event // |___________| |________________| // // // //############################################################################

# // $TI Release: F28311xS Support Library v3.02.00.00 $ // $Release Date: Sat Sep 16 15:30:24 CDT 20111 $ // $Copyright: // Copyright (C) 2014-20111 Texas Instruments Incorporated -

http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT


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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################

# // // Included Files // #include "driverlib.h" #include "device.h" // // Defines // #define EX_ADC_RESOLUTION ADC_RESOLUTION_12BIT // Or ADC_RESOLUTION_16BIT #define EX_ADC_SIGNAL_MODE ADC_MODE_SINGLE_ENDED // Or

ADC_MODE_DIFFERENTIAL // // Globals // uint16_t dutyCycle; uint16_t adcAResult0; uint16_t adcAResult1; uint16_t adcBResult0; uint16_t adcBResult1; uint16_t triggerNumber; // uint16_t tbp2;//time base period uint16_t tbc2;//time base counter uint16_t Phase2;// phase shift uint16_t tbp6;//time base period uint16_t tbc6;//time base counter uint16_t Phase6;// phase shift uint16_t tbp8;//time base period uint16_t tbc8;//time base counter uint16_t Phase8;// phase shift uint16_t tbp9;//time base period uint16_t tbc9;//time base counter uint16_t Phase9;// phase shift uint16_t tbp10;//time base period uint16_t tbc10;//time base counter uint16_t Phase10;// phase shift uint16_t tbp11;//time base period uint16_t tbc11;//time base counter uint16_t Phase11;// phase shift uint32_t ledBlink; uint32_t epwm6TZIntCount; uint32_t epwm2TZIntCount;


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uint32_t epwm11TZIntCount; uint32_t epwm8TZIntCount; uint32_t epwm9TZIntCount; uint32_t epwm10TZIntCount; // // Function Prototypes // //void initEPWM1(void); void initADCs(void); void initADCSOCs(void); void initEPWM2(void); void initEPWM6(void); void initEPWM11(void); void initEPWM8(void); void initEPWM9(void); void initEPWM10(void); void initTZGPIO(void); void initEPWMGPIO(void); void stopFunc(void); __interrupt void epwm6TZISR(void); __interrupt void epwm2TZISR(void); __interrupt void epwm11TZISR(void); __interrupt void epwm8TZISR(void); __interrupt void epwm9TZISR(void); __interrupt void epwm10TZISR(void); void main(void) { // // Initialize global variables // tbp2 = 16U;//controls freq dutyCycle = (tbp2 / 2) - 1;//10U; tbp6 = tbp2; tbp8 = tbp2; tbp9 = tbp2; tbp10 = tbp2; tbp11 = tbp2; tbc2= 11U;//controls phase//2U tbc6= 0U;//10 tbc8= 3U; tbc9= 0U; tbc10= 10U; tbc11= 0U;


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Phase2= 0U;//contorols total phase Phase6= 0U; Phase8= 0U; Phase9= 0U; Phase10= 0U; Phase11 = 0U; ledBlink = 0U; triggerNumber = 3860;// number that triggers stop from 0 to 4095

representing 0 V to supply voltage //3860 represents 3.33 * root(2) amps epwm6TZIntCount = 0U; epwm2TZIntCount = 0U; epwm11TZIntCount = 0U; epwm8TZIntCount = 0U; epwm9TZIntCount = 0U; epwm10TZIntCount = 0U; // // Initialize device clock and peripherals // Device_init(); // // Disable pin locks and enable internal pull-ups. // Device_initGPIO(); GPIO_setPadConfig(DEVICE_GPIO_PIN_LED1, GPIO_PIN_TYPE_STD); GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED1, GPIO_DIR_MODE_OUT); // // Initialize PIE and clear PIE registers. Disables CPU interrupts. // Interrupt_initModule(); // // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // Interrupt_initVectorTable(); // // Set up ADCs, initializing the SOCs to be triggered by software // initADCs(); initADCSOCs(); // // Interrupts that are used in this example are re-mapped to ISR functions // found within this file. // Interrupt_register(INT_EPWM2_TZ, &epwm2TZISR); Interrupt_register(INT_EPWM6_TZ, &epwm6TZISR);


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Interrupt_register(INT_EPWM11_TZ, &epwm11TZISR); Interrupt_register(INT_EPWM8_TZ, &epwm8TZISR); Interrupt_register(INT_EPWM9_TZ, &epwm9TZISR); Interrupt_register(INT_EPWM10_TZ, &epwm10TZISR); // // Configure ePWM1, ePWM2, and TZ GPIOs // initEPWMGPIO(); initTZGPIO(); // // Disable sync(Freeze clock to PWM as well) // SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); // // Initialize ePWM6 and ePWM2,11,8,9,10 // initEPWM2();//1A initEPWM6();//1B initEPWM11();//3B initEPWM8();//2A initEPWM9();//2B initEPWM10();//3A // // Enable sync and clock to PWM // SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); // // Enable interrupts required for this example // Interrupt_enable(INT_EPWM2_TZ); Interrupt_enable(INT_EPWM6_TZ); Interrupt_enable(INT_EPWM11_TZ); Interrupt_enable(INT_EPWM8_TZ); Interrupt_enable(INT_EPWM9_TZ); Interrupt_enable(INT_EPWM10_TZ); // // Enable Global Interrupt (INTM) and real time interrupt (DBGM) // EINT; ERTM;


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// // IDLE loop. Just sit and loop forever (optional): // GPIO_writePin(DEVICE_GPIO_PIN_LED1, 0); //GPIO_writePin(DEVICE_GPIO_PIN_LED0, 0); for(;;) { //ledBlink = 1U; //NOP;// do nothing command //if (ledBlink != 0U){ // ledBlinkFun(); /} // // Convert, wait for completion, and store results // ADC_forceSOC(ADCA_BASE, ADC_SOC_NUMBER0); ADC_forceSOC(ADCA_BASE, ADC_SOC_NUMBER1); ADC_forceSOC(ADCB_BASE, ADC_SOC_NUMBER0); ADC_forceSOC(ADCB_BASE, ADC_SOC_NUMBER1); // // Wait for ADCA to complete, then acknowledge flag // while(ADC_getInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1) ==

false) { } ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1); // // Wait for ADCB to complete, then acknowledge flag // while(ADC_getInterruptStatus(ADCB_BASE, ADC_INT_NUMBER1) ==

false) { } ADC_clearInterruptStatus(ADCB_BASE, ADC_INT_NUMBER1); // // Store results // Linear 0to supply voltage, 0 to 4095 adcAResult0 = ADC_readResult(ADCARESULT_BASE,

ADC_SOC_NUMBER0);//aa0, current sensor module 1 if((adcAResult0>triggerNumber)){ stopFunc(); } adcBResult0 = ADC_readResult(ADCBRESULT_BASE,

ADC_SOC_NUMBER0);//ab0 current sensor module 2 if((adcBResult0>triggerNumber){ stopFunc(); }


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adcBResult1 = ADC_readResult(ADCBRESULT_BASE, ADC_SOC_NUMBER1);//ab1 current sesnror module 3

if((adcBResult1>triggerNumber)){ stopFunc(); } } } void stopFunc(void){ GPIO_writePin(DEVICE_GPIO_PIN_LED1, 1); dutyCycle = 0U; ESTOP0;// software stop } void ledBlinkFun(void){ // // Turn on LED // GPIO_writePin(DEVICE_GPIO_PIN_LED1, 0); // // Delay for a bit. // DEVICE_DELAY_US(50000); // // Turn off LED // GPIO_writePin(DEVICE_GPIO_PIN_LED1, 1); // // Delay for a bit. // DEVICE_DELAY_US(50000); } // // epwm2TZISR - ePWM2 TZ ISR // __interrupt void epwm2TZISR(void) { epwm2TZIntCount++; // // Toggle GPIO to notify when TZ is entered // GPIO_togglePin(11); // // Clear the flags - we will continue to take this interrupt until the TZ // pin goes high. // EPWM_clearTripZoneFlag(EPWM2_BASE, (EPWM_TZ_INTERRUPT |

EPWM_TZ_FLAG_CBC));


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// // Acknowledge this interrupt to receive more interrupts from group 2 // Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP2); } __interrupt void epwm6TZISR(void) { epwm6TZIntCount++; // // Toggle GPIO to notify when TZ is entered // GPIO_togglePin(11); // // Clear the flags - we will continue to take this interrupt until the TZ // pin goes high. // EPWM_clearTripZoneFlag(EPWM6_BASE, (EPWM_TZ_INTERRUPT |

EPWM_TZ_FLAG_CBC)); // // Acknowledge this interrupt to receive more interrupts from group 2 // Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP2); } __interrupt void epwm11TZISR(void)//11 { epwm11TZIntCount++; // // Toggle GPIO to notify when TZ is entered // GPIO_togglePin(11); // // Clear the flags - we will continue to take this interrupt until the TZ // pin goes high. // EPWM_clearTripZoneFlag(EPWM11_BASE, (EPWM_TZ_INTERRUPT |

EPWM_TZ_FLAG_CBC)); // // Acknowledge this interrupt to receive more interrupts from group 2 // Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP2); } __interrupt void epwm8TZISR(void)//8 { epwm8TZIntCount++; // // Toggle GPIO to notify when TZ is entered //


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GPIO_togglePin(11); // // Clear the flags - we will continue to take this interrupt until the TZ // pin goes high. // EPWM_clearTripZoneFlag(EPWM8_BASE, (EPWM_TZ_INTERRUPT |



EPWM_TZ_FLAG_CBC)); // // Acknowledge this interrupt to receive more interrupts from group 2 // Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP2);


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} // // initEPWM2 - Configure ePWM2 // // // TIMING STARTS HERE // void initEPWM2()//1A { EPWM_enableTripZoneSignals(EPWM2_BASE, EPWM_TZ_SIGNAL_CBC1); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH); EPWM_enableTripZoneInterrupt(EPWM2_BASE, EPWM_TZ_INTERRUPT_CBC); EPWM_setTimeBasePeriod(EPWM2_BASE, tbp2); EPWM_setPhaseShift(EPWM2_BASE, Phase2); EPWM_setTimeBaseCounter(EPWM2_BASE, tbc2); EPWM_setTimeBaseCounterMode(EPWM2_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(EPWM2_BASE); EPWM_setClockPrescaler(EPWM2_BASE, EPWM_CLOCK_DIVIDER_4, EPWM_HSCLOCK_DIVIDER_4); EPWM_setCounterCompareValue(EPWM2_BASE, EPWM_COUNTER_COMPARE_A,

dutyCycle);//9 EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); } void initEPWM6()//1B { EPWM_enableTripZoneSignals(EPWM6_BASE, EPWM_TZ_SIGNAL_CBC1); EPWM_setTripZoneAction(EPWM6_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH); EPWM_enableTripZoneInterrupt(EPWM6_BASE, EPWM_TZ_INTERRUPT_CBC);


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EPWM_setTimeBasePeriod(EPWM6_BASE, tbp6); EPWM_setPhaseShift(EPWM6_BASE, Phase6); EPWM_setTimeBaseCounter(EPWM6_BASE, tbc6); EPWM_setTimeBaseCounterMode(EPWM6_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_enablePhaseShiftLoad(EPWM6_BASE); EPWM_setClockPrescaler(EPWM6_BASE, EPWM_CLOCK_DIVIDER_4, EPWM_HSCLOCK_DIVIDER_4); EPWM_setCounterCompareValue(EPWM6_BASE, EPWM_COUNTER_COMPARE_A,

dutyCycle); EPWM_setActionQualifierAction(EPWM6_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM6_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); } void initEPWM11()//3B { EPWM_enableTripZoneSignals(EPWM11_BASE, EPWM_TZ_SIGNAL_CBC1); EPWM_setTripZoneAction(EPWM11_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH); EPWM_enableTripZoneInterrupt(EPWM11_BASE, EPWM_TZ_INTERRUPT_CBC); EPWM_setTimeBasePeriod(EPWM11_BASE, tbp11); EPWM_setPhaseShift(EPWM11_BASE, Phase11); EPWM_setTimeBaseCounter(EPWM11_BASE, tbc11); EPWM_setTimeBaseCounterMode(EPWM11_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(EPWM11_BASE); EPWM_setClockPrescaler(EPWM11_BASE, EPWM_CLOCK_DIVIDER_4, EPWM_HSCLOCK_DIVIDER_4); EPWM_setCounterCompareValue(EPWM11_BASE, EPWM_COUNTER_COMPARE_A,

dutyCycle); EPWM_setActionQualifierAction(EPWM11_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM11_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);


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} void initEPWM8()//2A { EPWM_enableTripZoneSignals(EPWM8_BASE, EPWM_TZ_SIGNAL_CBC1); EPWM_setTripZoneAction(EPWM8_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH); EPWM_enableTripZoneInterrupt(EPWM8_BASE, EPWM_TZ_INTERRUPT_CBC); EPWM_setTimeBasePeriod(EPWM8_BASE, tbp8); EPWM_setPhaseShift(EPWM8_BASE, Phase8); EPWM_setTimeBaseCounter(EPWM8_BASE, tbc8); EPWM_setTimeBaseCounterMode(EPWM8_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(EPWM8_BASE); EPWM_setClockPrescaler(EPWM8_BASE, EPWM_CLOCK_DIVIDER_4, EPWM_HSCLOCK_DIVIDER_4); EPWM_setCounterCompareValue(EPWM8_BASE, EPWM_COUNTER_COMPARE_A,

dutyCycle); EPWM_setActionQualifierAction(EPWM8_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM8_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); } void initEPWM9()//2B { EPWM_enableTripZoneSignals(EPWM9_BASE, EPWM_TZ_SIGNAL_CBC1); EPWM_setTripZoneAction(EPWM9_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH); EPWM_enableTripZoneInterrupt(EPWM9_BASE, EPWM_TZ_INTERRUPT_CBC); EPWM_setTimeBasePeriod(EPWM9_BASE, tbp9); EPWM_setPhaseShift(EPWM9_BASE, Phase9); EPWM_setTimeBaseCounter(EPWM9_BASE, tbc9); EPWM_setTimeBaseCounterMode(EPWM9_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(EPWM9_BASE); EPWM_setClockPrescaler(EPWM9_BASE, EPWM_CLOCK_DIVIDER_4,


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EPWM_HSCLOCK_DIVIDER_4); EPWM_setCounterCompareValue(EPWM9_BASE, EPWM_COUNTER_COMPARE_A,

dutyCycle); EPWM_setActionQualifierAction(EPWM9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); } void initEPWM10()//3A { EPWM_enableTripZoneSignals(EPWM10_BASE, EPWM_TZ_SIGNAL_CBC1); EPWM_setTripZoneAction(EPWM10_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH); EPWM_enableTripZoneInterrupt(EPWM10_BASE, EPWM_TZ_INTERRUPT_CBC); EPWM_setTimeBasePeriod(EPWM10_BASE, tbp10); EPWM_setPhaseShift(EPWM10_BASE, Phase10); EPWM_setTimeBaseCounter(EPWM10_BASE, tbc10); EPWM_setTimeBaseCounterMode(EPWM10_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(EPWM10_BASE); EPWM_setClockPrescaler(EPWM10_BASE, EPWM_CLOCK_DIVIDER_4, EPWM_HSCLOCK_DIVIDER_4); EPWM_setCounterCompareValue(EPWM10_BASE, EPWM_COUNTER_COMPARE_A,

dutyCycle); EPWM_setActionQualifierAction(EPWM10_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM10_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); } // // TIMING ENDS HERE //


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//initTZGPIO - Configure TZ GPIO // void initTZGPIO(void) { // // Set GPIO 12 as as Asynchronous input with pull up enabled // GPIO_setPadConfig(12, GPIO_PIN_TYPE_PULLUP); GPIO_setPinConfig(GPIO_12_GPIO12); GPIO_setDirectionMode(12, GPIO_DIR_MODE_IN); GPIO_setQualificationMode(12, GPIO_QUAL_ASYNC); // // Set GPIO 12 as TZ1 input // XBAR_setInputPin(XBAR_INPUT1, 12); // // Configure GPIO 11 as general purpose GPIO for monitoring when the TZ // Interrupt has been entered // GPIO_setPadConfig(11, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_11_GPIO11); GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT); } // // initEPWMGPIO - Configure ePWM GPIO // void initEPWMGPIO(void) { // // Disable pull up on GPIO 0 and GPIO 2 and configure them as PWM1A and // PWM2A output respectively. // GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_10_EPWM6A);//6 GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_2_EPWM2A);//2 GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_20_EPWM11A);//11 GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_14_EPWM8A);//8 GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_16_EPWM9A);//9 GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD); GPIO_setPinConfig(GPIO_18_EPWM10A);//10 }


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// // Function to configure and power up ADCs A and B. // void initADCs(void) { // // Set ADCCLK divider to /4 // ADC_setPrescaler(ADCA_BASE, ADC_CLK_DIV_4_0); ADC_setPrescaler(ADCB_BASE, ADC_CLK_DIV_4_0); // // Set resolution and signal mode (see #defines above) and load // corresponding trims. // ADC_setMode(ADCA_BASE, EX_ADC_RESOLUTION, EX_ADC_SIGNAL_MODE); ADC_setMode(ADCB_BASE, EX_ADC_RESOLUTION, EX_ADC_SIGNAL_MODE); // // Set pulse positions to late // ADC_setInterruptPulseMode(ADCA_BASE, ADC_PULSE_END_OF_CONV); ADC_setInterruptPulseMode(ADCB_BASE, ADC_PULSE_END_OF_CONV); // // Power up the ADCs and then delay for 1 ms // ADC_enableConverter(ADCA_BASE); ADC_enableConverter(ADCB_BASE); DEVICE_DELAY_US(1000); } // // Function to configure SOCs 0 and 1 of ADCs A and B. // void initADCSOCs(void) { // // Configure SOCs of ADCA // - SOC0 will convert pin A0. // - SOC1 will convert pin A1. // - Both will be triggered by software only. // - For 12-bit resolution, a sampling window of 15 (75 ns at a 200MHz // SYSCLK rate) will be used. For 16-bit resolution, a sampling window // of 64 (320 ns at a 200MHz SYSCLK rate) will be used. // #if(EX_ADC_RESOLUTION == ADC_RESOLUTION_12BIT) ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 15); ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN1, 15); #elif(EX_ADC_RESOLUTION == ADC_RESOLUTION_16BIT) ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 64);


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ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN1, 64); #endif // // Set SOC1 to set the interrupt 1 flag. Enable the interrupt and make // sure its flag is cleared. // ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1); ADC_enableInterrupt(ADCA_BASE, ADC_INT_NUMBER1); ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1); // // Configure SOCs of ADCB // - SOC0 will convert pin B0. // - SOC1 will convert pin B1. // - Both will be triggered by software only. // - For 12-bit resolution, a sampling window of 15 (75 ns at a 200MHz // SYSCLK rate) will be used. For 16-bit resolution, a sampling window // of 64 (320 ns at a 200MHz SYSCLK rate) will be used. // #if(EX_ADC_RESOLUTION == ADC_RESOLUTION_12BIT) ADC_setupSOC(ADCB_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 15); ADC_setupSOC(ADCB_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN1, 15); #elif(EX_ADC_RESOLUTION == ADC_RESOLUTION_16BIT) ADC_setupSOC(ADCB_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 64); ADC_setupSOC(ADCB_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN1, 64); #endif // // Set SOC1 to set the interrupt 1 flag. Enable the interrupt and make // sure its flag is cleared. // ADC_setInterruptSource(ADCB_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1); ADC_enableInterrupt(ADCB_BASE, ADC_INT_NUMBER1); ADC_clearInterruptStatus(ADCB_BASE, ADC_INT_NUMBER1); }

Date post:	12-Sep-2019
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Design and Implementation of a Voltage Step Down DC DC...

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