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Design, Fabrication, and Characterization of Package EmbeddedSolenoidal Magnetic Core Inductors for High-Efficiency
System-In-Package Integrated Voltage RegulatorsM. L. F. Bellaredj 1, A. K. Davis 1, P. Kohl2, M. Swaminathan1, and S. Sandler3
1School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA2School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA
3Picotest, Phoenix, AZ 85085 USA
In this paper, we discuss the design, fabrication, and characterization of package embedded solenoidal inductor using a NiZn ferritemagnetic core material based on the novel fabrication process. The process relies on stencil printing of the magnetic core materialalong with the photolithography and copper electroplating of the inductor’s traces. The electrical parameters of the fabricatedinductors were extracted using a pi-equivalent circuit and showed an average dc resistance of 29 m�, an inductance of 26 nH,and an ac resistance of 2.62 � at 100 MHz, which represents the targeted switching frequency of the system-in-package integratedvoltage regulator. The organic substrate parasitic effects were accounted for through the extraction of an average shunt capacitanceof 1.2 pF and an average parasitic conductance of 0.12 mS at 100 MHz. The measured 10% saturation current of the inductor was9.6 A. The electrical parameters of the fabricated inductors were modeled and showed a good agreement with the measured data.
Index Terms— Integrated voltage regulators (IVRs), magnetic composite material, magnetic core, NiZn ferrite, package embeddedsolenoid inductor, system-in-package (SIP).
I. INTRODUCTION
INTEGRATED voltage regulators (IVRs) [1] provideon-package voltage regulation closer to the load, enabling
faster power management loops with better power integrity andsaving. Inductive IVRs require inductor integration. To reducethe inductor size for IVR miniaturization while significantlyincreasing the inductance density, the use of an integrated low-loss magnetic core inductor, switching at high frequency isrequired. Solenoid inductors [2], [3] can achieve a higherinductance density with reduced substrate parasitic losses (thusimproved the overall IVR efficiency) compared to the planarracetrack [4] and single-via-winding [5] inductors due toconfined parallel magnetic field lines to the substrate. Differentprocesses have been developed for the fabrication of integratedmagnetic core solenoid inductors, with on-silicon technologybeing dominant in the last decades. On-silicon magneticcore solenoid inductors having ferromagnetic (FM) [6]–[11],laminated multilayer (LM) [12]–[22], nanogranular (NG) [23],[24] and ferrite [25], [26] magnetic cores deposited usingelectroplating [6]–[8], [20], sputtering [9]–[11], [12]–[19],[23], [24], electroplating/dip-coating [21], thermal evapora-tion/folding [22], manual filling [25], spin spraying [26] andenclosed in polyimide [6], [10], [11], [15], [23], [24], [26],silicon oxide [7]–[9] or SU-8 [14], [20], [21] insulated, electro-plated copper [15], [12]–[17], [23]–[25], sputtered aluminum[7], [8] windings/vias, or simply wire wound with a magnetwire [22] have been demonstrated. The FM inductors showed
Manuscript received November 5, 2018; revised January 28, 2019; acceptedFebruary 17, 2019. Corresponding author: M. L. F. Bellaredj (e-mail:[email protected]).
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMAG.2019.2901780
high-magnetic core losses resulting from their low resistiv-ity, which make them unsuitable for high-frequency, high-efficiency IVRs. The multiple depositions [12]–[21], stiction(due to copper sacrificial layers etching) [20], [21], and delam-ination risks between the dielectric/metallic layers [12]–[21]and punching/wire wounding [22] increase the LM inductorsprocess complexity. Similarly, the multiple sputtering stepsassociated with the polyimide smoothness requirements [23],[24], the manual filling of the cavity [25], and the verylow-core deposition rate [26] limit the core thickness whileincreasing the NG and ferrite inductors process cost/time.Other limitations of on-silicon inductors include silicon wafercost, poor dielectricproperties, and thin windings thickness(few microns) to comply with the CMOS metallization layers,which increases the dc resistance of the inductors, limitingtheir power density capabilities, and the IVR overall efficiency.Glass [27], [28] and ceramic [29], [30] dielectric substrateshave been considered as alternatives to silicon for solenoidinductors. On-glass inductors were fabricated using electro-plated NiFe cores manually placed [27] or wrapped withthe electroplated copper vias/windings, electrically insulatedusing a planarized polyimide layer [28]. The ceramic inductors[29], [30] were fabricated in low-temperature co-fired ceram-ics (LTCC) technology with printed silver windings/vias insidea ceramic stack enclosing a ferrite core. However, the glass’sbrittleness and difficult processing as well as the high-LTCCfiring temperature pose serious challenges for inductor andIVR integration. Compared to inorganic substrates, organicpackages are a valuable option for inductors integration dueto their low cost, low losses, low processing temperatures(<200 °C), and multilayer stacking/lamination capability.On-package NG core inductors were fabricated [31] byenclosing a sputtered NG film between the patterned bottom
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and electroplated top copper windings covered with an organicdielectric layer and connected through laser-drilled coppervias. The inductors showed a limited core thickness with arough printed wiring board (PWB) surface, which degrades thecore permeability. On-package bondwire inductors [32], [33]were built by fully covering the aluminum bondwires in amanually brushed magnesium zinc (MgZn) ferrite compos-ite [32], [33] or by assembling a laminated stack of Vit-rovac 6155/dielectric tape and placing it between aluminumbondwires [34]. Although simple and relatively cost effec-tive, the process [32]–[34] is limited by the bondwire size(diameter and thickness), material (aluminum and gold), andinter-windings separation due to the wirebonder head size.Moreover, the hand-brushed core deposition [32], [33] lacksprecision and can damage the bondwire windings. As an alter-native approach, we showed [35]–[37], [39] the advantages ofa system-in-package (SIP) solution using package embeddedmagnetic core solenoid inductors with magnetic compositematerials [37] for implementing a high-efficiency IVR. Inthis paper, a novel fabrication process of package embed-ded magnetic core solenoid inductors is demonstrated basedon the previous design explorations [37], [39]. The processallows the deposition of a very thick magnetic core comparedwith [6]–[21], [23], and [24] using a simple and cost-effective printing process. An organic-substrate-compatiblecomposite magnetic material [37] was used for the magneticcore to allow very good adhesion to the substrate with reducedbuilt-in stress at the core–substrate interface. The good dielec-tric properties of the composite material [37], [40], [41]avoid the use of an insulation layer at the core/windingsinterface, which simplifies the process and reduces its overallcost/time. Moreover, the process takes the advantage of theprinted core shape to deposit the inductor’s top windingswhile simultaneously interconnecting them to the inductor’sbottom windings without vertically patterned vias after succes-sive planarization/photolithography steps [6]–[8], [10]–[17],[20], [2]–[24], [26], [28]–[30]. This also simplifies consid-erably the process compared with [6]–[8], [10]–[17], [20],[2]–[24], [26], and [28]–[31] while reducing significantly
the dc resistance resulting from the contact resistance at thevias/windings interface. The rest of this paper is organized asfollows. In Section I, the design/modeling procedure of theinductors is presented. In Section III, the fabrication processof the inductors is discussed in detail. The characterizationresults of the fabricated inductors are provided in Section IVand compared with the simulation results.
II. DESIGN AND MODELING
The goal was to design embedded solenoidal inductorsfor a four-phase SIP buck converter [36], [37], [39] with aminimum inductance of 25 nH/phase at a 100 MHz switchingfrequency [39]. The 3-D solenoid inductors [Fig. 1(a)] weredesigned with a magnetic core enclosed in copper windings,built on the top side of a two-copper-layer FR4 PWB (70 μm-thick copper for each side and 500 μm-thick FR4 substrate).The top copper layer was used to define the inductor bottomwindings, which were covered with the magnetic core, and thecontact pads for the top copper windings. The bottom copper
Fig. 1. (a) Structure of the designed inductors (drawings not to scale).(b) Simulation process flow: the inductor is built in HFSS, then Rdc, L , Racare extracted (S–Y parameters and conversion into a pi-equivalent circuit), andthe IVR efficiency is estimated using the analytical approach in [39]. Then,the procedure is repeated for multiple times by changing the inductor designparameters, and the efficiency is recomputed until the highest IVR efficiencyis obtained for a given inductor design.
layer was used as a ground plane for the electromagnetic inter-ference reduction. A NiZn ferrite epoxy composite magneticmaterial having good insulation properties combined with arelatively high-permeability and low-electromagnetic losses athigh frequency was chosen as the core material [37].
Consequently, no insulation layer between the magnetic coreand the copper windings [40], [41] was used in the designedinductor compared with the structure in [39]. Moreover,the dome-like magnetic core shape resulting from the stencilprinting deposition process was also considered in the designinstead of a rectangular core [39] by using experimentallymeasured core profiles in the simulations to accurately modelthe inductors. The design parameters of the inductors werethe magnetic core thickness tmag_core, length lmag_core, widthWmag_core, number N , and width Wtrace of the copper windingswhile the overall area A and the windings thicknesses werekept fixed. A 3-D model of the solenoid inductor of Fig. 1(a)was created in a full-wave simulator (Ansys Electronics Desk-top ver. 2015.2) to account for the complex electromagneticfield distributions and loss effects in the magnetic core andthe copper windings. The measured complex permeabilityspectrum of the NiZn ferrite magnetic material [37], wasused into the solver to accurately represent the magneticcore. The simulations were run from 10 MHz to 1 GHz,and the results were extracted as frequency-dependent two-port network parameters (S-parameters) and converted into asimple pi-equivalent circuit, as shown in Fig. 1(b), where theseries inductance L and resistance Rac represent the inductor’seffective inductance and losses, respectively, while the parallelconductance and capacitance represent the inductor’s parasiticsdue to the organic substrate and the copper ground plane Api-topology is a simple and an acceptable representation ofthe inductor since the targeted switching frequency of theIVR (100 MHz) is below the first self-resonant frequency ofthe inductor (>1 GHz), and consequently, the impedance is
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BELLAREDJ et al.: DESIGN, FABRICATION, AND CHARACTERIZATION OF PACKAGE EMBEDDED SOLENOIDAL MAGNETIC CORE INDUCTORS 3
Fig. 2. Extracted RF parameters of the designed solenoid inductor. (a) Inductance. (b) AC resistance. (c) Parasitic capacitance. (d) Parasitic conductance.
Fig. 3. Designed boards with (a) inductors’ bottom windings, (b) TRL deembedding structures, and (c) stencil design for magnetic core printing.
mainly inductive [37]. The dc resistances Rdc of the designedinductor was obtained in Ansys Maxwell ver.2015.2. Theextracted inductor electrical parameters (Rdc, L, and Rac) wereused as inputs to evaluate the impact of the inductor on theoverall IVR efficiency, following the same analytical approach(based on the small-ripple approximation representing theinductor current as a triangular waveform) described in [34]and [37] which considers all the major loss components fromthe buck chip, the passives (inductor and output capacitor),and power delivery network. Based on the overall IVR peakefficiencies (at optimum load) evaluation, multiple cycles ofsimulation and modification of the inductor design parameterswere carried out [Fig. 1(b)] until the highest overall IVRefficiency was obtained for a given inductor geometry withan inductance close to 25 nH. The inductor design approachis summarized in Fig. 1(b). The extracted RF parameters
and the dimensions of the final inductor design are shownin Fig. 2 and Table I, respectively, where an inductanceof 27.8 nH was obtained at 100 MHz, which represents a 5×inductance density increase compared to an air core inductorof the same size. Based on the dimensional parameters ofthe magnetic core and the inductor (Table I), the organicsubstrate (PWB) for the inductor fabrication and the stencil formagnetic core deposition (Fig. 3) were designed in Cadenceand AutoCAD, respectively. The PWB design included twopatterns of the bottom copper windings connected to SMApads with feedlines as well as process alignment marks.Thru–reflect–line (TRL) deembedding structures were alsodesigned for the electrical characterization of the inductors.The stencil design had two openings for magnetic coreprinting and alignment marks for precise alignment withthe PWB.
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TABLE I
DIMENSIONAL PROPERTIES AND MAIN FIGURES OF MERIT (AT 100 MHZ) OF THE DESIGNED INDUCTOR (A COMPARISON TO AN AIR
CORE INDUCTOR OF SIMILAR SIZE IS INCLUDED.)
Fig. 4. Fabrication process flow of the solenoid inductors. (a) Initially two-copper layer, FR4 PWB substrate. (b) PWB etching to define the bottom coppertracks. (c) Stencil printing of the NiZn ferrite magnetic core. (d) Photoresist deposition and patterning using photolithography. (e) Sputter deposition of a seedlayer of 50 nm Cr + 200 nm Au. (f) Liftoff process to remove the photoresist and pattern the seed layer for the top windings electroplating. (g) Photoresistdeposition and patterning using photolithography. (h) Electrodeposition of the top copper windings. (i) Removal of the photoresist. (j) Photoresist depositionand patterning using photolithography. (k) Seed layer and photoresist removal.
III. EXPERIMENT
The fabrication process flow of the solenoid inductor isshown in Fig. 4. A 640 μm thick, two-copper layer FR4 PWB(70 μm thick for both copper layers and 500 μm-thickFR4 layer) was used as a substrate Fig. 4(a). First, the bottominductor windings on the top side of the substrate were definedusing the standard PWB copper etching process Fig. 4(b). Thecopper traces width, separation, and thickness were measuredusing an optical microscope and the Veeco Dektak 150 surfaceprofilometer and were found to be around 450 μm, 225 μm[Fig. 5(a)], and 74 μm [Fig. 5(c)], respectively. Then, the mag-netic core was deposited on the top of the bottom copperwindings Fig. 4(c) by stencil printing a custom preparedFR4 compatible composite magnetic paste, made by mixinga magnetic powder (FP350 NiZn ferrite from pptechnology)with an epoxy polymer at 85 wt% [36] using the MPM SPM7279 Semiautomatic Stencil Printer (PPM Inc.). The substratewas cured for 1 h at 180 °C to form the magnetic compositecore as shown in Fig. 5(b). The cured core showed no reactionto commonly used solvents, a very strong adhesion to thesubstrate, and good dielectric properties [36] assessed by ameasured very high-dc resistance (beyond 30 M�) whichavoided the use of insulation layers between the magnetic coreand the copper windings [40], [41].
The measured profile of the magnetic core is shownin Fig. 5(c), where the average measured core thickness isaround 350 μm. After the magnetic core deposition, a firstphotolithography step was used to pattern a seed layer onthe top of the magnetic core for the electroplating of thetop windings. A thick photoresist mold (>74 μm which isthe bottom windings thickness) was required to ensure thefull coverage of the inter-pads space of the bottom copperwindings with photoresist. Intervia 65A BPN photoresist wasspray coated directly on the top of the magnetic core andthe bottom copper windings using the Suss Delta Alta Spraycoater. A photoresist thickness of 100 μm was obtained,
and no softbaking was applied to avoid trapped air bubblesin the photoresist mold. The photoresist was exposed usingthe non-contact lithography mode of the EVG 620 Maskaligner at 365 nm wavelength and 5 mW/cm2 for 200 s. Theexposed photoresist was then developed in RD6 developer for5 min Fig. 4(d). A 50 nm chromium/200 nm gold seed layerwas then sputtered at 5 mtorr using the Unifilm multisourcesputtering system at a rate of 8.3 and 33 A/s for chromiumand gold, respectively, Fig. 4(e). A liftoff process [Fig. 4(f)]was used to pattern the seed layer and remove the photoresistFig. 5(d). A second photolithography step Fig. 4(g) similar tothe previous photolithography step was required to fabricatethe photoresist mold for the top windings electroplating.A 170 μm-thick Intervia 65A BPN photoresist was spraycoated directly on the top of the patterned seed layer to allowthe deposition of very thick copper windings to reduce thedc resistance of the inductor. The photoresist was exposedfor 330 s and then developed in RD6 for 8 min. The topcopper windings were then electroplated Fig. 4(h) using anacid copper-based electroplating bath at a current density of10 mA/cm2 for a plating time of 6 h. The photoresist moldwas then removed in acetone solvent Fig. 4(i). A third pho-tolithography step was required to protect the plated top copperwindings from the seed layer etching solutions. An 8 μm-thickAZ 4620 photoresist was spray coated on the top of theinductor, softbaked for 2 min at 120 °C, and exposed for 100 s.The photoresist was then developed in RD6 for 4 min Fig. 4(j).The seed layer was removed Fig. 4(k) using standard goldand chromium etching solutions from Sigma-Aldrich. Finally,the AZ 4620 photoresist was removed in acetone Fig. 4(i).An example of a fabricated inductor is shown in Fig. 5(e).A measured profile of the electroplated copper top windingsis shown in Fig. 5(f) where around 76.5 μm-thick copper wasdeposited on the top of the magnetic core. The inductors’ dcresistance was measured using the four wires mode of theHP 34401A multimeter. The RF parameters of the inductors
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BELLAREDJ et al.: DESIGN, FABRICATION, AND CHARACTERIZATION OF PACKAGE EMBEDDED SOLENOIDAL MAGNETIC CORE INDUCTORS 5
Fig. 5. Different steps of the fabrication process. (a) Patterned bottom copper windings. (b) Printed magnetic core on the top of the bottom copper.(c) Measured core profile (lateral scan). (d) Patterned seed layer after the liftoff process. (e) Optical view of the fabricated inductor. (f) Measured profile ofthe top copper windings.
Fig. 6. Comparison of the measured and simulated (updated) inductor RF parameters. (a) Inductance. (b) AC resistance. (c) Parasitic capacitance. (d) Parasiticconductance.
were characterized between 20 MHz and 1 GHz using theAgilent H8363B Vector Network Analyzer. A standard SOLTcalibration was carried out, followed by the measurementof the two port S-parameters of the inductors and the TRLdeembedding structures which were then mathematically post-processed to extract the effective inductors RF parameters.The dc saturation current of the inductors was measured by
coupling a dc current delivered by a power supply to the acvoltage of the VNA using a bias tee provided by Picotest.
IV. RESULTS AND DISCUSSION
Different inductors were characterized and showed an aver-age dc resistance of 29 m� while the inductance variedfrom 25.64 to 31 nH (at 100 MHz) which corresponds to an
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6 IEEE TRANSACTIONS ON MAGNETICS
Fig. 7. (a) Measured Q factor. (b) Inductance variation due to the applied dc current.
TABLE II
UPDATED SIMULATION PARAMETERS BASED ON EXPERIMENTAL DATA
TABLE III
EXTRACTED RF PARAMETERS AND COMPARISON TO SIMULATION DATA
average value of 28.32 nH with ±3.32 nH deviation from thetargeted minimal 25 nH inductance. Fig. 6 shows an exampleof the extracted RF parameters of an inductor. The inductancedecreased due to the permeability decrease of the NiZn ferritecomposite beyond its ferromagnetic resonance frequency [36]while the ac resistance increased, resulting from the pro-nounced magnetic core and RF (proximity and eddy current)losses at high frequency. The inductor showed a qualityfactor Q of 6.37 at 100 MHz with a maximum of 11.33 at41.1 MHz [Fig. 7(a)]. The inductor models (section) wereupdated based on the measured dimensions of the fabricatedinductors (Table II), and the simulation results were comparedwith the experimentally measured RF parameters as shownin Fig. 6 and summarized in Table III. A good match isobserved between the experimental and modeling results.The discrepancies observed for C2, G2, and Rac (beyond300 MHz) could be attributed to errors resulting from thedeembedding process which was carried out using deembed-ding structures defined on a separate board. Moreover, the usedpi-model assumed an ideal two-port inductor model, whichimplies perfectly symmetric ports (thus C1_sim = C2_simand G1_sim = G2_sim), which was not the case for thefabricated inductors due to the fabrication process (printedcore and windings definition) and the deembedding procedurewhich explains the differences observed between C2, G2 andC2sim, G2sim, respectively. The effect of the dc current onthe inductance is shown in Fig. 7(b), where 1.94 nH decreaseis observed for 6 A at 41.1 MHz which corresponds to a6.2% drop from the unbiased initial inductance value. The 10%saturation current of the inductor is estimated accordingly to
be around 9.6 A (at maximum Q), which is higher than thetargeted maximum load current for the IVR (2.5 A/phase).
V. CONCLUSION
The SIP-based IVRs represent a valuable approach toachieve combined high-integration density and efficiency forthe point-of-load voltage regulation. In this paper, a novelon-package magnetic core solenoidal power inductor wasdemonstrated for the implementation of a high efficiency,100 MHz switching SIP-based buck-type IVR. The optimuminductor design was selected based on the highest achievableoverall IVR efficiency. The inductor was fabricated on anorganic substrate using stencil printing and non-contact litho-graphy processes. A pi-equivalent circuit and standard TRLdeembedding were used for the inductor characterization, anda good match was obtained with the modeling results. Thedeveloped fabrication process will be used for the integra-tion of package embedded magnetic core solenoidal powerinductors in both single phase and four phase SIP-based IVRsallowing three voltage conversion ratios (5 V:1 V, 3 V:1 V,and 1.7 V:1 V).
ACKNOWLEDGMENT
This work was supported in part by the Power Deliveryfor Electronic Systems Consortium at Georgia Tech and inpart by the National Science Foundation under Grant ECCS-1542174. This work was performed in part at the GeorgiaTech Institute for Electronics and Nanotechnology, Atlanta,GA, USA, and a member of the National NanotechnologyCoordinated Infrastructure.
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BELLAREDJ et al.: DESIGN, FABRICATION, AND CHARACTERIZATION OF PACKAGE EMBEDDED SOLENOIDAL MAGNETIC CORE INDUCTORS 7
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