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Design GoalDesign GoalDesign an Analog-to-Digital Conversion chip Design an Analog-to-Digital Conversion chip to meet demands of high quality voice to meet demands of high quality voice applications such as: Digital Telephony, applications such as: Digital Telephony, Digital Hearing Aids and VOIP.Digital Hearing Aids and VOIP.
TEAM W3:TEAM W3:Digital Voice Processor 525Digital Voice Processor 525
Jarrett Avery (W3-1)Jarrett Avery (W3-1)Sean Baker (W3-2)Sean Baker (W3-2) Huiyi Lim (W3-3)Huiyi Lim (W3-3)
Sherif Morcos (W3-4)Sherif Morcos (W3-4) Amar Sharma (W3-5)Amar Sharma (W3-5)
Date: 3/1/2006
Component Layout &
Floorplan
Design Manager: Abhishek Design Manager: Abhishek JajooJajoo
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StatusStatus Design ProposalDesign Proposal
Project chosen: 16 bit Delta-Sigma ADCProject chosen: 16 bit Delta-Sigma ADC Basic specs definedBasic specs defined
ArchitectureArchitecture Matlab simulatedMatlab simulated Behavioral Verilog simulatedBehavioral Verilog simulated Structural Verilog simulatedStructural Verilog simulated
SchematicSchematic Digital – All modules created including top-levelDigital – All modules created including top-level Analog – All modules except modulator completedAnalog – All modules except modulator completed
FloorplanFloorplan Revised floorplan due to changes in designRevised floorplan due to changes in design Analog component sizes chosen and digital design Analog component sizes chosen and digital design
completedcompleted Simulation/VerificationSimulation/Verification
All digital modules simulated and verified at top-All digital modules simulated and verified at top-levellevel
LayoutLayout Basic components (gates, full adder, flip-flop) Basic components (gates, full adder, flip-flop)
completedcompleted Sinc filter bit slice about 60% completeSinc filter bit slice about 60% complete
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Algorithm DetailAlgorithm Detail
Decimation (Sinc Filter,
Downsample)
Measure PeakAmplitude
(Peak Input Indicator)
DigitalOutput
DigitalPeakIndicator
AnalogInput Lowpass Filter
Analog to DigitalConversion
(Delta-SigmaModulator)
Analog
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Analog Design ProgressAnalog Design Progress
Optimized component sizes for Optimized component sizes for low-pass filter and modulatorlow-pass filter and modulator
Low-pass filter schematic and Low-pass filter schematic and layout completedlayout completed
Op-amp transistor level Op-amp transistor level schematic completed but in schematic completed but in need of tuningneed of tuning
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Algorithm DetailAlgorithm Detail
Decimation (Sinc Filter,
Downsample)
Measure PeakAmplitude
(Peak Input Indicator)
DigitalOutput
DigitalPeakIndicator
AnalogInput Lowpass Filter
Analog to DigitalConversion
(Delta-SigmaModulator)
Digital
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Changes to Digital Changes to Digital DesignDesign
Digital portion of design depends heavily Digital portion of design depends heavily on structure and topology of analog designon structure and topology of analog design
Analog design changed from 2Analog design changed from 2ndnd order order modulator to 1modulator to 1stst order order
Digital sinc filter must also change – from Digital sinc filter must also change – from 33rdrd order to 2 order to 2ndnd order order
Adder and register widths must also Adder and register widths must also changechange width = order * log2(oversampling factor)width = order * log2(oversampling factor) = 2 * log2(256) = 2 * 8 = 16 bits= 2 * log2(256) = 2 * 8 = 16 bits
PII comparators and registers also reduced PII comparators and registers also reduced to 16-bitto 16-bit
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Updated Sinc FilterUpdated Sinc Filter
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New Sinc Filter New Sinc Filter SchematicSchematic
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Changes to Digital Design Changes to Digital Design (cont’d)(cont’d)
Fixed problem relating to Nyquist clockFixed problem relating to Nyquist clock Added buffers to clean up signalAdded buffers to clean up signal Changed Nyquist clock positive edge to occur on Changed Nyquist clock positive edge to occur on
negative edge of oversampled clocknegative edge of oversampled clock Changed full adder design to fix glitches Changed full adder design to fix glitches
occurring on sum outputsoccurring on sum outputs Glitches caused by new inputs overlapping with Glitches caused by new inputs overlapping with
old carry input due to slow carry out pathold carry input due to slow carry out path Original design used mirror adder with inverters Original design used mirror adder with inverters
on carry outputon carry output New design eliminates inverters through New design eliminates inverters through
Boolean manipulationsBoolean manipulations Result is faster path through carry out and Result is faster path through carry out and
elimination of glitches on sum outputselimination of glitches on sum outputs
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Changes to Full AdderChanges to Full Adder
Mirror adder produces complemented Mirror adder produces complemented carry and sum outputscarry and sum outputs
Invert inputs for every other bit & Invert inputs for every other bit & inverters for carry can be eliminated, inverters for carry can be eliminated, reducing delayreducing delay
Diagram courtesy of Professor Ken Mai (ECE 722)Diagram courtesy of Professor Ken Mai (ECE 722)
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Top-level Schematic Top-level Schematic SimulationSimulation
Verified top-level digital module Verified top-level digital module (i.e. decimator) against Verilog (i.e. decimator) against Verilog structural model using simulated structural model using simulated analog inputanalog input
Transistor level schematic Transistor level schematic simulated in Cadence Spectresimulated in Cadence Spectre
Analog output compared against Analog output compared against structural digital outputsstructural digital outputs
Outputs match for both sinc filter Outputs match for both sinc filter and PII function sub-modulesand PII function sub-modules
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Top-level Digital Top-level Digital SchematicSchematic
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Structural Verilog Structural Verilog OutputOutput
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Schematic Spectre Schematic Spectre Output (Y)Output (Y)
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Schematic Spectre Schematic Spectre Output (Max)Output (Max)
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Schematic Spectre Schematic Spectre Output (Min)Output (Min)
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Top-level Simulation Top-level Simulation (cont’d)(cont’d)
Simulated top-level module Simulated top-level module with analog behavioral model with analog behavioral model used earlier with behavioral used earlier with behavioral Verilog modelsVerilog models
Output is a digitized sine waveOutput is a digitized sine wave This verifies the digital portion This verifies the digital portion
of our design at the transistor of our design at the transistor levellevel
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Mixed Signal SimulationMixed Signal Simulation
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Digital Design Digital Design MeasurementsMeasurements
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Critical PathCritical Path Our critical path located in sinc filterOur critical path located in sinc filter Consists of two 16-bit subtracters Consists of two 16-bit subtracters
connected in seriesconnected in series Critical path delay = 4.222 nsCritical path delay = 4.222 ns Maximum clock frequency = 237 Maximum clock frequency = 237
MHzMHz Speed is not an issue since we are Speed is not an issue since we are
operating at 5.12 MHz and 20 KHzoperating at 5.12 MHz and 20 KHz Area and power consumption much Area and power consumption much
more important parametersmore important parameters
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Layout of Basic Layout of Basic ComponentsComponents
We have completed layout of some We have completed layout of some basic modulesbasic modules Legacy layouts of primitive gates and 2-Legacy layouts of primitive gates and 2-
input muxinput mux New layouts of flip-flop and full adder New layouts of flip-flop and full adder
cellscells Started bit slice of sinc filter moduleStarted bit slice of sinc filter module
Bit slice contains 4 full adders, 5 flip-Bit slice contains 4 full adders, 5 flip-flops, and some invertersflops, and some inverters
When finished, will stack 16 slices on top When finished, will stack 16 slices on top of each other to create 16-bit 2of each other to create 16-bit 2ndnd order order sinc filtersinc filter
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Full AdderFull Adder
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D Flip-FlopD Flip-Flop
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Sinc Filter Bit Slice (in Sinc Filter Bit Slice (in progress)progress)
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Updated FloorplanUpdated Floorplan Major changes to designMajor changes to design
Analog modulator changed to 1Analog modulator changed to 1stst order order Digital sinc filter changed to 2Digital sinc filter changed to 2ndnd order order Adder and register widths changed to 16 bitsAdder and register widths changed to 16 bits
All these changes have reduced size of All these changes have reduced size of design considerablydesign considerably
Digital portion contains only 6,400 Digital portion contains only 6,400 transistorstransistors
Analog portion contains 21 large Analog portion contains 21 large transistors plus several extremely large transistors plus several extremely large (150 (150 μmμm x 50 x 50 μm) resistors and μm) resistors and capacitorscapacitors
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FloorplanFloorplan
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Problems and QuestionsProblems and Questions Simulating total designSimulating total design
Spectre/ModelSim comparison simulation took Spectre/ModelSim comparison simulation took over 8 hoursover 8 hours
AHDL mixed-signal simulation took 10 hoursAHDL mixed-signal simulation took 10 hours How are we going to make changes and test How are we going to make changes and test
them out?them out? Analog components still extremely large Analog components still extremely large
even for 1even for 1stst order modulator order modulator May cause overall area to exceed limit of May cause overall area to exceed limit of
300,000 300,000 μμm²m² Layout of PII moduleLayout of PII module
Less opportunities for bit slicingLess opportunities for bit slicing Some large components – 24-bit counterSome large components – 24-bit counter
Use of GPDK design kitUse of GPDK design kit Do we have to convert?Do we have to convert?