DESIGN OF 200V N·TYPE SUPERJUNCTION LATERAL INSULATED GATE BIPOLAR TRANSISTOR ON PARTIAL

SILICON ON INSULATOR

Elizabeth Kho Ching Tee

PhD of Electronic Engineering 2014

ACKNOWLEDGEMENT

I would like to express my Sincere gratitude and appreciation to both of my

supervisors, Dr Wan Azlan bin Wan Zainal Abidin and Mr. Ng Liang Yew for their guidance,

support and patience upon the completion of my Phd. I would like to thank my co-supervisors

seniors in XFAB Sarawak Sdn. Bhd., Dr Alexander Holke, Dr Deb Kumar Pal, Dr Steven

John Pilkington and Mr Tia Swee Hua for their technical support and encouragement on my

research. I would also like to thank XFAB Sarawak Sdn. Bhd. in providing me the good

environment and financial support toward my research work. In addition, I would hke to

thank to Bahagian Biasiswa, Kementerian Pengajian Tinggi to approve my application of the

PhD Industri grant that give me full financial support in continuing my research.

I am highly indebted to my working partner, Prof. Dr Florin Udrea and Dr Marina

Antoniou from the Department of Electrical Engineering, Cambridge University for their

invaluable guidance and advices during the research progress. I am extremely thankful for

their meticulous care in reviewing all publications related to this research work.

I would like to extend my thanks to my parents and my family for the continuous

mental support, strength and encouragements during the years of my PhD work.

I

ABSTRACT

( Lateral insulated-gate bipolar transistors (LIGBTs) have long been proposed for use in

integrated Power Integrated Circuits (PICs). LIGBTs can be fabricated on either bulk silicon

substrate or silicon-on-insulator (SOl). The later have been favored by most Integrated PICs

due to its superior isolation. However, there are some weaknesses associated with SOl

LIGBTs such as reduced Reduce Surface Field (RESURF) effect, higher forward voltage drop

(VON), more severe self heating as weU as undesired back-gate and side-gate impacts. The

partial SOl (PSOI) concept is subsequently proposed to improve the existing weaknesses in

SOl technology such as alleviates the crowding effect of the electrical potential lines in the

confined silicon and dissipates the heat more effectivelj

For most high voltage (HY) double-diffused metal-ox ide-semiconductor field effect

transistor (OMOS) structures, RESURF is the main concept applied to optimize the trade-off

in getting high breakdown voltage (BY) and low specific on resistance (RON). The

introduction of superjunction concept featuring alternating nand p layers in the drift region

proved to be effective in breaking the 'silicon limit' and resulted in drastically reduced RON

DMOS. A charge baJanced superjunction allows the depletion of the entire drift region

happens at a lower voltage which yields a uniform electric field distribution. The

superjunction concept with nand p layers arranged in the device width direction was later

extended into both discrete IGBTs and LIGBTs.

The main motivation of this research is to design and realize a LIGBT that combines

the superjunction with nand p layers arranged in lateral direction approach with the PSOI

concept. To realize the superjunction LIGBT, a minimum one additional mask layer is added

ii

to the O.18f..lm partial SOl HV process. This work presents and delivers a novel superjunction

LIGBT with BV of 220V, Von of 1.55V, 1.75V and 2.30V at 100Ncm2, l50Ncm2 and

300A/cm2 respectiveJy. The measured turn-off time is 130ns under clamped inductive

switching circuit. The device is also evaluated at higher temperature and found to have

negligible VON increase with the increase of temperature up to 448K. This research work well

proving the success in combining the superjunction and partial SOl into a LlGBT device.

iii

ABSTRAK

Terlindung Get Transistor Dwikutub Sisi (LIGBTs) telah lama dicadangkan untuk

kegunaan dalam Litar Bersepadu Kuasa (PIC) yang berintigrat. LIGBTs boleh direka sarna

ada atas substrat silikon pukal atau Silikon-Atas-Penebat (SOl). LIGBTs atas SOl telah

digemari oleh kebanyakan PIC yang berintigrat kerana pengasingan yang unggul. Walau

bagaimanapun, terdapat beberapa kelemahan yang dikaitkan dengan LIGBTs atas SOl seperti

kekurangan dalam Pengurangan Medan Permukaan (RES URF), lebih tinggi Boltan Hadapan

Jatuh (YON) dan pemanasan sendiri yang lebih teruk. Separa SOl (PSOI) konsep kemudiannya

telah dicadangkan untuk mengurangkan kelemahan yang sedia ada dalam teknologi SOl

sepel1i melegakan kesan kesesakan garis potensi elektrik dalam silikon terkurung dan

menyelerak haba dengan lebih berkesan.

Untuk Yoltan Tinggi (HY) Dua Disebarkan Logam-Oksida Semikonduktor Transistor

Kesan Medan (DMOS) struktur, RESURF adalah konsep utama yang digunakan untuk

mengoptimumkan perdagangan dalam mendapatkan kerosakan voltan tinggi (BY) dan khusus

rendah rintangan (RON). Pengenalan konsep superjunction memaparkan bersilih ganti lapisan

n dan p di rantau hanyut terbukti berkesan dalam memecahkan ' had silikon ' dan

menyebabkan kekurangan DMOS RON secara drastik . Caj superjunction yang seimbang

membolehkan pengurangan rantau hanyut keseluruhan berlaku pad a voltan yang lebih rendah

dan membantu penghasilan taburan medan elektrik yang seragam. Konsep superjunction

dengan n dan p lapisan disusun dalam arah lebar peranti kemudiannya diperluaskan ke dalam

kedua-dua IGBTs diskret dan LIGBTs.

iv

Motivasi utama kajian ini adalah untuk membina dan merealisasikan LIGBT yang

menggabungkan superjunction dengan lapisan n dan p disusun dalam pendekatan ke arah sisi

dengan konsep PSOl itu. Bagi merealisasikan superjunction LIGBT, satu lapisan topeng

ditambah kepada O.18Jlffi SOl separa HV proses. Kerja ini membentangkan dan

menyampaikan novel sisi superjunction LIGBT dengan BV 220V, VON 1.55V, 1.75V dan

2.30V di lOONcm2, 150Ncm2 dan 300Ncm2

. Masa tutup l30ns dicapai di bawah induktif

diapit litar bertukar. Peranti ini juga dinilai pada suhu yang lebih tinggi dan didapati

mempunyai sedikit peningkatan VON sahaja dengan peningkatan suhu sehingga 448K. Kajian

ini telah menbuktikan kerjayaan dalam penggabungan superjunction dan SOl separa dengan

LIGBT.

v

TITLE

CHAPTER 1

1.1

1.2

1.3

IA

1.5

1.6

CHAPTER 2

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2A

2.2.5

2.2.6

2.2.7

2.2.8

I'osat Khldnnt M kJuml t Akad~ lh UNIVERSm MALAYSIA SARAWAK

T ABLE OF CONTENT

ACKNOWLEDGEMENT

ABSTRACT

ABSTRAK

T ABLE OF CONTENT

LIST OF TABLES

LIST OF FIGURES

LIST OF ABBREVIATIONS

INTRODUCTION

Overview

Statement of Problems

Objectives

Expected Outcomes

Contribution of the Research

Outline of the Dissertation

LITERATURE REVIEW

Overview of Insulated Gate Bipolar Transistors

(IGBTs)

Discrete IGBTs

Early Discrete IGBTs

Planar Gate IGBT

Trench Gate IGBT

Soft Punch Through IGBT

Injection Enhanced IGBT

Carrier Stored Trench Gate Bipolar Transistor

High-Conductive IGBT

Supeljunction Bipolar Transistor

PAGE

i i-iii

lV-V

vi-viii

Xl

xii-xviii

xix -xxiii

1-5

1-2

2

4

4

4

5

6-85

6-8

9-22

9-12

12-13

13-15

15-16

17-18

18-19

19-20

20-22

vi

TITLE PAGE

2.3 Integrated IGBTs or LIGBTs 23-83

2.3.1 Overview 23-24

2.3.2 Junction Isolation LIGBTs 24-49

2.3.3 Silicon-On-Insulator LIGBTs 49-68

2.3.4 Partial Silicon-On-Insulator LIGBTs 68-75

2.3.5 Membrane LIGBTs 76-84

2.4 Summary 85

CHAPTER 3 DESIGN AND FABRICATION OF LIGBT 86-98

3.1 Overview 86-87

3.2 Process Flow and Simulation 88-95

Process Flow Description and Process 3.2.1 88-90

Simulation Considerations

Two-dimension Process Simulation for Charge 3.2.2 91-95

Balance of Superjunction

3.3 Device Characterization and Simulation 95-98

3.3.1 Off-state Condition 95

3.3.2 On-state Condition 96

3.3.3 Transient Condition 96-98

3.4 Summary 98

CHAPTER 4 RESULTS AND DISCUSSIONS 99-152

4.1 Overview 99

4.2 Proposed Structure Description 99-103

Silicon Result and Performance Analysis 944.3

4.3.1 Off-state Condition 103-116

4.3.2 On-state Condition 116-142

4.3.3 Transient Behavior and Discussions 142-151

4.4 Summary 152

vii,

TITLE PAGE

CHAPTER 5 CONCLUSIONS AND

RECOMMENDATIONS 153

5.1 Conclusions of the Research 153-155

5.2 Recommendations for Future Work 155-156

REFERENCES 157-170

APPENDIXES 171-210

A Process Simulation Figures

Superjunction N-type LIGBT

for Lateral 171-173

B ENCON 2011: Overview of IGBT 174-177

C ISPSD 2013: 200Y Lateral Superjunction Lateral

IGBT Fabricated on Partial SOl 178-181

ENCON 2013: Methods to Suppress Earlier

D Leakage In 200Y Superjunction LIGBT on 182-186

Partial SOl

IOSR-JEEE: A Review of Techniques used In

E Lateral Insulated Gate Bipolar Transistor 187-204

(LIGBT)

F IEEE-EDL: 200Y Lateral Supeljunction LIGBT

on Partial SOl 205-207

G IEEE-TED: 2()()Y SJ N-type LIGBT

Improved Latch-up Characteristics

with 208-211

viii

TITLE

Table 2.1

Table 2.2

Table 3.1

Table 4.1

Table 4.2

Table 4.3

Table 4.4

Table 4.5

LIST OF TABLES

Category of LIGBTs

Specific on-resistance comparison

Final implant condition of 200V n-type superjunction LIGBT

Summary of device geometry for 200v n-type superjunction

LIGBT

Measured off-state parameters at different temperature for

superjunction LIGBT and superjunction LDMOS

Layout splits to investigate the alternate np design impacts

towards VON and latch-up voltage

Temperature coefficient of VON at different operating current

density

Comparison of temperature effect of superjunction LIGBT versus

superjunction LDMOS

xi

PAGE

24

81

94

102

liS

130

139

142

I

LIST OF FIGURES

TITLE PAGE

Figure 2.1 Overview of different types of IGBTs 8

sinkers

W n+/p to W n+/p+W p under clamped inducti ve switching circuit

ratios

different anode gate (AG) and main gate (CG) bias

Figure 2.2 Schematic cross section of NPT planar gate IGBT II

Figure 2.3 Schematic cross section of PT planar gate IGBT 12

Figure 2.4 Schematic cross section of SPT Trench IGBT 16

Figure 2.5 Schematic cross section of IEGT 18

Figure 2.6 Schematic cross section of CSTBT 19

Figure 2.7 Schematic cross section of HiGT 20

Figure 2.8 Schematic cross section of S1BT 21

Figure 2.9(a) Schematic cross section of LIGBT with p sinker 26

Figure 2.9(b) Schematic cross section of LIGBT with p type buried layer 26

Figure 2.9(c) Schematic cross section of hole divelter design 27

Figure 2.10 Schematic cross section of LIGBT with double buried layers and 28

Figure 2.11 Schematic cross section of SA-LIGBT 30

Figure 2.12 Typical IV characteristic of SA-LIGBT 31

Figure 2.13 Schematic cross section of Segmented Anode LIGBT 33

Figure 2. 14 Example of NPN Controlled LIGBT 34

Figure 2.15 Schematic cross section of SA-NPN LIGBT 34

Figure 2.16 Turn-off waveforms of SA-NPN-LIGBT for different ratios of 36

Figure 2.17 Comparison of turn-off and conduction losses for different anode 37

Figure 2. 18 Schematic cross section of GHI-LIGBT 38

Figure 2.19 IV Characteristics of GHI-LIGBT and SA-LIGBT 40

Figure 2.20 Schematic cross section of DGILET 41

Figure 2.21 Measured current-voltage characteristic of a DGILET with 44

xii

,. I

TITLE

Figure 2.22

Figure 2.23

Figure 2.24

Figure 2.25

Figure 2.26(a)

Figure 2.26(b)

Figure 2.27

Figure 2.28

Figure 2.29

Figure 2.30

Figure 2.31

Figure 2.32

Figure 2.33

Figure 2.34

Figure 2.35

Figure 2.36

Figure 2.37

Figure 2.38

Figure 2.39

Figure 2.40

Figure 2.41

PAGE

Measured turn-off waveform under clamped inductive switching 45

circuit

Schematic cross section of ILBT 46

Measured Output Characteristic of ILBT 47

Schematic cross section of LTGBT 48

Conventional LIGBT on bulk wafer 50

LIGBT on SOl wafer 51

Schematic cross section of Multi-Channel LIGBT 52

Schematic cross section of improved Multi-channel LIGBT 53

Trade-off curves of the Multi-channel LIGBTs with the 53

conventional LIGBT

Schematic cross section of LIGBT on ultra thin SOl 55

(a) VON vs drift region length for LIGBTs (b) Current density vs 55

drift region length (L) for LIGBT and LDMOS on different SOl

thickness

BV vs drift region length for LIGBT (with and without n- buffer) 56

on different SOl thickness

Current density vs drift region length for LIGBT and LDMOS on 56

different SOl thickness

Schematic cross section of LIGBT segment In hybrid 57

LIGBT I LOMOS device

Schematic cross section of Oxide Trench, Hole Bypassed Gate 59

Configuration LIGBT

Simulated potential contours upon off-state breakdown 60

Simulated electric field distribution upon off-state breakdown 61

Measured turn-off waveform at a current density of 1000Alcm2 62

Trade-off of turn-off time and VON at 700Alcm2 and IOOOA/cm2 62

Schematic cross section of Multi-channel ROP LIGBT 63

Example of multi-emitter LIGBT 65

xiii

TITLE PAGE

Figure 2.42

Figure 2.43

Figure 2.44

Figure 2.45

Figure 2.46

Figure 2.47

Figure 2.48

Figure 2.49

Figure 2.50

Figure 2.51

Figure 2.52

Figure 2.53

Figure 2.54

Figure 2.55

Figure 2.56

Figure 2.57

Figure 2.58

Figure 2.59

Measured current-voltage characteristic of Multi-emitter LIGBT 66

without HBNW layer; (a) full picture and (b) zoon in of low

voltage region

Measured current-voltage characteristic of Multi-emitter LIGBT 67

with HBNW layer

Breakdown voltage dependence on HBNW dose 68

Schematic cross section of LIGBT based on partial isolation SOl 70

technology

Potential distribution during off-state simulation at breakdown 70

point

Electron distribution during the on-state simulation 71

Schematic cross section of LIGBT on partial isolation SOl 72

Potential distribution in (a) JI LIGBT (b) SOl LIGBT (c) PSOI 73

LIGBT

Simulated current-voltage characteristic of 11, SOl and PSOI 74

LIGBTs

Simulated turn-off waveforms of 11, SOl and PSOI LIGBTs 74

Basic steps of the recrystallization process in LEGO 75

Schematic cross section of (a) conventional LIGBT and (b) 77

Super-junction LIGBT on Membrane technology

Simulated electrical potential line distribution during breakdown 77

Comparison of breakdown voltage of devices with various drift 78

lengths for SOl LIGBT and membrane

Turn-off waveform of membrane LIGBT measured with clamped 79

inductive switching circuit

Junction temperature function of power density for thick SOl and 80

thin SOl membrane LIGBT

Simulated trade-off curve for membrane LIGBT on SOl 82

Simulated trade-off curve for 9.5J.lm SOl membrane LIGBT with 83

variation of buffer doping

xiv

I

TITLE

Figure 2.60

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6

Figure 4.1

Figure 4.2

Figure 4.3

Figure 4.4

Figure 4.5

Figure 4.6(a)

Figure 4.6(b)

Figure 4.7(a)

Figure 4.7(b)

Figure 4.8

Figure 4.9

PAGE

Membrane LIGBT on Bulk CMOS technology 84

Research chart of 200V n-type superjunction LIGBT on PSOI 87

Process flow chart of 200V n-type superjunction LIGBT 90

fabrication

Example of (a) general electric field distribution (b) ideal electric 92

field distribution in drift region

Example of superjunction diode (a) n- and p- layers stacked on 93

top of each other (b) n- and p- layers arranged side by side

Doping profile at the end of process for the 200V n-type 95

superjunction LIGBT

Inductive clamped switching circuit 97

Proposed cross-section of 200V n-type superjunction LIGBT 99

Proposed top view of 200V superjunction n-type LIGBT on PSOI 100

Superjunction profile at the end of 20 process simulation 101

N buffer profile at the end of 20 process simulation 102

SEM picture of 200V n-type superjunction LIGBT 103

Electrical potential line distribution of the 200V n-type 104

superjunction LIGBT on PSOI during breakdown at

temperature = 300K

Electrical potential line distribution of the 200V n-type 105

superjunction LIGBT on SOl during breakdown at

temperature = 300K

Impact ionization rate of the 200v n-type superjunction LIGBT 105

on PSOI during breakdown at temperature = 300K

Impact ionization rate of the 200V n-type superjunction LIGBT 106

on SOl during breakdown at temperature=300K

Measured off-state plot of the final 200V n-type supeljunction 106

LIGBT on PSOI at temperature = 300K

Cross-section of initial 200V n-type superjunction LIGBT on 107

PSOI

xv

~LE PAGE

Figure 4. 1O(a) Off-state plot of the initial 200V n-type superjunction LIGBT on 108

PSOI in logarithmic scale at temperature = 300K

Figure 4. 10 b) Off-state plot of the initial 200V n-type superjunction LIGBT on 108

PSOI in logarithmic scale at temperature = 300K '

Figure 4.1 1 Electrical potential line distribution when Vanode=2V and buried 109

junction is grounded at temperature = 300K

Figure 4.12(a) Hole current density when Vanode=20V and buried junction IS 110

grounded at temperature = 300K

Figure 4.1 2(b) Zoom in of hole current density at anode region when Vanode=20V 110

and buried junction is grounded at temperature = 300K

Figure 4.13 Top view of the initial two finger design 112

Figure 4.14 Cross-section of the equivalent n-type superjunction LOMOS on 114

PSOI

Figure 4.15 Off-state plot of the 200V n-type supeljunction LIGBT versus 114

equivalent superjunction LOMOS on PSOI at different

temperature

Figure 4. 16(a) Measured transfer characteristic of 200V n-type superjunction I 17

LIGBT on PSOI at different anode voltage, temperature = 300K

in linear scale

Figure 4.16(b) Measured transfer characteristic of 200V n-type superjunction 118

LIGBT on PSOI at different anode voltage, temperature = 300K

in linear scale

Figure 4.17 Measured output characteristic of 200V n-type superjunction I 18

LIGBT on PSOI in DC at temperature = 300K

Figure 4.18 Output characteristic comparison of supeljunction LIGBT and 120

superjunction LOMOS at temperature = 300K

Figure 4.19(a) Electron current density distribution across the n layer and pLayer 121

at temperature = 300K

Figure4.19(b) Hole current density distribution across the n layer and p layer at 121

temperature = 300K

xvi

I

TITLE PAGE

Figure 4.20(a) Vertical cut-line across the superjunction at x = 4J.lm 122

silicon depth at temperature = 300K

temperature = 300K in superjunction LIGBT

temperature = 300K in superjunction LOMaS

temperature = 300K

when V Gs=5V at temperature = 300K

at temperature =300K with 250ns pulse width

temperature = 300K with Ins pulse width

at temperature = 300K with 100)1.s pulse width

at temperature = 300K with 10J.1s pulse width

at temperature = 300K with l)1.s pulse width

at temperature = 300K with 250n5 pulse width

Figure 4.20(b) Electron and hole density versus background doping against 123

Figure 4.21(a) Total current density when VGs=5V, Vanode=IOV at 124

Figure 4.21 (b) Total current density when V Gs=5V, V drain = lOY at 124

Figure 4.22(a) Cross-section of typical sal LIGBT 125

Figure 4.22(b) Equivalent circuit of typical sal LIGBT 126

Figure 4.23( a) Cross-section of second design 126

Figure4.23(b) Measured current-voltage curve at VGS =5V of second design at 127

Figure 4.24(a) Simplified equivalent circuits of superjunction LIGBT 128

Figure 4.24(b) Equivalent circuits of superjunction LIGBT 128

Figure 4.25 Trade-off parameters of latch-up voltage versus VON at 300Ncm2 131

Figure 4.26(a) Pulse output characteristic of superjunction LIGBT in Figure 4.1 134

Figure 4.26(b) Pulse output characteristic of SJ LIGBT 10 Figure 4. 1 at 134

Figure 4.27(a) Pulse output characteristic of supeljunction LIGBT in Figure 4.1 135

Figure 4.27(b) Pulse output characteristic of superjunction LIGBT in Figure 4.1 136

Figure 4.27(c) Pulse output characteristic of superjunction LIGBT in Figure 4.1 136

Figure 4.27(d) Pulse output characteristic of superjunction LIGBT in Figure 4.1 137

Figure 4.28(a) Measured IV curve at V Gs=5V at different temperature 138

xvii

TITLE PAGE

Figure 4.28(b) Zoom in of low anode voltage region of measured IV curve at 139

V Gs=5Vat different temperature

Figure 4.29 Flow chart showing the temperature coefficient behavior of IGBT 141

Figure 4.30( a) Wafer level test inductive switching waveform, Ianode and V anode 143

versus time at temperature = 300K

versus time at temperature = 300K

versus time at temperature = 300K

versus time at temperature = 300K

Figure 4.30(b) Wafer level test inductive switchjng waveform, Ianode and V GS 144

Figure 4.31(a) Wafer level test inductive switching waveform, LJrain and V drain 146

Figure 4.31 (b) Wafer level test inductive switching waveform, , LJrain and V GS 146

Figure 4.30 Simulated switching waveform at temperature = 300K 147

Figure 4.31 (a) Simulated changes of minority current density during turn off, 148

when the device is still on

IOns after the turn off

20ns after the turn off

40ns after the turn off

70ns after the turn off

80ns after the turn off

LIGBT at different temperature

Figure 4.31 (b) Simulated changes of minority current density during turn off, 148

Figure 4.31(c) Simulated changes of minority current density during turn off, 149

Figure 4.31 (d) Simulated changes of minority current density during turn off, 149

Figure 4.3 1 (e) Simulated changes of minority current density during turn off, 150

Figure 4.3 1(f) Simulated changes of minority current density during turn off, 150

Figure 4.32 Measured wafer level switch-off waveform for superjunction 151

xviii

LIST OF ABBREVIATIONS

A

AG

a

BJT

BY

BOX

CAGR

CFP

CG

CMOS

COMFET

CSTBT

DGILET

DI

DMOS

OMS

OTI

E

EFP

EMI

FS

10-35 6 71.8 X cm y-

Anode Gate

Width of n+ and p+ at Source

Bipolar Junction Transistor

Breakdown yoltage

Buried Oxide

Compound Annual Growth Rates

Collector Side Field Plate

Main Gate

Complementary Metal-Oxide-Semiconductor

Conductivity Modulated Field Effect Transistor

Carrier Stored Trench Gate Bipolar Transistor

Dual-Gate Inversion Layer Emitter Transistor

Dielectric Isolation

Double-diffused Metal-Oxide-Semiconductor Field Effect

Transistor

Dummy Metal Short

Deep Trench Isolation

Electric Field

Emitter Side Field Plate

Electromagnetic Interference

Field Stop

XIX

GHI-LIGBT Double Gate Structure, Gradual Hole Injection Dual-Gate

GOI

HDP

HiGT

HTRB

HV

IC

IEGT

IGBT

IGT

ILBT

lLI

IOFF

lj1eak

JI

W D

LDMOS

Lunodc

~rih

Lgatc

LIGBT

Gate Oxide Integrity

High Density Plasma

High-Conductivity IGBT

High Temperature Reverse-biased

High Voltage

Integrated Circuit

Injection Enhanced Insulated Gate Bipolar Transistor

Insulated Gate Bipolar Transistor

Insulated Gate Transistor

Inversion Layer Bipolar Transistor

Inversion Layer Injection

Leakage Current

Peak Current

Junction Isolation

Low Doped Drift

Lateral Diffused Metal-0xide-Semiconductor Field Effect

Transistor

Accumulation Length

Anode Length

Drift Length

Gate Length

N Buffer Length

xx

LLVP

LSTI

Lterm

LIGBT

LEGO

LPT

LTGBT

LV

MOS

MPE

MV

NBUR

Nd

NOR

NPT

ONO

PIC

Pi N

PDP

PSOI

PT

RESURF

RBSOA

Gap between LV P Well to Poly Edge

Shallow Trench Isolation Length

Space between Anode and OTI

Lateral Insulated Gate Bipolar Transistor

Lateral Epitaxial Growth Over Oxide

Light Punch Through

Lateral Trench-Gate Bipolar Transistor

Low Voltage

Metal-Ox ide-Semiconductor

Mask Proximity Effect

Medium Voltage

N-type Buried Layer

Doping Concentration

Negative Differential Resistance

Non Punch Through

Oxide-nitride-oxide

Power Integrated Circuit

P-type Semiconductor I Intrinsic Semiconductor IN-type

Semiconductor

Plasma Display Panel

Partial SOl

Punch Through

Reduced Surface Field

Reverse-biased SOA

XXI

RC

RDP

RIE

RoN

SEM

VCESAT

SA-LIGBT

SCSOA

SA-NPN LlGBT

S1

SJBT

SOA

SOl

SPT

STI

TLP

VON

JI

RIE

RON

R. o

SJ

SOA

SOl

Reverse Conducting

Retrograded Doping Profile

Reactive Ionic Etch

Specific On Resistance

Scanning Electron Microscope

Saturation Voltage

Shorted Anode LIGBT

Short Circuit SOA

Segmented Anode NPN Controlled LIGBT

Super Junction

Super Junction Bipolar Transistor

Safe Operating Area

Silicon On Insulator

Soft Punch Through

Shallow Trench Isolation

Transmission Line Pulses

Forward Voltage Drop

J unction Isolation

Reactive Ion Etching

Specific On Resistance

Source Drain Sheet Resistance

Super Junction

Safe Operating Area

Silicon-On-Insulator

XXll

ST}

TCAD

x

ID

2D

Vanodc

w

x

a

Shallow Trench Isolation

Technology Computer Aided Design

Superjunction Layer Thickness

Drain to Source Voltage

Gate to Source Voltage

Threshold Voltage

Overlapping Distance of DTI Field Plate with Drift

One-dimensional

Two-dimensional

Anode Voltage

Depletion Region Edge for One-sided Junction

Dimension Parallel with the Electric Field Distribution

Ionization Coefficients

xxiii

CHAPTER 1 INTRODUCTION

1.1 Overview

The power semiconductor market has grown steadily in past two decades from $2.7

billion in 1992 and projected to reach $16.3 billion annual sales volume in the year 2015 due to

rapid proliferation of power electronics [I]. Application of power electronics has been extended

in many fields such as telecommunication, automotive, consumer, transportation, utilities,

industrial, new renewable energy system and energy conversion. This motivates the development

of silicon based power switches with ever decreasing static and dynamic losses. Among the

power transistor products, integrated IGBTs becomes one of the key devices which are potential

to serve as high voltage and high current switches today. The five-year forecast on IC Insight

shows that the sales of integrated IGBTs are expected to increase by a CAGR (compound annual

growth rate ·) of7 percent to $3.2 billion in the year 2015 [I].

Since 1985, development of the IGBT had started with integration mode. The integrated

IGBTs also known as lateral IGBT (LIGBT) as the anode has been moved from back-side of

wafer (ali in discrete IGBT) to the surface of the silicon. The LIGBT is a promising device for

Power Integrated Circuit (pIC),s due to its combination of high input impedance of the MOS gate

and the conductivity modulation effect of the drift region. Similar in discrete IGBT, the

conductivity modulation effect a'llows LIGBT to have low forward voltage drop (VON) but high

witching loss due to the removal of electron-hole plasma retaining in the un-depleted drift region.

However, irradiation techniques used in discrete IGBTs which reduces the carrier lifetime is not

itable as it adversely affects the CMOS (complementary Metal-Oxide-Semiconductor) devices

in PIC [2 - 3]. To achieve a well trade-off between VON and turn-off losses, various ideas and

interaction between

behave

"

approaches had been found in literatures [4]. However, most of them still suffer from certain

weaknesses and optimizations are currently underway.

1.2 Statements of the Problems

The reported LIGBTs are fabricated on bulk wafer, SOl wafer and )ater on membrane

[4,6]. Fabrication of LIGBTs on bulk wafer is the focus in early years due to the common wafer

source, cheaper wafer price and more mature bulk technology. For the conventional LIGBTs that

fabricated on bulk wafer, the normally encountered problems are undesired static and dynamic

devices, high switching loss due to deep injection of carriers from the

bstrate and lower VON that resulted in the efforts to compensate the high switching loss. To

address the common problems found in bulk technology, development focus of LIGBTs is shifted

ro SOl technology. SOl is well known in offering superior isolation with lower leakage current.

The SOl LIGBTs have the potential for lower switching loss compared to bulk LIGBTs as deep

injection of carriers is no longer exist (not applied to thick SOl). In thick SOl, the device would

similar like those fabricated on bulk wafer. However, there are also some common

weaknesses found in SOl devices, such as severe self heating, reduced RESURF [5] effect which

to lower BV and possible parasitic back-gate and side-gate effect. The later approach known

PSOI (Partial SOl) is introduced which has the same advantages as SOl while still allows

~r BV and more effective heat dissipation. The membrane technology is the latest technology

ng used as substrate for LIGBT which has ideal BV, low VON and low switching loss but

suffered from even more severe self-heating and complex manufacturing process.

2