Design of a balanced X-band low-noise amplifier using a GMIC …650307/FULLTEXT01.pdf ·...

Department of Science and Technology Institutionen för teknik och naturvetenskap Linköpings Universitet Linköpings Universitet SE-601 74 Norrköping, Sweden 601 74 Norrköping

ExamensarbeteLITH-ITN-ED-EX--06/007--SE

Design of a balanced X-bandlow-noise amplifier using a

GMIC processRikard Eliasson

2006-02-24

LITH-ITN-ED-EX--06/007--SE

Design of a balanced X-bandlow-noise amplifier using a

GMIC processExamensarbete utfört i Elektronikdesign

vid Linköpings Tekniska Högskola, CampusNorrköping

Rikard Eliasson

Handledare Anders WallHandledare Anders SundbergExaminator Shaofang Gong

Norrköping 2006-02-24

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Examensarbete B-uppsats C-uppsats D-uppsats

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Institutionen för teknik och naturvetenskap

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LITH-ITN-ED-EX--06/007--SE

Design of a balanced X-band low-noise amplifier using a GMIC process

Rikard Eliasson

This report is the result of a master thesis work done at SAAB Bofors Dynamics AB between September2005 and January 2006. The purpose of the work was to design a balanced low-noise amplifier coveringthe X-band (8 12 GHz) using the GMIC (Glass Microwave Integrated Circuit) process provided byM/A-COM, Tyco Electronics UK Limited.

This thesis work has resulted in an approved and functional balanced low-noise amplifier design. Themanufacturer, M/A-COM, reviewed the design for manufacturability only and takes no responsibility forthe electrical performance. The amplifier has been designed to have a flat frequency response and lowreflections on the input and output. Of course, the noise performance has also been taken intoconsideration during the design process. This thesis report covers the whole design flow in achronological order.

The layout work and most of the simulations were accomplished by using the design tool MicrowaveOffice from Applied Wave Research. For complex structures such as Lange couplers and spiralinductors, more accurate simulation models were obtained by using HFSS (High Frequency StructureSimulator) from Ansoft.

Glass Microwave Integrated Circuit, X-band, Low-noise amplifier, RF, Microwave Office, HFSS, 3dBhybrid, Balanced amplifier, Lange coupler, SAAB Bofors Dynamics

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© Rikard Eliasson

I

Abstract This report is the result of a master thesis work done at SAAB Bofors Dynamics AB between September 2005 and January 2006. The purpose of the work was to design a balanced low-noise amplifier covering the X-band (8 – 12 GHz) using the GMIC (Glass Microwave Integrated Circuit) process provided by M/A-COM, Tyco Electronics UK Limited. This thesis work has resulted in an approved and functional balanced low-noise amplifier design. The manufacturer, M/A-COM, reviewed the design for manufacturability only and takes no responsibility for the electrical performance. The amplifier has been designed to have a flat frequency response and low reflections on the input and output. Of course, the noise performance has also been taken into consideration during the design process. This thesis report covers the whole design flow in a chronological order. The layout work and most of the simulations were accomplished by using the design tool Microwave Office from Applied Wave Research. For complex structures such as Lange couplers and spiral inductors, more accurate simulation models were obtained by using HFSS (High Frequency Structure Simulator) from Ansoft.

II

Sammanfattning Den här rapporten är resultatet utav ett examensarbete genomfört på SAAB Bofors Dynamics AB mellan september 2005 och januari 2006. Det övergripande syftet med examensarbetet har varit att konstruera en balanserad lågbrusförstärkare på X-bandet (8 – 12 GHz) med GMIC-processen som tillhandahålls av M/A-COM, Tyco Electronics UK Limited. Det här examensarbetet har resulterat i en godkänd och fungerande balanserad lågbrusförstärkarkonstruktion. Tillverkaren, M/A-COM, har enbart granskat att konstruktionen går att tillverka och avsäger sig allt ansvar för elektrisk prestanda. Förstärkaren har konstruerats för att ha ett platt frekvenssvar samt låga reflektioner på in- och utgången. Brusegenskaperna har givetvis beaktats under hela konstruktionsprocessen. Den här rapporten följer hela konstruktionsprocessen i en kronologisk ordning. All skapad layout och större delen utav simuleringarna har genomförts i konstruktionsverktyget Microwave Office, som tillhandahålls av Applied Wave Research. Komplexa strukturer, såsom Langekopplare och spiralinduktanser, har simulerats i HFSS från Ansoft för att erhålla mer exakta simuleringsmodeller.

III

Acknowledgements This thesis work has been carried out at SAAB Bofors Dynamics AB in Linköping as a part of a Master of Science degree in Electronics Design Engineering at Linköping University. I would like to thank all persons who have helped and encouraged me during the work. Especially, I would like to thank following persons:

• My supervisors Anders Wall and Anders Sundberg at SAAB Bofors Dynamics AB, for all support and assistance during the thesis work.

• Mats Eriksson at MTT AB, for providing the Microwave Office license.

• Robert Smith at M/A-COM Ltd, for validating the manufacturability of the

created amplifier layout.

• The staff at Excelics Semiconductors Inc., for contributing the s-parameter files.

• Björn Peterson at SAAB Bofors Dynamics AB, for all help with the simulation software HFSS.

• My examiner Shaofang Gong at the Department of Science and Technology,

Linköping University, for valuable comments on the report.

• My opponent Anna-Maria Lann for her valuable comments and feedback on my thesis report.

Rikard Eliasson

February 2006

IV

Contents

Terminology IX

1 Introduction 1 1.1 Background .......................................................................................................... 1 1.2 Task...................................................................................................................... 1 1.3 Purpose................................................................................................................. 2 1.4 Method ................................................................................................................. 2 1.5 Delimitations........................................................................................................ 2 1.6 Outline.................................................................................................................. 2

2 Design specification 5

3 Theory 7 3.1 General microwave theory................................................................................... 7

3.1.1 Transmission-line concept ...................................................................... 7 3.1.2 Terminated lossless transmission line................................................... 10 3.1.3 Microstrip transmission line ................................................................. 12

3.2 Scattering parameters......................................................................................... 14 3.3 Microwave transistor amplifiers ........................................................................ 15

3.3.1 DC bias.................................................................................................. 15 3.3.2 Stability................................................................................................. 17 3.3.3 Gain....................................................................................................... 18 3.3.4 Noise ..................................................................................................... 20 3.3.5 1-dB compression point ........................................................................ 20 3.3.6 Third-order intercept point.................................................................... 21

3.4 Broadband amplifiers......................................................................................... 22 3.4.1 Frequency compensated networks ........................................................ 23 3.4.2 Balanced amplifiers .............................................................................. 24

4 The GMIC process 27 4.1 The GMIC substrate........................................................................................... 27

4.1.1 Conductor traces ................................................................................... 27 4.1.2 Airbridge interconnections.................................................................... 28 4.1.3 Pedestals................................................................................................ 28

4.2 Passive elements ................................................................................................ 29 4.2.1 MIM Capacitor...................................................................................... 29 4.2.2 Thin-film resistor .................................................................................. 31 4.2.3 Spiral inductor....................................................................................... 33

4.3 Lange coupler..................................................................................................... 36

5 Design process 39 5.1 The transistor ..................................................................................................... 39

V

5.1.1 Small-signal model ............................................................................... 39 5.1.2 Large-signal model ............................................................................... 40 5.1.3 Footprint................................................................................................ 40

5.2 DC bias............................................................................................................... 41 5.3 Stability.............................................................................................................. 49 5.4 Impedance matching .......................................................................................... 53

5.4.1 Input matching network ........................................................................ 53 5.4.2 Output matching network ..................................................................... 55

5.5 The balanced amplifier ...................................................................................... 59

6 Results 63 6.1 Simulations ........................................................................................................ 63

6.1.1 Gain....................................................................................................... 63 6.1.2 Noise ..................................................................................................... 64 6.1.3 Stability................................................................................................. 64 6.1.4 Reflections and reverse transmission.................................................... 65 6.1.5 1-dB compression point ........................................................................ 66 6.1.6 Third-order output intercept point ........................................................ 67

6.2 Temperature behavior ........................................................................................ 67 6.3 Yield analysis..................................................................................................... 68

6.3.1 Table ..................................................................................................... 68 6.3.2 Graphs ................................................................................................... 70

7 Discussions 75

8 Conclusions 77

9 Further work 79

References 81

A Microwave Office schematics 83

B Stress sheets 87

C Targets/simulations 89

VI

List of figures Figure 3.1: Lumped element model of a transmission line................................................. 8 Figure 3.2: Terminated transmission line ......................................................................... 10 Figure 3.3: Microstrip line ................................................................................................ 12 Figure 3.4: Incident and reflected waves in a two-port network ...................................... 14 Figure 3.5: Operating points ............................................................................................. 16 Figure 3.6: Unipolar biasing network for FET ................................................................. 17 Figure 3.7: Transistor with input and output matching networks..................................... 18 Figure 3.8: Definition of the 1-dB compression point...................................................... 21 Figure 3.9: Definition of the third-order intercept point................................................... 22 Figure 3.10: Frequency behavior of |S21|, |S12| and |S12S21|................................................ 23 Figure 3.11: Increase and decrease of the transducer gain ............................................... 24 Figure 3.12: Balanced amplifier using 3-dB 90˚ hybrids ................................................. 25 Figure 3.13: Lange coupler with port 4 terminated to 50 ............................................. 26 Figure 4.1: Cross-sectional view of an airbridge .............................................................. 28 Figure 4.2: MWO layout of an Airbridge ......................................................................... 28 Figure 4.3: MWO layout of a pedestal.............................................................................. 29 Figure 4.4: MWO layout of a MIM capacitor................................................................... 30 Figure 4.5: 3-D HFSS model of a MIM capacitor ............................................................ 31 Figure 4.6: Comparison between capacitor models.......................................................... 31 Figure 4.7: MWO layout of a thin-film resistor................................................................ 32 Figure 4.8: 3-D HFSS model of a thin-film resistor ......................................................... 32 Figure 4.9: Comparison between resistor models............................................................. 33 Figure 4.10: MWO layout of a spiral inductor ................................................................. 34 Figure 4.11: 3-D HFSS model of a spiral inductor........................................................... 34 Figure 4.12: Comparison between inductor models ......................................................... 35 Figure 4.13: Input impedance of the spiral inductor......................................................... 35 Figure 4.14: MWO layout of a Lange coupler.................................................................. 36 Figure 4.15: S21 and S31 for the Lange coupler ................................................................. 36 Figure 4.16: Phase difference between ports 2 and 3 ....................................................... 37 Figure 5.1: Transistor footprint......................................................................................... 41 Figure 5.2: Transistor footprint with bond wires, capacitors and bond pads.................... 41 Figure 5.3: Biasing network.............................................................................................. 43 Figure 5.4: IV-curve.......................................................................................................... 43 Figure 5.5: Resistor network............................................................................................. 44 Figure 5.6: DC supply network......................................................................................... 45 Figure 5.7: Layout of DC supply network ........................................................................ 46 Figure 5.8: Isolation .......................................................................................................... 47 Figure 5.9: Complete biasing network.............................................................................. 48 Figure 5.10: Currents and voltages through the transistors, A: upper and B: lower......... 48 Figure 5.11: Stability factors of the unstable amplifier .................................................... 49 Figure 5.12: Noise figure of the unstable amplifier .......................................................... 50 Figure 5.13: Stabilization resistors ................................................................................... 50

VII

Figure 5.14: Stability factors of the stable amplifier ........................................................ 51 Figure 5.15: Noise figure of the stable amplifier .............................................................. 51 Figure 5.16: Stabilized amplifier branches ....................................................................... 52 Figure 5.17: S21 of unmatched amplifier branch............................................................... 53 Figure 5.18: Input matching network................................................................................ 54 Figure 5.19: Field radiation, A: un-mitered, B: optimal mitered...................................... 54 Figure 5.20: Comparison between HFSS and MWO models ........................................... 55 Figure 5.21: Output matching network............................................................................. 56 Figure 5.22: Comparison between HFSS and MWO models ........................................... 56 Figure 5.23: Matched amplifier branches ......................................................................... 57 Figure 5.24: S21 of matched amplifier branch................................................................... 58 Figure 5.25: Noise figure of matched amplifier branch.................................................... 58 Figure 5.26: S11 and S22 of matched amplifier branch ...................................................... 59 Figure 5.27: Circuit schematic of the balanced amplifier................................................. 59 Figure 5.28: The balanced amplifier................................................................................. 61 Figure 6.1: Gain ................................................................................................................ 63 Figure 6.2: Noise figure .................................................................................................... 64 Figure 6.3: Stability factors............................................................................................... 65 Figure 6.4: S11, S12 and S22 ................................................................................................ 65 Figure 6.5: S11 and S22 represented in Smith chart............................................................ 66 Figure 6.6: 1-dB compression point and power gain at f = 12 GHz ................................. 66 Figure 6.7: Third-order output intercept point at f = 12 GHz ........................................... 67 Figure 6.8: S21, five linear models, 100 yield runs............................................................ 70 Figure 6.9: Stability factors, five linear models, 100 yield runs....................................... 71 Figure 6.10: Stability factors, one nonlinear model, 100 yield runs................................. 71 Figure 6.11: S12, Reverse isolation, five linear models, 100 yield runs ............................ 72 Figure 6.12: S11, five linear models, 100 yield runs.......................................................... 72 Figure 6.13: S22, five linear models, 100 yield runs.......................................................... 73 Figure 7.1: Input impedance of spiral inductors ............................................................... 76 Figure 9.1: Further work ................................................................................................... 79 Figure A.1: Resistor network............................................................................................ 83 Figure A.2: DC supply...................................................................................................... 84 Figure A.3: Grounded tune stub........................................................................................ 85 Figure A.4: Matched amplifier branch.............................................................................. 85 Figure A.5: Balanced amplifier stage ............................................................................... 86

VIII

List of tables Table 2.1: Design specification........................................................................................... 5 Table 4.1: Current ratings for conductors ......................................................................... 27 Table 5.1: Maximum ratings............................................................................................. 39 Table 5.2: Resistance values ............................................................................................. 44 Table 5.3: Stabilization resistors....................................................................................... 52 Table 6.1: 1-dB compression points ................................................................................. 67 Table 6.2: Third-order output intercept points.................................................................. 67 Table 6.3: Gain variations with respect to the temperature .............................................. 68 Table 6.4: Yield analysis................................................................................................... 68 Table B.1: Active component stress sheet ........................................................................ 87 Table B.2: Capacitor stress sheet ...................................................................................... 87 Table B.3: Resistor stress sheet ........................................................................................ 88 Table C.1: Targets/simulations ......................................................................................... 89

IX

Terminology Abbreviation Explanation 3-D Three Dimensional ABRIDGE Airbridge dBm Power level in decibel (dB) relative to 1 mW DC Direct Current CAD Computer-Aided Design FEM Finite Element Method FET Field Effect Transistor GaAs Gallium Arsenide GMIC Glass Microwave Integrated Circuit HEMT High Electron Mobility Transistor HFSS High Frequency Structure Simulator Ids Drain current Idss Saturated drain current IMN Input Matching Network LNA Low-Noise Amplifier MIM Metal-Insulator-Metal MMIC Monolithic Microwave Integrated Circuit MRINDSBR Rectangular Microstrip Inductor with Strip Bridge MWO Microwave Office NF Noise Figure OIP3 Third-order Output Intercept Point OMN Output Matching Network Pout, 1 dB 1-dB compression point RF Radio Frequency RFC Radio-Frequency Choke SWR Standing Wave Ratio TFCM Thin-Film Capacitor for MMIC TFR Thin-Film Resistor Vds Drain-source Voltage Vgs Gate-source Voltage

X

1

1 Introduction This chapter serves as an introduction to this master thesis work. It starts with describing the background to why this project was initiated and is followed by the task, purpose, method, delimitations and report outline.

1.1 Background A balanced low-noise amplifier that covers the entire X-band (8 – 12 GHz) is a strategically important microwave component in a future project at SAAB Bofors Dynamics AB. The wanted balanced low-noise amplifier is needed in an X-band radar application. X-band radar systems are of great interest at SAAB Bofors Dynamics AB, since the short wavelengths make possible high-resolution radars for target identification and target detection. Before the summer 2005, all GMIC design work at SAAB Bofors Dynamics was accomplished by manually implemented layouts. An adaptation of the GMIC process provided by M/A-COM, Tyco Electronics UK Limited to the design tool Microwave Office was needed. The author of this thesis report adapted parts of the GMIC process to Microwave Office during the summer 2005. Dynamic layouts of GMIC elements were written in the programming language C++ and linked together with suitable simulation models in Microwave Office. To validate the adapted GMIC process to Microwave Office by designing the wanted balanced low-noise amplifier, this thesis work was initiated.

1.2 Task The task of this master degree project was to design a balanced low-noise amplifier covering the frequency range 8 – 12 GHz using the GMIC process provided by M/A-COM, Tyco Electronics UK Limited. The thesis work involved component selection and layout work. It was also required that the design should be optimized with respect to temperature and parameter variations, i.e., a yield analysis was performed. The thesis work was finished by submitting the amplifier layout to the manufacturer. The manufacturer M/A-COM reviewed the layout for manufacturability only and takes no responsibility for the electrical performance.

Section 1.3 Purpose Chapter 1 Introduction

2

1.3 Purpose The main objective for the thesis work was to accomplish an approved balanced low-noise amplifier layout and thus strengthen SAAB Bofors Dynamics AB’s design experience and expand the existing component library. Another important objective was to validate the adapted GMIC process to Microwave Office by submitting the amplifier layout to the manufacturer, which is equipped with a design rule violation checker.

1.4 Method The theoretical ground of the required knowledge was obtained by reading selected chapters in books and by useful discussions with the supervisors at SAAB Bofors Dynamics AB. The performed simulations were accomplished with the design tools Microwave Office from Applied Wave Research and HFSS (High Frequency Structure Simulator) from Ansoft. HFSS was used to obtain accurate simulation models for complex structures such as Lange couplers and spiral inductors. All layout work has been done by the adapted GMIC process to Microwave Office. The final balanced amplifier layout was submitted to M/A-COM and will be realized as hardware in a future project at SAAB Bofors Dynamics AB.

1.5 Delimitations Since the s-parameters for the selected transistor were measured on an Al2O3 carrier, the behavior may vary when a glass substrate is used. This effect has not been covered in this thesis work.

1.6 Outline The report is organized in the following chapters:

• Chapter 2 contains the design specification. All specified parameter values are given in this chapter.

• Chapter 3 covers most of the theory used in this thesis work. It also contains an

introduction to general RF and microwave theory.

• Chapter 4 describes the GMIC process. Passive elements, such as MIM capacitors, spiral inductors and thin-film resistors, are described in this chapter.

• Chapter 5 covers the entire design process from component selection to the final

balanced amplifier layout.

Section 1.6 Outline Chapter 1 Introduction

3

• Chapter 6 contains the simulated results for the balanced amplifier. It also contains temperature behavior and yield analysis.

• Chapter 7 contains the discussions regarding the results obtained by this project.

• Chapter 8 contains the conclusions drawn by this master thesis work.

• Chapter 9 gives suggestions on further work in this area.

4

5

2 Design specification All specified requirements of the balanced low-noise amplifier are given in Table 2.1.

Table 2.1: Design specification

Parameter Desired value Comments Process technology

GMIC M/A-COM

Supply voltage +4 V Unipolar supply voltage

Current consumption

< 50 mA

Frequency range 8 – 12 GHz The X-band

Gain variation within frequency range ±1 dB

S11 < -15 dB Input reflection

S21 > 8 dB Forward transmission

S12 < -20 dB Reverse transmission

S22 < -15 dB Output reflection

NF < 3 dB Noise figure

Pout, 1 dB > 5 dBm 1-dB compression point

OIP3 > 13 dBm Third-order output intercept point

Temperature range -55 – 95 ˚C

Gain variation within temperature range < 2 dB

Mechanical length 9 mm

Chapter 2 Design specification

6

K B1

> 1 > 0

Requirement for unconditional stability

Other requirements:

• The design should be able to handle a 20-dBm signal applied on the input within the frequency range 7 -13 GHz.

• The amplifier should be optimized with respect to temperature and parameter

variations.

• The two amplifier branches should be biased from the same DC supply.

7

3 Theory This chapter covers most of the theory used in this thesis report. It is assumed that the reader has a basic knowledge in electrical engineering. For further knowledge, see the books listed in references.

3.1 General microwave theory In conventional low-frequency electronics, voltage and current follows Kirchhoff’s equations and are spatially uniform in a conductor. At higher frequencies, Kirchhoff’s voltage and current laws do not longer apply. When the wavelength of the signal becomes small, current and voltage will propagate as electromagnetic waves in the conductor. [ 1], [ 2]

3.1.1 Transmission-line concept In RF and microwave engineering, the three most commonly used transmission lines are two-wire transmission line, coaxial transmission line and microstrip transmission line. This section focuses mainly on the microstrip transmission line, even though most of the presented equations are valid for all kinds of transmission lines. [ 2] Since magnitude and phase vary along the transmission line, Kirchhoff’s laws cannot be applied as an analytical method on a macroscopic level. This problem can be circumvented if the length of the transmission line is divided into infinitesimally small segments, which follow Kirchhoff’s laws on a microscopic level. The segments are still large enough to contain characteristics such as loss, as well as inductive and capacitive effects. [ 1], [ 2]

Section 3.1 General microwave theory Chapter 3 Theory

8

Figure 3.1: Lumped element model of a transmission line

An electrical model for a transmission line is shown in Figure 3.1 [ 1]. The length of the transmission line is divided into many identical segments with length z. Each segment is modeled by a resistance R per unit length (R in /m), an inductance L per unit length (L in H/m), a capacitance C per unit length (C in F/m), and a conductance G per unit length (G in S/m). Applying Kirchhoff’s voltage and current laws to the model in Figure 3.1 gives:

( ) ( ) ( ) ( )t

tzizLtzziRtzzvtzv

∂∂∆+∆=∆+− ,

,,, ( 3.1)

( ) ( ) ( ) ( )t

tzzvzCtzzzvGtzzitzi

∂∆+∂∆+∆+∆=∆+− ,

,,, ( 3.2)

Dividing by z, the following equations are obtained:

( ) ( ) ( ) ( )t

tziLtzRi

ztzvtzzv

∂∂−−=

∆−∆+ ,

,,,

( 3.3)

( ) ( ) ( ) ( )t

tzzvCtzzGv

ztzitzzi

∂∆+∂−∆+−=

∆−∆+ ,

,,,

( 3.4)

Taking the limits as 0→∆z results in:

( ) ( ) ( )t

tziLtzRi

ztzv

∂∂−−=

∂∂ ,

,,

( 3.5)

( ) ( ) ( )t

tzvCtzGv

ztzi

∂∂−−=

∂∂ ,

,,

( 3.6)

[ 1], [ 2]


9

The partial differential equations (3.5) and (3.6) describe the voltages and currents along the transmission lines. With sinusoidal steady-state condition only propagation in z-direction can be observed, the equations can therefore be simplified to:

( ) ( ) ( )zILjRdz

zdV ω+−= ( 3.7)

( ) ( ) ( )zVCjGdz

zdI ω+−= ( 3.8)

Solving equations (3.7) and (3.8), gives the standard second-order differential equation:

( ) ( ) 022

2

=− zVdz

zVd γ ( 3.9)

where the complex propagation constant is given by:

( )( )CjGLjRj ωωβαγ ++=+= ( 3.10)

The attenuation constant is given in nepers per meter and the propagation constant in radians per meter. The general solution of equation (3.9) is:

( ) zz eVeVzV γγ +−−+ += ( 3.11)

From equation (3.7) it follows that the current can be expressed in the form:

zzzz

eIeIZeV

ZeV

zI γγγγ

−−++−−+

+=−=00

)( ( 3.12)

where the complex characteristic impedance Z0 of the transmission line is given by:

CjGLjR

Zωω

++=0 ( 3.13)

[ 1], [ 2] Equations (3.11) and (3.12) represent the voltage and current along the transmission line as a pair of waves traveling in opposite directions, with phase velocity vp = / and


10

decreasing in amplitude according to e-z or ez. The wave e-z = e-ze-jz is called the incident wave and the wave ez = ezejz is called the reflected wave. [ 1], [ 2]

3.1.2 Terminated lossless transmission line At high frequencies, the conductive and resistive terms in (3.13) become insignificant compared to the frequency dependent inductive and capacitive terms and can therefore be neglected. The equation for the characteristic impedance when R = G = 0 (a lossless transmission line) is:

CL

Z =0 ( 3.14)

When the transmission line is lossless, the propagation constant is purely complex and can be related to the wavelength as:

λπωβγ 2

jLCjj === ( 3.15)

[ 1], [ 2]

Figure 3.2: Terminated transmission line

A finite lossless transmission line of length l connected to a load impedance of ZL is shown in Figure 3.2 [ 2]. If an incident wave of the form V+e-z is generated at z = -l, the wave will propagate in the positive z-direction. When the incident wave hits the load impedance ZL Z0 located at z = 0, some part of the wave will reflects back in the negative z-direction. The reflected wave has the form V-ez and the ratio between incident wave and reflected wave at z = 0 is known as the reflection coefficient given by:

+

−

=ΓVV

0 ( 3.16)

[ 1], [ 2]


11

Equations (3.11) and (3.12) for the voltage and the current in the transmission line can be re-expressed in terms of the reflection coefficient as:

( )zz eeVzV γγ0)( Γ+= −+ ( 3.17)

( ) ( )zzzz eeIeeZV

zI γγγγ00

0

)( Γ−=Γ−= −+−+

( 3.18)

If (3.17) is divided by (3.18), an impedance function of space is given as:

( ) ( )( ) zz

zz

eeee

ZzIzV

zZ γγ

γγ

0

00 Γ−

Γ+== −

−

( 3.19)

At location z = 0, the exponential terms in (3.19) cancels and the impedance becomes the load impedance. The impedance function of space at z = 0 becomes:

( )0

00 1

10

Γ−Γ+

== ZZZ L ( 3.20)

Solving (3.20) for the reflection coefficient 0 gives:

0

00 ZZ

ZZ

L

L

+−

=Γ ( 3.21)

[ 1], [ 2] An infinite load impedance, i.e., an open line, results in 0 = 1. It means that the reflected voltage wave returns with the same polarity as the incident voltage wave. For a short circuit (ZL = 0) the reflection coefficient becomes 0 = -1 and the reflected voltage wave returns with opposite polarity as the incident voltage wave. A load impedance equal to the characteristic impedance results in 0 = 0. When this occurs, the impedances are matched and the entire incident voltage wave is absorbed by the load and there is no reflected voltage wave. To quantify the degree of mismatch, the standing wave ratio is given as:

0

0

1

1

Γ−Γ+

=SWR ( 3.22)

[ 1], [ 2]


12

In microwave and RF applications, it is important to know how a load impedance is transformed along a transmission line. The input impedance at a distance d of a lossless transmission line terminated to ZL is given by the equation:

( ) ( )( )djZZ

djZZZdZ

L

oLin β

βtantan

00 +

+= ( 3.23)

[ 1], [ 2] Using equation (3.23) it is obvious to see that a transmission line with the length of a quarter wavelength (/4) terminated to a load represented by a short circuit results in an infinite input impedance, hence ( ) 2iftan πββ →∞→ dd . With equation (3.23) it is possible to design impedances by using transmission lines. Impedances designed with transmission lines are known as distributed components.[ 1], [ 2]

3.1.3 Microstrip transmission line A microstrip transmission line is a conductor of thickness t and width w at a distance h from a ground plane. The distance between the conductor and the ground plane is defined by a substrate height h with the dielectric constant r. Figure 3.3 shows a cross-sectional view of a microstrip line. [ 2]

Figure 3.3: Microstrip line

The ground plane below the conductor helps prevent excessive field leakage and thus reduces radiation loss. On one hand, the field leakage and cross coupling between adjacent conductor traces depends on the dielectric constant of the substrate. It is therefore good to use a substrate with as high dielectric constant as possible. On the other hand, substrates with a low dielectric constant offer a broad range of characteristic impedances when thin substrates are used. To avoid cross coupling, there is a rule of thumb saying that the spacing between adjacent microstrip lines should be twice the substrate thickness. [ 2] If the conductor thickness is negligible compared to the substrate height, the characteristic impedance of a microstrip line is only dependent of the conductor width,


13

the substrate height and the dielectric constant. For narrow lines, w/h<1, the characteristic impedance is given by:

+=h

wwhZ

Zeff

f

48ln

20 επ

( 3.24)

where Ω== 8.37600 εµfZ is the wave impedance in free space, and eff is the effective dielectric constant given by:

−++

−+

+=

2

104.0121

12

12

1hw

wh

rreff

εεε ( 3.25)

For wide lines, w/h>1, the line impedance is given by:

+++=

444.1ln32

393.10

hw

hw

ZZ

eff

f

ε ( 3.26)

with

wh

rreff

121

12

12

1

+⋅

−+

+=

εεε ( 3.27)

With knowledge of the effective dielectric constant it is possible to calculate the wavelength of the strip line by the expression:

eff

p

f

cf

v

ελ == ( 3.28)

where vp is the phase velocity, c is the speed of light and f is the operating frequency.[ 2]

Section 3.2 Scattering parameters Chapter 3 Theory

14

3.2 Scattering parameters Scattering parameters, or s-parameters, are normalized power wave descriptors that define input-output relations of a network in terms of incident and reflected power waves. Figure 3.4 [ 2] shows a two-port network with normalized incident and reflected power waves defined as follows:

( )nnn IZVZ

a 0

02

1 += ( 3.29)

( )nnn IZVZ

b 0

02

1 −= ( 3.30)

[ 1], [ 2] where the index n refers either to port 1 or port 2. The incident power wave at port n is given by (3.29) and the reflected power wave at port n is given by (3.30). Vn and In are the voltage and current at port n and Z0 is the characteristic impedance of the two-port network. [ 1], [ 2]

Figure 3.4: Incident and reflected waves in a two-port network

Based on the directional convention shown in Figure 3.4, the s-parameters are defined as the matrix:

=

2

1

2221

1211

2

1

a

a

SS

SS

b

b ( 3.31)

where the terms are:

01

111

2 =

=a

ab

S (Input reflection) ( 3.32)

Section 3.2 Scattering parameters Chapter 3 Theory

15

01

221

2 =

=a

ab

S (Forward transmission) ( 3.33)

02

222

1=

=a

ab

S (Output reflection) ( 3.34)

02

112

1=

=a

ab

S (Reverse transmission) ( 3.35)

[ 1], [ 2] The term S11 represents the input reflection coefficient and is measured as the ratio between b1 and a1 when a2 = 0. The incident power wave on port 2 is equal to zero if the output port is properly terminated to an impedance equal to the characteristic impedance of the two-port network. This means that a traveling incident wave on the load will be totally absorbed and no energy will be returned to the output port. The term S21 represents the transmission from port 1 to port 2, S12 the transmission from port 2 to port 1 and S22 represents the output reflection coefficient of the network [ 1], [ 2] The advantage of measuring the ratio between normalized power waves instead of the total voltage or current is obvious. At high frequencies, accurate system characterizations can no longer be accomplished by measuring the total voltage or current through a two-port network. S-parameters are measured using matched terminations, i.e., no undesired reflections occur at the ports. The s-parameters for transistors are measured under specific bias conditions at small-signal levels. [ 1], [ 2]

3.3 Microwave transistor amplifiers RF and microwave amplifier design differ quite much from traditional low-frequency design. The most important design considerations in high-frequency amplifier design are stability, power gain, bandwidth, noise and DC requirements. The first step in a design is usually to obtain a model of a transistor. A non-linear, large-signal model is needed for the DC settings and the output-power characteristics. For parameters such as gain, noise and stability, a small-signal model of the transistor is required for the analysis. The small-signal model is usually represented as a set of s-parameters measured at a specific bias point. [ 1], [ 2], [ 3] This section focuses only on GaAs hetero junction field effect transistors (FETs) because of its outstanding frequency response and noise performance at frequencies above 4 GHz. [ 1], [ 2]

3.3.1 DC bias Biasing provides an appropriate operating point for the transistor under specified conditions. The choice of operating point depends upon the desired application. Different choices of operating points are shown in Figure 3.5 [ 1], [ 3]

Section 3.3 Microwave transistor amplifiers Chapter 3 Theory

16

Figure 3.5: Operating points

The lowest noise figure is obtained when the current through the transistor is small; approximately 10 % of the saturated drain current IDSS. A low noise amplifier is commonly designed for low power gain and the operating point is set to P1 shown in Figure 3.5. [ 3] Lower voltage on the gate, VGS, results in higher current, IDS, through the transistor. The operating point P2 results in a higher gain than the point P1. [ 3] To get as high output power as possible, an increase of the voltage is required. The operating point P3, shown in the figure, is biased to 50 % of IDSS and is recognized as a class A power amplifier. A class A amplifier has good linearity and the transistor is in a conducting state the whole signal period. The main disadvantage with a class A stage is its poor DC to RF efficiency, which has a theoretical maximum value of 50 %.[ 3] If the gate voltage, VGS, is increased to the operating point P4, the transistor has reached a non-conducting state and thus consumes no energy when no input signal is applied. The behavior of the transistor at this operating point is known as a class B power amplifier, which has similar output power as the class A stage but with lower gain and higher noise figure. [ 3] A compromise between the class A and class B power amplifiers is the class AB stage with the operating point P5. This type of amplifier is employed when a high-power linear amplification is required.[ 2], [ 3] According to the design specification, the supply voltage should be positive and unipolar. The book “Microwave transistor amplifiers” [ 1] contains different types of passive


17

biasing networks for FETs. The only biasing network that satisfies the required power supply is shown in Figure 3.6.

Figure 3.6: Unipolar biasing network for FET

The voltage drop over the resistance Rs limits the current in the transistor and gives the required bias setting on the gate. A DC blocking capacitance CB is connected in parallel over the resistance to prevent RF signal going through the resistance. At DC, all blocking capacitors CB represent an open circuit and all RFCs (radio frequency chokes) behave like short circuits. The voltage drop over Rs is determined with the expression:

sDSs RIV = ( 3.36)

The disadvantage with a resistance connected to the source of the transistor is a slight increase of the noise figure and poorer efficiency.[ 1], [ 2], [ 3]

3.3.2 Stability When designing amplifiers, one must ensure that the device is stable, i.e., no oscillations occur at any frequency. The amplifier can start to oscillate if the amplified signal is fed back to the input. If this occurs, the fed back signal may combine with reflections already present on the transistor to produce effective reflection coefficients whose magnitudes exceeds unity. The feedback can occur by the transistor itself and by the biasing network. [ 1], [ 2], [ 3] An amplifier is unconditionally stable, i.e., stable for all passive termination impedances on the input and output, if the following conditions are satisfied:

12

1

2112

2222

211 >

∆+−−=

SS

SSK ( 3.37)


18

and

0122

222

111 >∆−−+= SSB ( 3.38)

where

21122211 SSSS −=∆ ( 3.39)

[ 1], [ 2] The criterions for unconditional stability should be satisfied for all frequencies, i.e., it also includes frequencies outside the desired bandwidth. At low frequencies, the transistor has high gain and can readily start to oscillate. To ensure unconditional stability, the analysis should be done from DC to frequencies above the specified frequency range. [ 3] One way to stabilize an unstable transistor is to add resistances in series or in parallel to the input or output. Since a resistance produces thermal noise, it is preferable to put it on the output of the transistor. Placing it before the transistor will result in amplified noise. The series resistances should be as small as possible, since it reduces the gain and increases the noise figure of the amplifier.[ 1], [ 2], [ 3]

3.3.3 Gain An amplifier can be designed for maximum gain using matching networks on the input and output. The functionality of a matching network is to transform a given impedance to another value and thus reduce undesired reflections on the input and output. Maximum gain is achieved if the input and output ports of the transistor are conjugate matched to the source and load terminations. Figure 3.7 shows a transistor with input and output matching networks. [ 1], [ 2], [ 3]

Figure 3.7: Transistor with input and output matching networks


19

If the feedback parameter S12 of the transistor is neglected, the transistor is unilateral. Since there is no interaction between the input and output ports, the reflection coefficients are IN = S11 and OUT = S22. The maximum power flow is obtained when *

11SS =Γ

and *22SL =Γ , where a * indicates the complex conjugate of the parameters. The maximum

unilateral transducer gain, which defines the gain of the amplifier placed between source and load, is given by:

222

2212

112

22

22

21211

2

max,1

1

1

1

1

1

1

1

SS

SSS

SG

L

L

s

sTU

−−=

Γ−

Γ−

Γ−

Γ−= ( 3.40)

[ 1], [ 2] In reality, the transistors feedback parameter cannot be neglected. The interaction between the input and output makes the reflection coefficients dependent on each other. The optimal values of the reflection coefficients in the bilateral case (S12 0) are given by:

1

21

211

2

4

C

CBBMS

−±=Γ ( 3.41)

2

22

222

2

4

C

CBBML

−±=Γ ( 3.42)

where

2222

2111 1 ∆−−+= SSB ( 3.43)

22

112

222 1 ∆−−+= SSB ( 3.44)

and

*22111 SSC ∆−= ( 3.45)

*11222 SSC ∆−= ( 3.46)

[ 1], [ 2]


20

The maximum gain is obtained when the matching networks have the reflection coefficients MS and ML. When the reflection coefficients are found, matching networks can be designed with distributed or lumped components. The maximum transducer gain in the bilateral case is given by:

( ) ( )( )( ) 2

12212211

2221

2

max,11

11

MSMLMLMS

MSMLT

SSSS

SG

ΓΓ−Γ−Γ−

Γ−Γ−= ( 3.47)

[ 1], [ 2], [ 4]

3.3.4 Noise Noise can be defined as any random interference unrelated to the signal of interest. In many applications it is essential to minimize the generated noise since the signal level at the input may be extremely low. Three main causes of electrical noise in an amplifier are:

• Thermal noise, caused by the thermal agitation of free electrons in conductors.

• Shot noise, caused by the random fluctuation of current flow in semiconductors.

• Flicker noise, caused by fluctuation in the conductivity of the medium.[ 5]

An amplifier produces noise even if no input signal is applied and the noise performance is determined with the expression:

( ) 22

2

0min

11

4

optS

optSn

ZR

FFΓ+Γ−

Γ−Γ+= ( 3.48)

[ 1], [ 2], [ 3] The minimum noise figure Fmin, equivalent noise resistance Rn and optimum reflection coefficient opt are given in the transistor data sheet or measured by the manufacturer. [ 2] If an amplifier is designed for maximum gain, it might not give the best noise performance. For best noise performance, the input reflection coefficient S is transformed to opt using a matching network. Matching or mismatching the output does not have any effect on the signal-to-noise ratio and noise figure. A trade-off between gain, noise and VSWR has to be done when designing amplifiers.[ 1], [ 2], [ 4]

3.3.5 1-dB compression point When the input power is increased, the gain begins to fall off. The amount of input power that causes the small-signal gain of the amplifier to drop by 1 dB is called the 1-dB compression point. This is an important parameter when characterizing the nonlinear behavior of an amplifier. To obtain the 1-dB compression point, a nonlinear model of the


21

transistor is needed. The definition of the 1-dB compression point is shown in Figure 3.8 and can be calculated as:

)(1)()()( 1,01,11, dBmPdBdBGdBmPdBGP dBindBindBdBout +−=+= ( 3.49)

where G1dB is the gain where the small-signal gain G0 has dropped by 1 dB. [ 2], [ 5]

Figure 3.8: Definition of the 1-dB compression point

3.3.6 Third-order intercept point Since the amplifier begins to work in a nonlinear region when the input power is increased, the small-signal assumption is no longer valid. The input-output relationship of the nonlinear amplifier can be described with the Taylor expansion:

( ) ( ) ( ) ( ) ...33

221 +++= txtxtxty ααα ( 3.50)

[ 1], [ 5] A sinusoidal input signal )cos()cos()( 2211 tAtAtx ωω += applied to (3.50) gives an output signal containing frequency components at DC, 1, 2, 21, 22, 31, 32, 1±2, 21±2 and 22±1. The frequencies 1 and 2 are the fundamentals, 21, 22, 31 and 32 are the harmonics, 1±2 are the second-order intermodulation products and 21±2 and 22±1 are the third-order intermodulation products. [ 1], [ 5]


22

If the frequencies 1 and 2 are close to each other, the third-order intermodulation products at 21-2 and 22-1 might fall within the amplifiers bandwidth and cause distortion. Figure 3.9 [ 1] shows the output powers of the third-order intermodulation product P21-2 and the fundamental component P1 versus the input power. If the two curves are extrapolated in the linear region, the point where they intercept is defined as the third-order intercept point. [ 1], [ 5]

Figure 3.9: Definition of the third-order intercept point

The third-order output intercept point OIP3 is a quantity that characterizes the linearity of an amplifier. It is therefore good to have as high OIP3 as possible.[ 1], [ 5]

3.4 Broadband amplifiers An amplifier is considered to be broadband if its bandwidth is greater than 20 % of the center frequency. The transistor s-parameters vary with frequency, as shown in Figure 3.10 [ 1]. Typically, |S21| decreases with frequency at a rate of 6 dB/octave and |S12| increases with frequency at the same rate. The frequency variation of the product |S12S21| is critical, since the stability of the amplifier depends on this quantity. [ 1], [ 4]

Section 3.4 Broadband amplifiers Chapter 3 Theory

23

Figure 3.10: Frequency behavior of |S21|, |S12| and |S12S21|

There are two commonly used methods to compensate the frequency variations of the transistor s-parameters in broadband amplifiers. One is to use frequency compensated matching networks, and the other is to use negative feedback. The technique of negative feedback is not covered in this thesis report since it tends to limit the maximum power gain and increase the noise figure of the amplifier.[ 1], [ 2]

3.4.1 Frequency compensated networks The frequency variations of |S21| can be compensated by introducing frequency compensated matching networks. The technique involves mismatching the output and input at low frequencies to compensate for the variations. As shown in Figure 3.11 [ 4], the gain is decreased at low frequencies and increased at high frequencies. Design of frequency compensated matching networks requires a CAD tool since it is almost impossible to obtain the networks in an analytical way. [ 1], [ 2], [ 4]


24

Figure 3.11: Increase and decrease of the transducer gain

The main disadvantage with this technique is the poor impedance match. Since the gain is decreased at some frequencies, more power is reflected. According to the design specification, the input and output reflections of the amplifier should be less than -15 dB. These requirements are not possible to achieve by only using frequency compensated networks. One practical way to achieve good impedance match is to use a balanced amplifier configuration. [ 1], [ 2], [ 4]

3.4.2 Balanced amplifiers A good impedance match on the input and output is achieved if two identical amplifier branches are placed between two 3-dB 90˚ hybrids. This thesis report focuses only on the Lange coupler since it is the smallest microstrip realization of a 3-dB 90˚ hybrid and is possible to fabricate with the GMIC process. Signals reflected from the input and output ports of amplifiers A and B in Figure 3.12 are summed together and dissipated in the 50- terminations on the hybrids. As a result, the balanced amplifier is completely isolated from reflected signals and matched to 50 . Figure 3.12 shows a balanced amplifier configuration using two 3-dB 90˚ hybrids. [ 1], [ 2], [ 4], [ 6]


25

Figure 3.12: Balanced amplifier using 3-dB 90˚ hybrids

The 3-dB 90˚ hybrid on the input works as a power divider and the one on the output works as a power combiner. The incident power wave on the input in Figure 3.12 is equally divided in magnitude but with a phase shift of 90˚ between the input ports of amplifiers A and B. The output 3-dB 90˚ hybrid combines the output signals from amplifiers A and B by introducing an additional 90˚ phase shift, thus bringing them in phase again. The s-parameters for a balanced amplifier are given by:

BA

BA

BA

BA

SSS

SSS

SSS

SSS

222222

121212

212121

111111

21212121

−=

+=

+=

−=

( 3.51)

[ 1], [ 2], [ 4], [ 6] If the two amplifier branches are identical, then S11 = S22 = 0. The forward and reverse transmissions, S21 and S12, are equal to one branch of the amplifier. The main advantages with a balanced amplifier are:

1. Good impedance match if the amplifiers in both branches have similar characteristics.

2. The output power is twice that obtained from a single amplifier.

3. Noise figure almost the same as in a single branch.


26

4. Easy to cascade with other units, since the amplifier is isolated by the 3-dB 90˚ hybrid.

5. One of the two amplifiers continues to operate even if the other one fails.

The drawbacks with a balanced amplifier are that it is larger and contains two amplifiers, thus consumes more DC power. [ 1] A microstrip realization of a 3-dB 90˚ hybrid is the Lange coupler. When the Lange coupler is used as a 3-dB hybrid, port 4 is terminated to 50 . The Lange coupler has interconnections between the microstrip lines to achieve half of the incident power from port 1 to ports 2 and 3, i.e., transmissions of -3 dB. Design of a Lange coupler involves specification of the length l, conductor width w and spacing d. The length l should be /4 at the center frequency to achieve the phase shift of 90˚ between ports 2 and 3. Figure 3.13 [ 2] shows a Lange coupler with port 4 terminated to 50 . [ 1], [ 2], [ 4], [ 6]

Figure 3.13: Lange coupler with port 4 terminated to 50

27

4 The GMIC process The GMIC (Glass Microwave Integrated Circuit) process is a circuit technology, which has been under development at M/A-COM since 1985. GMIC provides a broad range of hybrid applications as well as efficient integration. GMIC is an extremely reproducible and robust fabrication technology capable of meeting the needs for high performance, complex microwave circuits in space, defense and other high reliability applications. M/A-COM offers different techniques of manufacturing GMIC applications. The amplifier in this thesis report uses the full glass process since it provides the highest performance and highest design flexibility. Due to the confidentiality of the GMIC process, no comprehensive process overview can be given in this thesis report. This chapter is written under permission from M/A-COM.[ 7], [ 8]

4.1 The GMIC substrate The GMIC substrate consists of a glass wafer laminated to a silicon wafer. The glass layer serves as the microstrip transmission medium and the silicon layer provides mechanical support and creates an integral carrier. Since glass has poor thermal conductivity, the silicon layer provides good heat transfer through the substrate. Other reasons why silicon is used are that it has thermal expansion match to glass, smooth surface and is cheap to manufacture. The glass and silicon layers have thicknesses of 200 µm and 400 µm respectively. [ 7], [ 8] The composite microwave structure allows the use of standard silicon chemical processing, photolithographic and thin-film deposition techniques. By this method it is possible to produce two layers of metallization, resistors, capacitors, inductors, conductors, air bridges and plated via holes. [ 7], [ 8]

4.1.1 Conductor traces Conductor traces are formed by one of the metallization layers on the GMIC substrate. Table 4.1 contains current ratings for different conductor widths. The minimum width of a conductor is limited to 10 µm. [ 7], [ 8]

Table 4.1: Current ratings for conductors

Width (m) Current limit (mA) 25 40 50 75 75 100

A conductor with the width W = 407 µm results in a characteristic impedance of 50 at 10 GHz. The value of the characteristic impedance was calculated with the utility TXLine in

Section 4.1 The GMIC substrate Chapter 4 The GMIC process

28

Microwave Office. Measurements have shown losses to be 0.02 dB/mm at 18 GHz for a 50- line. [ 7], [ 8]

4.1.2 Airbridge interconnections Airbridge interconnections are used when conductor cross-unders are needed and when interconnecting elements. An airbridge consists of support pillars at the interface between two metallization layers. Figure 4.1 shows a cross-sectional view of an airbridge. The yellow areas in the figure represent the microstrip metallization layer. [ 7], [ 8]

Figure 4.1: Cross-sectional view of an airbridge

Calculations have showed that a force >100,000 g would be required to lift a typical airbridge due to the low mass and the relatively large area of the support pillars. Figure 4.2 shows the Microwave Office layout of an airbridge. The airbridges are modeled by the ABRIDGE model in Microwave Office. [ 7], [ 8], [ 9]

Figure 4.2: MWO layout of an Airbridge

4.1.3 Pedestals The silicon wafer in the GMIC substrate is highly doped thus provides good electrical connection between the glass-silicon interface and the ground plane when pedestals are used. Pedestals are via holes that maintain access from the glass layer to the ground plane. Since glass has poor thermal conductivity, active devices is mounted on pedestal to increase the heat transfer from the substrate. Figure 4.3 shows the Microwave Office layout of a pedestal. The pedestals are modeled in Microwave Office by a resistance R = 1x10-4 connected to ground. [ 7], [ 8], [ 9]

Section 4.1 The GMIC substrate Chapter 4 The GMIC process

29

Figure 4.3: MWO layout of a pedestal

On the top of the pedestal, metal layers are plated up to maintain electrical connection to other elements. Since pedestals are created by the use of hydrofluoric etchant, an under etch is introduced. The gray area surrounding the pedestal in Figure 4.3 represents the under etch. [ 7], [ 8], [ 9]

4.2 Passive elements The GMIC substrate offers a high level integration of passive elements, such as MIM (Metal-Insulator-Metal) capacitors, thin-film resistors and spiral inductors.

4.2.1 MIM Capacitor A MIM capacitor consists of two parallel metal plates separated by a dielectric layer. Figure 4.4 shows the Microwave Office layout of a GMIC capacitor with width and length equal to 150 m. The bottom plate of the capacitor consists of a thin metal layer followed by a dielectric layer. The top plate of the capacitor consists of one of the metallization layers. An airbridge is used to interconnect the capacitor top-plate with the adjacent conductor. [ 7], [ 8]

Section 4.2 Passive elements Chapter 4 The GMIC process

30

Figure 4.4: MWO layout of a MIM capacitor

The capacitance value of a GMIC capacitor is calculated with the expression:

fp CCC += ( 4.1)

where the principal capacitance Cp is given by:

pFd

LWC r

p

60 10×

=εε

( 4.2)

and the fringing capacitance Cf by:

( ) pFLWC f 22104.2 4 +×= − ( 4.3)

[ 7] The capacitor width W, length L and dielectric thickness d are in µm. A capacitor with a width W = 150 m, length L = 150 m and the dielectric thickness and relative dielectric constant of the layer in the GMIC process results in a certain capacitance value. If the capacitance value is divided by the capacitor area, a certain sheet capacitance in F/m2 is obtained. This value is required when using the TFCM (thin-film capacitor for MMIC) in Microwave Office. [ 9] To evaluate the Microwave Office model of a thin-film capacitor, the layout has been exported to HFSS (High Frequency Structure Simulator) from Ansoft. The HFSS simulation tool utilizes FEM (Finite Element Method) to solve Maxwell’s equations in the 3-D structure. To avoid boundary effects, de-embedded conductor traces with the length 1000 m have been added to the ports of the capacitor. Figure 4.5 shows the 3-D HFSS model of the MIM capacitor.


31

Figure 4.5: 3-D HFSS model of a MIM capacitor

The results from HFSS have been exported to Microwave Office as a set of s-parameters. Figure 4.6 shows S11 and S21 for the Microwave Office and HFSS models.

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

CSwp Max

15GHz

Swp Min5GHz

S(1,1)C_HFSS_MODEL

S(2,1)C_HFSS_MODEL

S(1,1)C_MWO_MODEL

S(2,1)C_MWO_MODEL

Figure 4.6: Comparison between capacitor models

The simulated results presented in Figure 4.6 show that the accuracy of the Microwave Office model is excellent in the desired frequency range. Since the good accuracy, it was decided to use the Microwave Office model TFCM in this thesis work

4.2.2 Thin-film resistor Thin-film resistances are implemented on the substrate by a layer with a certain resistivity. Connections to the resistive layer are achieved by the metallization layer used when implementing conductors. The width and length of the thin-film resistor correspond to the


32

width of the metallization layer and the length of the resistive layer. The resistance value is calculated with the expression:

WL

RR s ⋅= ( 4.4)

[ 7], [ 8] where L is the length, W is the width and Rs is the sheet resistivity in /. Figure 4.7 shows the Microwave Office layout of a 50- thin-film resistor with the width W = 407 µm. [ 9]

Figure 4.7: MWO layout of a thin-film resistor

To validate the Microwave Office model of a thin-film resistor, the layout has been exported to HFSS. The model that is used in Microwave Office is the TFR model. Figure 4.8 shows the 3-D HFSS model of the thin-film resistor.

Figure 4.8: 3-D HFSS model of a thin-film resistor

The simulation results from HFSS have been exported to Microwave Office and compared to the TFR model. Figure 4.9 shows the input reflections and the forward transmissions of the two models.


33

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

RSwp Max

15GHz

Swp Min5GHz

S(1,1)R_MWO_MODEL

S(1,1)R_HFSS_MODEL

S(2,1)R_HFSS_MODEL

S(2,1)R_MWO_MODEL

Figure 4.9: Comparison between resistor models

The simulated results in Figure 4.9 show that the Microwave Office TFR model is valid for the GMIC thin-film resistors. Since the good accuracy between the models, it was decided to use the Microwave Office model TFR in this thesis work.

4.2.3 Spiral inductor Spiral inductors are implemented on the substrate as loops by one of the metallization layers. The inner turn is brought to the outside by a cross-under. A cross-under is constructed as a thin conductor with a dielectric layer above overlapped by an airbridge. Figure 4.10 shows the Microwave Office layout of a spiral inductor with 13 segments, the dimensions 575 m x 575 m, the conductor width W = 50 m and the conductor spacing S = 25 m. These dimensions resulted in the best performance at 10 GHz. According to the design specification, the current consumption should be less than 50 mA. A conductor with a width of 50 m allows a maximum current of 75 mA, as given in Table 4.1. [ 7], [ 8], [ 9]


34

Figure 4.10: MWO layout of a spiral inductor

To analyze the behavior, the spiral inductor has been exported to HFSS. Figure 4.11 shows the 3-D HFSS model and Figure 4.12 shows the comparison with the Microwave Office model MRINDSBR.

Figure 4.11: 3-D HFSS model of a spiral inductor


35

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

LSwp Max

15GHz

Swp Min5GHz

S(2,1)L_HFSS_MODEL

S(2,1)L_MWO_MODEL

S(1,1)L_MWO_MODEL

S(1,1)L_HFSS_MODEL

Figure 4.12: Comparison between inductor models

The simulated results presented in Figure 4.12 show that S11 and S21 differ between the models. To get as accurate model as possible in the amplifier design, it was decided to use the HFSS model. The spiral inductors will be used as RF chokes, i.e., to create large impedances at the center frequency. Figure 4.13 shows the input impedance of the spiral inductor modeled by HFSS. It can be seen that the inductor has an impedance peak of 1169 at 10.2 GHz.

5 10 15Frequency (GHz)

Spiral inductor

0

500

1000

1500

Impe

danc

e (O

hm)

|ZIN(1)| (Ohm)L_HFSS_MODEL

Figure 4.13: Input impedance of the spiral inductor

Section 4.3 Lange coupler Chapter 4 The GMIC process

36

4.3 Lange coupler The conductor traces in the Microwave Office layout shown in Figure 4.14 were implemented by one of the metallization layers and the interconnections between adjacent conductors were made as cross-unders. To get a characteristic impedance of 50 , the ports have been designed with a width of 407 m.[ 8], [ 10]

Figure 4.14: MWO layout of a Lange coupler

A Lange coupler with the length L = 4638 m, conductor width W = 50 m and the conductor spacing S = 20 m resulted in the best performance at the desired frequency range. These dimensions were found by simulating the structure in HFSS. Figure 4.15 shows the transmissions S21 and S31 of the HFSS model. [ 10]

7 9 11 13 15Frequency (GHz)

magnitude

-5

-4

-3

-2

-1

0

Tran

smis

sion

(dB

)

DB(|S(2,1)|)Lange_4638_50Ohm_W50_s20

DB(|S(3,1)|)Lange_4638_50Ohm_W50_s20

Figure 4.15: S21 and S31 for the Lange coupler

The results presented in Figure 4.15 show that the transmissions S21 and S31 are -3 dB, i.e., the magnitude of the incident power on port 1 is equally divided between ports 2 and 3. It can also be seen that the center frequency of the Lange coupler is at approximately 10 GHz. Another important feature of the Lange coupler is the phase difference of 90˚ between ports 2 and 3. The phase difference was achieved by (4.5) and the simulated result for this quantity is shown in Figure 4.16.

=

31

21argSSϕ ( 4.5)

Section 4.3 Lange coupler Chapter 4 The GMIC process

37


phase difference

0

20

40

60

80

100

Pha

se d

iffer

ence

(D

eg)

Figure 4.16: Phase difference between ports 2 and 3

Figure 4.16 shows that the Lange coupler has a phase difference of 90˚ at 8 GHz and approximately 92˚ at 12 GHz. The difference of 2˚ between the frequencies 8 and 12 GHz can be neglected. [ 10]

38

39

5 Design process This chapter covers the whole design process of the balanced amplifier in a chronological order.

5.1 The transistor The selected transistor for the amplifier was the Excelics EPA018A high efficiency hetero junction power FET. The EPA018A have a noise figure of 0.75 dB and an associated gain of 12.5 dB at 12 GHz. Maximum ratings is listed in Table 5.1.

Table 5.1: Maximum ratings

Parameter Maximum value Description Vds 12 V Drain-source voltage Vgs -8 V Gate-source voltage Ids 80 mA Drain current Igsf 9 mA Forward gate current Pin 20 dBm Input power Tch 175 ˚C Channel temperature Tstg -65 – 175 ˚C Storage temperature Pt 740 mW Total power dissipation

Exceeding any of the ratings listed in Table 5.1 may cause permanent damage of the transistor. The manufacturer has rated the maximum input power to 20 dBm, which is 4 dBm more than the value given in the transistor data sheet [ 11]. If 20 dBm is applied to the input of the balanced amplifier, 17 dBm will reach the two transistors since the Lange coupler at the input divides the incident power equally between the two amplifier branches. This transistor satisfies all of the specified requirements given in the design specification, such as gain, noise figure and power handling capabilities. [ 11]

5.1.1 Small-signal model The small-signal model of the transistor has been included in the design as a set of s-parameters measured under specific bias conditions. According to the design specification, the current consumption should be less than 50 mA. Since a balanced amplifier contains two transistors, each will have a maximum current limited to 25 mA.

Section 5.1 The transistor Chapter 5 Design process

40

The bias points of the transistors have therefore been set to 4 V and 25 mA. To analyze the uniformity, five s-parameter files measured within the same wafer by the manufacturer were used. S-parameter files with the following bias points were included in the design: 4 V, 24.6 mA; 4 V, 24.9 mA; 4 V, 24.7 mA; 4 V, 24.5 mA; 4 V, 24.6 mA. The s-parameter file with the bias point 4 V, 24.9 mA is the only one that contains noise parameters and was therefore used in the nominal design. The provided s-parameters were measured on an Al2O3 carrier with the following bond wires included:

• 1 gate wire with a length of 15 mils (1 mil = 25.4 m). • 1 drain wire with a length of 20 mils. • 6 source wires, each with a length of 8 mils.

All of the bond wires have the diameter 0.7 mil and are fabricated by gold. [ 11] Since the s-parameters were measured on an Al2O3 carrier, the behavior may vary when a glass substrate is used. This effect has not been covered in this thesis work.

5.1.2 Large-signal model The large-signal model of the transistor has been represented as a Curtice-Ettenburg model in Microwave Office. Large-signal model parameters were provided from the manufacturer. The Curtice-Ettenburg model in Microwave Office has bond wires included as inductors connected in series to the gate, source and drain. [ 12]

5.1.3 Footprint To mount the transistor on the substrate, a footprint was needed. The dimensions for the footprint were found in the transistor data sheet [ 11]. A footprint with these dimensions was created with the GMIC substrate. For grounding and thermal purposes, the footprint was constructed on a pedestal. The footprint consists of two metallization layers separated by an airbridge pillar. Figure 5.1 shows the transistor footprint with dimensions in m and alignments for gate, source and drain. [ 9], [ 11]

Section 5.1 The transistor Chapter 5 Design process

41

Figure 5.1: Transistor footprint

5.2 DC bias To determine the DC bias settings, a biasing network was needed. The topology of the created biasing network is the same as the network shown in Figure 3.6 in the theory chapter. The first step in the biasing network design was to add bond wires, bypass capacitors and bond pads to the transistor footprint.

Figure 5.2: Transistor footprint with bond wires, capacitors and bond pads

Connected to source resistor

Section 5.2 DC bias Chapter 5 Design process

42

Figure 5.2 shows the transistor footprint with bond wires, bypass capacitors and bond pads. The included bond wires have been given the same dimensions as the ones used in the s-parameter measurements. The DC connection between the two source connections was achieved by a conductor trace between the two bypass capacitors top-plates. A conductor has been connected to the lower capacitor top-plate to provide the DC connection to the source resistor. To be able to measure the current through the transistor, a probe point has been attached on the conductor connected to the resistor. The probe point was implemented as an airbridge support pillar with a metallization layer above. The bypass capacitors bottom plates overlap the transistor footprint thus provide the necessary ground connections by the pedestal where the active device will be mounted. Both bypass capacitors have the dimensions 200 m x 200 m. The bond pads where the transistor gate and drain are connected have been implemented as airbridge support pillars with the dimensions 100 m x 150 m. The next step in the biasing network design was to add blocking capacitors and a RFC, as shown in Figure 5.3. DC blocking capacitors with the dimensions 150 m x 150 m have been placed on the transistor input and output to force the DC signal going to the transistor. The large impedance created by the spiral inductor at the center frequency prevents the RF signal going to the DC voltage supply. A capacitor with the dimensions 480 m x 480 m placed on a pedestal has been connected to the spiral inductor to create a RF ground at this node. According to the biasing network presented in the theory chapter, a RFC should be connected to the transistor gate to achieve the required DC connection to ground. Instead of using a RFC, the DC connection to ground was implemented with the two resistors placed on the input of the amplifier. Resistance values and motives for the two resistors are covered in the next section.


43

Figure 5.3: Biasing network

The resistance value of the resistor connected to the transistor source was found by simulating the current through the transistor with an applied DC voltage of 4 V. With the resistance value R = 18.9 , the required current of 25 mA was found. Figure 5.4 shows the transistor IV-curve.

0 2 4 6Voltage (V)

bias

0

5

10

15

20

25

30

Cur

rent

(mA

)

p1

4 V24.75 mA

Figure 5.4: IV-curve

With the bias settings shown in Figure 5.4, the transistor has been biased to approximately 30 % of the saturated drain current IDSS. An amplifier with this bias setting results in the characteristic as a compromise between a class A and class AB stage.

Connected to source resistor

RF ground


44

Since the DC properties vary between different transistors fabricated within the same wafer, a tuning option was needed. To be able to tune the DC settings of the transistor, a resistor network was created. Figure 5.5 shows the resistor network.

Figure 5.5: Resistor network

The resistor network consists of five resistors with the resistance values given in Table 5.2. To achieve DC connection, an airbridge has been added on the middle branch in the network shown in Figure 5.5, hence the resistor R = 18.9 was used in the nominal design. All other resistors have been de-coupled by conductor gaps. Airbridge support pillars have been added on each side of the gaps to facilitate DC connection by manual bonding when another resistance value is needed. Of course, the implemented airbridge needs to be taken away when another resistor is used. APPENDIX A contains the Microwave Office schematic of the resistor network.

Table 5.2: Resistance values

Resistor no. Resistance value () 1 11.9 2 15.4 3 18.9 4 22.4 5 25.9

According to the design specification, the two amplifier branches should be biased from the same DC supply. The main issue with this requirement was to implement the DC


45

crossing on the upper transistor output signal path. One way to solve this problem was to implement the DC crossing as a cross-under. The main draw-back with this technique was that the electric coupling between the DC and RF paths became to strong and thus RF signal on the DC path was achieved. The simplest way to circumvent this problem was to use a network with the topology shown in Figure 5.6.

Figure 5.6: DC supply network

The functionality of the network in Figure 5.6 is quite simple. All of the RF signal from transistor 1 will reach the port named RFout 1 since the RFCs act like short circuits at DC and open circuits at the center frequency. The same functionality is maintained from transistor 2 to RFout 2. The DC signal applied at VDD will pass through the RFCs and will be blocked by the capacitors. Capacitors connected to ground are used to get low RF impedance at the nodes where the RFCs are connected. The DC current contributed by the supply will be divided equally between the two amplifier branches. A current of 50 mA from the supply results in the required currents of 25 mA in both amplifier branches. The motive for the RFC connected to the blocking capacitor placed on the lower amplifier branch was to ensure that the ports RFout 1 and RFout 2 are seeing equal impedances, hence the balanced amplifier performance.


46

Figure 5.7 shows the Microwave Office layout of the DC supply network. The distance between the two amplifier branches has been set to fit the ports of the Lange coupler, which has a length of 4638 m. The large capacitors have been placed on pedestals to ensure the desired ground connection. Small capacitors placed on pedestals have been added to the voltage supply line to prevent any present RF signal reaching the voltage supply and thus starting the amplifier to oscillate. APPENDIX A contains the Microwave Office schematic of the DC supply.

Figure 5.7: Layout of DC supply network

To measure the isolation of the network, ports have been added as shown in Figure 5.7 and the simulated results are shown in Figure 5.8.


47


Isolation

-80

-60

-40

-20

0

Tra

nsm

issi

on (d

B)

DB(|S(2,1)|)DCSupply







Figure 5.8: Isolation

The results presented in Figure 5.8 show that an equal isolation of approximately 33 dB was achieved between the RF signal paths represented by S41, S31, S13 and S23. Between the output of the upper transistor and the voltage supply, the simulated result of S51 shows that the isolation is greater than 43 dB within the desired frequency range. The transmissions from the output of the two transistors to the corresponding output of the network, S21 and S43, are almost 0 dB, i.e., no dampings occur between these ports. At the frequency f = 12 GHz, S21 and S43 have reduced to -0.5 dB. Figure 5.9 shows the Microwave Office layout of the complete biasing network. To avoid cross-coupling, all adjacent RF signal paths have a minimum separation of twice the substrate height, i.e., 407 m. Since the current from the supply is 50 mA, the DC conductor traces have been given a width of 50 m. To minimize the occupied space, the two resistor networks share the same pedestal.


48

Figure 5.9: Complete biasing network

To ensure that correct voltages and currents are applied on the two transistors, the annotation utility in Microwave Office was used. As shown in Figure 5.10, the currents have been divided equally between the two amplifier branches. Only a minimal voltage drop of 0.01 V has occurred between the upper and lower amplifier stages.

Figure 5.10: Currents and voltages through the transistors, A: upper and B: lower

Section 5.3 Stability Chapter 5 Design process

49

5.3 Stability According to the design specification, the amplifier should be unconditional stable. The stability of the amplifier has been investigated by simulating the stability factors K and B1. Figure 5.11 shows the simulated stability factors of the upper amplifier branch. According to the symmetry in the design, the same results were achieved by simulating the lower amplifier branch.


Stability

-2

-1

0

1

2

3

4

5

Sta

bilit

y fa

ctor

s

B1()Unstable

K()Unstable

Figure 5.11: Stability factors of the unstable amplifier

The criterions for unconditional stability are: K > 1 and B1 > 0 for all frequencies. Since these requirements were not fulfilled, stabilization was needed. The stabilization has been performed by adding resistors in series and in parallel to the amplifiers input and output. Since resistors increase the noise in the amplifier, the noise figure was simulated. Figure 5.12 shows the simulated result for the minimum noise figure and the noise figure of the unstable amplifier. As shown in the figure, the unstable amplifier has a noise figure of approximately 1 dB.


50


Noise

0

1

2

3

4

5

Noi

se (d

B)

DB(NF())Unstable

DB(NFMin())Unstable

Figure 5.12: Noise figure of the unstable amplifier

The unconditional stability requirements were satisfied when a shunt resistor was connected to the input and a shunt resistor connected to a series resistor on the output, as shown in Figure 5.13. The series resistor has been implemented with as small resistance value as possible since a large series resistor dissipates more power. To minimize the damping of the amplifier, the shunt resistors have been given large resistance values. According to the theory section, resistors are preferable placed on the transistor output since the noise caused by a resistor on the input results in amplified noise. No combination without a shunt resistor on the input was found to satisfy the unconditional stability requirements.

Figure 5.13: Stabilization resistors

When the stabilization resistors were included in the design, the stability factors shown in Figure 5.14 were obtained.


51


Stability

-2

-1

0

1

2

3

4

5

Sta

bilit

y fa

ctor

s

B1()Stable

K()Stable

Figure 5.14: Stability factors of the stable amplifier

With the stabilization resistors added, the unconditional stability requirements were satisfied. To investigate the increase of the noise figure introduced by the stabilization resistors, a simulation was performed. Figure 5.15 shows the simulated result of the noise figure.


Noise

0

1

2

3

4

5

Noi

se (d

B)

DB(NF())Stable

DB(NFMin())Stable

Figure 5.15: Noise figure of the stable amplifier

A conclusion drawn on the results of the noise figures of the stable and unstable amplifiers was that the stabilization resistors introduced an additional noise of approximately 0.7 dB. No modification of the stabilization resistors were needed since the noise figure of 1.7 dB within the frequency range fulfills the requirement given in the design specification.


52

Figure 5.16 shows the layout of the two amplifier branches with the stabilization resistors included. To avoid coupling between the shunt resistor on the input of the transistor and the resistor network, it was decided to split the resistor into two resistors with resistance values of 210 and 280 connected in series by a conductor bended by an angle of 90˚. Table 5.3 shows the resistance values of the stabilization resistors.

Figure 5.16: Stabilized amplifier branches

Table 5.3: Stabilization resistors

Identification Resistance value () Shunt input (1 of 2) 210 Shunt input (2 of 2) 280 Shunt output 100 Series output 6

Section 5.4 Impedance matching Chapter 5 Design process

53

5.4 Impedance matching The gain of a stabilized amplifier branch has a maximum value of 9.5 dB at 4.5 GHz. Between the frequencies 8 GHz and 12 GHz, the gain decreased from 8.8 dB to 6.6 dB, as shown in Figure 5.17. According to the design specification, the gain should be greater than 8 dB and vary by less than ± 1 dB within the frequency range. To achieve the required gain performance, matching networks were needed on the input and output. Tuning options have been included on both matching networks since the properties vary between different transistors fabricated within the same wafer.

0 5 10 15Frequency (GHz)

S21

0

2

4

6

8

10

12

Tran

smis

sion

(dB

)

DB(|S(2,1)|)Unmatched

Figure 5.17: S21 of unmatched amplifier branch

5.4.1 Input matching network The matching networks placed on the inputs of the amplifier branches were designed as open microstrip lines with a length of 2735 m and a width of 200 m. Tuning options have been included on the open line as small microstrip segments interconnected by airbridges. To facilitate manual change of length, airbridge support pillars have been placed on the disconnected conductor segments. When a shorter line is needed, one of the implemented airbridges has to be taken away. The distance between the tuning segments have been set to 125 m. Impedance transformers have been added to minimize discontinuity when connected between the Lange coupler and the blocking capacitors of the two amplifier branches. All dimensions of the input matching network shown in Figure 5.18 have been found by using the optimization utility in Microwave Office. To increase the degrees of freedom when finding optimal dimensions, the thin conductor placed between the two impedance transformers was added. A matching network with these properties suppresses high frequencies outside the desired bandwidth.


54

Figure 5.18: Input matching network

To verify that no coupling occurred between the open line and the adjacent tuning segment, the layout was exported to HFSS. The first layout that was exported to HFSS was designed with an un-mitered conductor and the second layout was designed with the optimal-miter feature in Microwave Office. As shown in Figure 5.19, the radiated electric field was heavily reduced when the optimal mitered microstrip was used. The input matching networks were therefore designed with the optimal miter feature. The HFSS results also showed that the accuracy of the Microwave Office model was improved when the optimal miter feature was used, as shown in Figure 5.20. The results presented in Figure 5.20 were achieved by simulating the phase of the reflection coefficient when looking into the mitered and un-mitered microstrip lines.

Figure 5.19: Field radiation, A: un-mitered, B: optimal mitered

A B


55


Open

-140

-120

-100

-80

-60

Pha

se (D

eg)

Ang(S(1,1)) (Deg)open_MWO_unmitered

Ang(S(1,1)) (Deg)open_MWO_optimal_mitered

Ang(S(1,1)) (Deg)open_HFSS_optimal_mitered

Ang(S(1,1)) (Deg)open_HFSS_unmitered

Figure 5.20: Comparison between HFSS and MWO models

5.4.2 Output matching network The matching networks placed on the outputs of the amplifier branches were designed as microstrip lines connected to two pedestals, as shown in Figure 5.21. Dimensions of the two impedance transformers and the conductor connected to the tuning network were found by using the optimization utility in Microwave Office. The optimal width and length of the conductor were found to 50 m and 2000 m respectively and the two impedance transformers widths were set to fit the series stabilization resistor width and the port of the output Lange coupler. Tuning options have been implemented as a variable length of the conductor connected to ground. The spacing of 371 m between the conductor and ground has been designed as a de-coupled conductor with a length and width of 250 m and 50 m respectively, as shown in Figure 5.21. An airbridge has been added to interconnect the microstrip connected to the amplifier branch and the grounded conductor placed in the middle. When another conductor length is needed, the airbridge has to be moved. To verify that no undesired cross-coupling occurs, the structure was simulated in HFSS. The phases of the reflection coefficients when looking into the HFSS and Microwave Office models have been compared, as shown in Figure 5.22. At 12 GHz, the phase difference between the models has its maximum of approximately 3˚. Since the small phase difference, it was decided to use the Microwave Office model in the amplifier design. A matching network with these properties suppresses low frequencies outside the desired bandwidth and thus improves the stability since high gain at low frequencies can start undesired oscillations in the amplifier. APPENDIX A contains the Microwave Office schematic of the output matching network.


56

Figure 5.21: Output matching network


Grounded

20

30

40

50

60

Pha

se (D

eg)

Ang(S(1,1)) (Deg)grounded_MWO

Ang(S(1,1)) (Deg)grounded_HFSS

Figure 5.22: Comparison between HFSS and MWO models

Figure 5.23 shows the layout of the matched amplifier branches. Both amplifier branches have a length of 4700 m and have been designed as identical stages. The ports of each stage will be connected to the Lange couplers and have been designed with a width of 407 m, i.e., a characteristic impedance of 50 . To avoid cross-coupling, adjacent RF paths have been separated by at least 407 m.


57

Figure 5.23: Matched amplifier branches

The optimization goals used when finding the dimensions of the matching networks were that S21 of each amplifier branch should be greater than 8.6 dB and smaller than 9.3. Figure 5.24 shows that these optimization goals were satisfied. At the frequencies 8 GHz and 12 GHz, the gains are 8.7 dB and 9 dB respectively. The maximum value of the gain, 9.2 dB, was found at the frequency 11.25 GHz. When other linear transistor models were used in the simulations, it showed that the gain decreased at frequencies above 11 GHz. The matching networks were therefore designed to introduce a slight increase of gain with respect to the frequency. APPENDIX A contains the Microwave Office schematic of a matched amplifier branch.


58


S21

0

2

4

6

8

10

12

Tran

smis

sion

(dB

)

DB(|S(2,1)|)Matched

Figure 5.24: S21 of matched amplifier branch

To investigate the noise introduced by the matching networks, a simulation was performed. The result presented in Figure 5.25 shows that the matching networks were adding approximately 0.3 dB noise in each amplifier branch. According to the design specification, the noise figure of the amplifier should be less than 3 dB. Since the noise figure of a balanced amplifier is almost to the same as in a single branch, no modifications of the matching networks were needed.


Noise

0

1

2

3

4

5

Noi

se (d

B)

DB(NF())Matched

DB(NFMin())Matched

Figure 5.25: Noise figure of matched amplifier branch

The flat and broadband frequency response of the two amplifier branches were achieved by mismatching the input and output at some of the frequencies. As shown in Figure 5.26, poor impedance matches were achieved on the input at frequencies between 8 – 11 GHz and on the output at frequencies above 10 GHz.


59


S11_S22

-30

-25

-20

-15

-10

-5

0

Ref

lect

ion

(dB

)

DB(|S(1,1)|)Matched

DB(|S(2,2)|)Matched

Figure 5.26: S11 and S22 of matched amplifier branch

5.5 The balanced amplifier To eliminate the reflections caused by the matching networks, the Lange couplers described in section 4.3 were included in the design. Figure 5.27 shows the circuit schematic of the balanced amplifier. As shown in the figure, the Lange couplers have been connected to the input matching networks (IMNs) and output matching networks (OMNs) of the two amplifier branches.

Figure 5.27: Circuit schematic of the balanced amplifier

Section 5.5 The balanced amplifier Chapter 5 Design process

60

Figure 5.28 shows the layout of the complete balanced amplifier. As shown in the figure, mitered conductor traces with a characteristic impedance of 50 have been connected between the Lange couplers and the input and output RF pads. The RF pads have been implemented with two metallization layers separated by an airbridge support pillar. To facilitate mounting of SMA-connectors, pedestals have been placed on each side of the pads. The 50- resistors terminated to the Lange couplers have been designed with a width of 407 m. A 50- resistor with smaller dimensions than the implemented resistor required an impedance transformer to minimize the discontinuity introduced at the interface of the Lange coupler. The additional length added by the impedance transformer reduced the performance of the balanced amplifier, since the phases of the reflected signals were changed in the 50- terminations. The dimensions of the complete balanced amplifier shown in Figure 5.28 are in m. To facilitate fabrication of the circuit, the saw marks at the corners of the amplifier have been placed 75 m outside the final chip area. Alignment marks, a test capacitor and a test resistor have also been added to the design since they are required during the fabrication. Since GMIC applications are fabricated in steps of 3 mm, the balanced amplifier was designed with the dimensions 9 x 9 mm. APPENDIX A contains the Microwave Office schematic of the balanced amplifier and APPENDIX B contains stress sheets for the active and passive elements.

Section 5.5 The balanced amplifier Chapter 5 Design process

61

Figure 5.28: The balanced amplifier

All simulated results for the balanced amplifier are presented in the next chapter.

62

63

6 Results The results presented in this chapter were achieved by simulating the complete balanced amplifier. All specified requirements given in the design specification have been simulated.

6.1 Simulations The results in this section have been accomplished by the transistor model used in the nominal design. Targets and simulated results for the amplifier requirements are also given in APPENDIX C.

6.1.1 Gain As shown in Figure 6.1, the gain requirements of the complete balanced amplifier have been satisfied. The gain variation is approximately ±0.3 dB within the frequency range; since the gain has its minimum of 8.4 dB at 8 GHz and its maximum of 8.9 dB at 11.4 GHz. At 12 GHz, the gain is 8.8 dB. The gain curve is almost identical to the gains of the single amplifier branches. Only a small decrease of approximately 0.2 dB was introduced by the Lange couplers.


S21

0

2

4

6

8

10

12

Tran

smis

sion

(dB

)

DB(|S(2,1)|)Balanced

Figure 6.1: Gain

Section 6.1 Simulations Chapter 6 Results

64

6.1.2 Noise Only a slight increase of the noise figure was obtained in the balanced amplifier when compared to the single branches. The noise increased from 2.1 dB at 8 GHz to 2.3 dB at 12 GHz, as shown in Figure 6.2. It is also shown that the curves for the noise figure and the minimum noise figure interact in the desired frequency range, i.e., no further noise reduction was possible to achieve.


Noise

0

1

2

3

4

5

Noi

se (d

B)

DB(NF())Balanced

DB(NFMin())Balanced

Figure 6.2: Noise figure

6.1.3 Stability In Figure 6.3, it can be seen that the unconditional stability requirements have been satisfied. It can also be seen that the stability have been improved by the balanced amplifier configuration when compared to one of the single branches.


65


Stability

-2

-1

0

1

2

3

4

5

Sta

bilit

y fa

ctor

s

B1()Balanced

K()Balanced

Figure 6.3: Stability factors

6.1.4 Reflections and reverse transmission The poor impedance matches of the single branches have been heavily reduced by introducing the Lange couplers in the design, as shown in Figure 6.4. The input reflection S11, reverse transmission S12 and output reflection S22 have magnitudes less than -22 dB, -24 dB and -28 dB respectively.


S11_S12_S22

-30

-25

-20

-15

-10

-5

0

Ref

lect

ion

(dB

)

-30

-25

-20

-15

-10

-5

0

Tran

smis

sion

(dB

)

DB(|S(1,1)|) (L)Balanced

DB(|S(1,2)|) (R)Balanced

DB(|S(2,2)|) (L)Balanced

Figure 6.4: S11, S12 and S22

In Figure 6.5 have S11 and S22 been represented in a Smith chart. As can be seen in the Smith chart, almost perfect 50- impedance matches were achieved on the input and output of the balanced amplifier.


66

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

S11_S22Swp Max

12GHz

Swp Min8GHz

S(1,1)Balanced

S(2,2)Balanced

Figure 6.5: S11 and S22 represented in Smith chart

6.1.5 1-dB compression point As shown in Figure 6.6, the output power has dropped 1 dB from the linear region when an input signal of 8.5 dBm at 12 GHz was applied. The 1-dB compression point at this amount of input power was determined to 14 dBm. Table 6.1 shows the 1-dB compression points for other frequencies. According to the design specification, the 1-dB compression point should be greater than 5 dBm. The amplifier accomplishes to deliver linear output powers up to approximately 13 dBm within the frequency range.

-10 0 10 20 25Input power (dBm)

1dB_compression

-10

0

10

20

30

Out

put p

ower

(dB

m)

-10

0

10

20

30

Pow

er g

ain

(dB

)

p2

p1

DB(|Pcomp(PORT_2,1)|)[5,X] (L, dBm)Balanced_nonlinear

DB(PGain(PORT_1,PORT_2))[5,X] (R)Balanced_nonlinear

Figure 6.6: 1-dB compression point and power gain at f = 12 GHz


67

Table 6.1: 1-dB compression points

Frequency (GHz) Pout, 1 dB (dBm) 8 12.7

10 13.3 12 14

6.1.6 Third-order output intercept point In Figure 6.7 have the output powers of the fundamental frequency and the third-order intermodulation product at 12 GHz been extrapolated in the linear region. The output power where the two lines intercept, i.e., the third-order output intercept point, was determined to 35 dBm. For other frequencies, the third-order output intercept points are given in Table 6.2.

Figure 6.7: Third-order output intercept point at f = 12 GHz

Table 6.2: Third-order output intercept points

Frequency (GHz) OIP3 (dBm) 8 32

10 33 12 35

6.2 Temperature behavior The gain of a GaAs FET decreases when the temperature is increased. Measurements on a fabricated GMIC LNA with two cascaded amplifier stages [ 13] have showed that the gain of the amplifier decreased with approximately -0.0125 dB/˚C. The transistors used in both amplifier stages were the Excelics EPA018A, i.e., the same transistor as in this master thesis work. Since the measured amplifier containing two cascaded stages, the

Section 6.2 Temperature behavior Chapter 6 Results

68

temperature behavior of a balanced amplifier with gain equal to one side of the coupler was estimated to -0.0125/2 = -0.00625 dB/˚C. Table 6.3 contains the estimated gain variations with respect to the temperature..

Table 6.3: Gain variations with respect to the temperature

Frequency (GHz)

S21 at T = -55 ˚C

(dB)

S21 at T = 25˚C

(dB)

S21 at T = 95 ˚C

(dB) 8 8.9 8.4 8.0

10 9.2 8.6 8.2 12 9.3 8.7 8.3

The maximum allowed gain deviation with respect to the temperature is, according to the design specification, required to be less than 2 dB. From the values in Table 6.3, it was found that the maximum deviation is approximately 1.3 dB within the frequency range.

6.3 Yield analysis To determine the scattering of the amplifier requirements given in the design specification when other transistor models were used and when the substrate tolerances were included, a yield analysis was made. The analysis was performed with the yield analysis function in Microwave Office. Uniform distribution was used on all variations and one hundred runs were used in each yield analysis, which was made with five different s-parameter files and with the nonlinear Curtice model. Three yield-runs were made. The first run tested unconditional stability on the balanced amplifier stage. The second run tested the other specifications on the amplifier stage. The third run tested the power requirements for the amplifier stage. Since only one of the s-parameter files contains noise parameters, yield analysis for the noise figure was never performed.

6.3.1 Table Table 6.4 contains the yield analysis results for the balanced amplifier requirements.

Table 6.4: Yield analysis

Variation Yield Goals Description Type No

Parameter Value Tolerance Parameter Value Comments

Yield [%]

Substrate thickness [um]

Relative dielectric constant

Resistivity [ohm/]

GMIC process related

GMIC

Capacitivity [pF/um^2]

Due to a non-disclosure agreement, values of these

parameters cannot be published.

These tolerances are used in yield-

analysis of the complete balanced amplifier

Section 6.3 Yield analysis Chapter 6 Results

69

Complete balanced

amplifier stage

Transistor model

Random change between five

linear s-parameter files

K

B1

>1

>0

Requirement for unconditional

stability

100%

S11 <-15 dB Input return loss 100%

S12 <-20 dB Reverse isolation 100%

S21 8.6±0.5 dB Gain 95%

S22 <-15 dB Output return loss

100%

EPA018A

NF <3 dB Noise figure Not Tested

Curtice model

Yield analysis only performed

with one nonlinear model

Variation of DC voltage

Vds 4V ± 0.2

K

B1

>1

>0

Requirement for unconditional

stability

100%

Pout, 1dB >5 dBm

1-dB compression

point at f=8Ghz

100%

Pout, 1dB >5 dBm 1-dB compression

point at f=10Ghz

100%

Pout, 1dB >5 dBm 1-dB compression

point at f=12Ghz

100%


70

IP3 >13 dBm third-order intercept point at

f=8Ghz

100%


f=10Ghz

100%


f=12Ghz

100%

As shown in Table 6.4, all of the specified requirements except S21 have a yield of 100 %. Since the scattering of S21 became significant at frequencies above 11 GHz, a yield of 100% was not possible to achieve.

6.3.2 Graphs The yield analysis results for the gain, stability, reverse isolation, input return loss and output return loss with respective yield goal are represented in graphs in this section. As shown in Figure 6.8, the scattering of S21 became significant at frequencies above 11 GHz. Only one combination of different s-parameter files resulted in a S21 curve with values located outside the required yield goal.


S21

0

2

4

6

8

10

12

Tran

smis

sion

(dB

)


Figure 6.8: S21, five linear models, 100 yield runs

Since the stability was improved by the balanced amplifier configuration, the amplifier remained unconditionally stable during the yield analysis. The yield analysis results when the linear and the non-linear models were used are shown in Figure 6.9 and in Figure 6.10 respectively.


71


Stability

-2

-1

0

1

2

3

4

5

Sta

bilit

y fa

ctor

s

B1()Balanced

K()Balanced

Figure 6.9: Stability factors, five linear models, 100 yield runs


Stability nonlinear model

-2

-1

0

1

2

3

4

5

Sta

bilit

y fa

ctor

s

B1()Balanced_nonlinear

K()Balanced_nonlinear

Figure 6.10: Stability factors, one nonlinear model, 100 yield runs

As shown in Figure 6.11, the reverse isolation remained almost constant for all sets of s-parameters during the yield analysis.


72


S12

-40

-30

-20

-10

0

Tran

smis

sion

(dB

)


Figure 6.11: S12, Reverse isolation, five linear models, 100 yield runs

As shown in Figure 6.12, the scattering of the input return loss became significant when different sets of s-parameters for the two transistors were used. The explanation of the scattering shown in Figure 6.12 is that the magnitude of the input return loss is, according to the theory chapter, proportional to the difference between S11 of the two amplifier branches. Since the input return loss for all combinations of s-parameter files are less than -15 dB within the frequency range, no modification of the design was needed. The required value S22 less than -15 dB within the frequency range were fulfilled with more than 8 dB for all sets of s-parameters, as shown in Figure 6.13.


S11

-50

-40

-30

-20

-10

0

10

Ref

lect

ion

(dB

)




73


S22

-60

-40

-20

0

20

Ref

lect

ion

(dB

)



74

75

7 Discussions The most critical parameter when designing the Lange couplers was the conductor spacing. A small conductor spacing, i.e., an increase of electrical coupling, resulted in a large bandwidth. The main drawback with small gaps was that the fluctuations of the transmissions S21 and S31 through the Lange coupler became too large. Simulations showed also that the phase difference between the two output ports of the Lange coupler was too poor when a small conductor spacing was used. As shown in the design process chapter, the Microwave Office and HFSS simulation results for an un-mitered microstrip line differ. The phase difference between the reflection coefficients when looking into the HFSS models of the un-mitered and optimal mitered grounded tune stubs with equal length was estimated to be 10˚. A phase difference of 10˚ results in a physical difference in length according to λ×°° 36010 . If the wavelength is estimated to be = 15 mm, the physical difference in length becomes approximately 0.4 mm. The extra length of 0.4 mm added by the un-mitered tune stub may degrade the performance of the amplifier when it is realized as hardware. When designing the spiral inductor, some interesting characteristics were studied. A small width of the conductor traces resulted in the option to achieve a high impedance peak. As shown in Figure 7.1, the impedance peak increases by approximately 1000 when the conductor width was reduced from 50 to 25 m. The spiral inductor with the width of 25 m was designed with 14 segments, a conductor spacing of 25 m and the outer dimensions 500 x 500 m. Due to the current ratings of the conductors, a spiral inductor with a width of 25 m could not be used in this thesis work.

Chapter 7 Discussions

76


Spiral inductor

0

500

1000

1500

2000

2500

Impe

danc

e (O

hm)

|ZIN(1)| (Ohm)W25

|ZIN(1)| (Ohm)W50

Figure 7.1: Input impedance of spiral inductors

Another characteristic studied was that the impedance peak was located at a higher frequency when the outer dimensions of the spiral inductor decrease. The same characteristic was obtained when the numbers of segments increased. As shown in the yield analysis section, the most critical element when designing the amplifier was the transistor model. The substrate tolerances were negligible compared to the scatterings caused by the transistor s-parameter files.

77

8 Conclusions The goal of this master thesis work was to design an approved broadband low-noise amplifier layout with the GMIC process adapted to Microwave Office. Since a functional design of a balanced amplifier has been produced using Microwave Office and was approved by M/A-COM, the goal for this project is reached. The approval done for manufacturability only verifies that the adaptation of the GMIC process to Microwave Office performed during the summer 2005 was successful. The main conclusion is that the design complies with all requirements in the design specification. Since the amplifier was designed as a balanced amplifier, excellent power handling capability was achieved. The design has been simulated thoroughly to show that it works as intended. Another important conclusion is that when designing microwave and RF systems, accurate modeling and parameter variations are crucial for a successful design.

78

79

9 Further work Suggested further work in this area is to investigate the performance of different amplifier architectures using the designed balanced amplifier. Two interesting architectures are first an amplifier with two cascaded balanced stages and second, the architecture shown in Figure 9.1.

Figure 9.1: Further work

80

81

References

[ 1] Guillermo Gonzalez, ”Microwave transistor amplifiers – analysis and design”, second edition, Prentice Hall, Upper Saddle River, 1997, ISBN 0-13-254335-4

[ 2] Reinhold Ludwig, Pavel Bretchko, ”RF circuit design – theory and applications”, international edition, Prentice Hall, Upper Saddle River, 2000, ISBN 0-13-122475-1

[ 3] Krister Andreasson, ”Mikrovågsteknik – 15 oscillator, 16 förstärkare”, andra upplagan, Sangus AB, 1989, Stockholm

[ 4] Rowan Gilmore, Les Besser, ”Practical RF circuit design for modern wireless systems - volume II: active circuits and systems”, Artech House, Norwood ,2003, ISBN 1-58053-522-4

[ 5] Behzad Razavi, ”RF microelectronics”, Prentice Hall, Upper Saddle River, 1998, ISBN 0-13-887571-5

[ 6] Krister Andreasson, ”Mikrovågsteknik – 5 Hybrider, 6 Effektdelare, 7 Ferriter, 8 Filter”, andra upplagan, Sangus AB, 1989, Stockholm

[ 7] Laura Christie, ”GMIC process overview”, Tyco Electronics UK Limited, M/A-COM Division, 2003-10-31

[ 8] Allan Buckle, Alan Paffard, ”GMIC – glass microwave integrated circuit, a wafer level technology for improved performance of microwave components and subsystems”, M/A-COM Ltd, ESA WPP-063, May 1993

[ 9] Rikard Eliasson, “Implementering av Tyco Electronics UK Limited GMIC-process till Microwave Office”, RT-R05:3034F, 2005-07-11

[ 10] Rikard Eliasson, ”Simulering av Langekopplare i HFSS från Ansoft”, RT-R05:3048F, 2005-09-21

[ 11] Excelics semiconductors, data sheet for the transistor EPA018A, http://www.excelics.com/p018a.pdf, accessed 21st September 2005

[ 12] Excelics semiconductors, large-signal model parameter for the transistor EPA018A, http://www.excelics.com/lsmval.pdf, accessed 22nd September 2005

[ 13] Björn Peterson, “OFFSET MWU Prototype test report LNA”, 3500500-469, version A.2005-04-15

82

83

APPENDIX A: Microwave Office schematics

ABPOSTID=ABPOST2

ABRIDGEID=TL1W=100 umL=204 um

1

2

3

4

MCROSSID=TL2W1=100 umW2=100 umW3=100 umW4=100 umMSUB=MSUB1

MLINID=TL3W=100 umL=100 umMSUB=MSUB1

MLINID=TL4W=100 umL=200 um



















1 2

3

MTEEID=TL23W1=100 umW2=100 umW3=100 umMSUB=MSUB1

1 2

3


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3


1 2

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3


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3


MTRACEID=X1W=100 umL=200 umBType=2M=0MSUB=MSUB1




PEDESTALID=PEDESTAL1W=150 umL=150 um

TFRID=TFR1

TFRID=TFR2

TFRID=TFR3

TFRID=TFR4

TFRID=TFR5

ABPOSTID=ABPOST8ABPOST

ID=ABPOST1

ABPOSTID=ABPOST7

ABPOSTID=ABPOST3

ABPOSTID=ABPOST6

ABPOSTID=ABPOST5

ABPOSTID=ABPOST9

To transistor source

Figure A.1: Resistor network


84

DCVSID=V1V=4 V




MLINID=TL4W=200 umL=461.885 umMSUB=MSUB1

MTAPERID=TL5W1=200 umW2=50 umL=300 umMSUB=MSUB1

1

2

3


1 2

3


1 2

3


1 2

3



TFCMID=TL10W=480 umL=480 um


MLEFID=TL12W=200 umL=2 umMSUB=MSUB1

x2

PROBPUNKTID=PROB1

MLINID=TL13W=200 umL=1113.529 umMSUB=MSUB1


MTRACEID=X2W=200 umL=2034.471 umBType=2M=0.5MSUB=MSUB1

x2

PROBPUNKTID=PROB2

x2PROBPUNKT

ID=PROB3



1

2

3

4


1

2

3

4MCROSSID=TL18W1=200 umW2=50 umW3=200 umW4=50 umMSUB=MSUB1









1

2

3






SUBCKTID=S1NET="spole_L575_N13_W50_0_22GHz"




DC supply to the upper transistor

DC supply to the lower transistor

RF signal from the upper transistor

RF signal from the lower transistor

Figure A.2: DC supply


85

1 2

3

MTEEID=TL3W1=W37 umW2=W37 umW3=W37 umMSUB=MSUB1

12

3


ABPOSTID=ABPOST1

MLINID=TL6W=W37 umL=26 umMSUB=MSUB1







12

3







1 2

3


12

3





1

2

3


1

2

3



MTRACEID=X2W=W37 umL=102 umBType=2M=0MSUB=MSUB1





MTRACEID=X3W=W37 umL=Ljord umBType=2M=0MSUB=MSUB1

1

2

3



1 2

3


ABRIDGEID=TL2W=W37 umL=171 um

ABPOSTID=ABPOST2

ABPOSTID=ABPOST3

ABPOSTID=ABPOST4

ABPOSTID=ABPOST5

ABPOSTID=ABPOST6

ABPOSTID=ABPOST7

ABPOSTID=ABPOST8

PORTP=1Z=50 Ohm

Figure A.3: Grounded tune stub

ABPOSTID=ABPOST10

ABRIDGE_GMICID=TL2W=100 umL=221 um



1

2

3

4


MLEFID=TL8W=W23 umL=250 um



MLINID=TL14W=200 umL=20 umMSUB=MSUB1MLIN

ID=TL15W=200 umL=200 umMSUB=MSUB1









MLINID=TL26W=W16 umL=L15 umMSUB=MSUB1







MLINID=TL45W=W23 umL=250 um




MTAPERID=MT1W1=W16 umW2=200 umL=300 umMSUB=MSUB1

MTAPERID=TL49W1=200 umW2=W26 umL=200 umMSUB=MSUB1

MTAPERID=TL50W1=W26 umW2=W29 umL=200 umMSUB=MSUB1MTAPER

ID=TL51W1=407 umW2=W16 umL=L22 umMSUB=MSUB1

MTAPERID=TL52W1=W29 umW2=407 umL=L34 umMSUB=MSUB1

MTAPERID=TL53W1=150 umW2=100 umL=150 umMSUB=MSUB1

1 2

3


1 2

3

MTEEID=TL57W1=W26 umW2=W26 umW3=50 umMSUB=MSUB1

12

3


1 2

3


MTRACEID=X1W=25 umL=980 umBType=2M=0


MTRACEID=X4W=W37 umL=Ljord umBType=2M=0MSUB=MSUB1




x2

PROBPUNKTID=PROB1

x2

PROBPUNKTID=PROB2

x2

PROBPUNKTID=PROB3

SHORTID=J1

SHORTID=J2

SHORTID=J3

SHORTID=J4

SHORTID=J5

SHORTID=J6

SHORTID=J7

SHORTID=J8





TFRID=TFR1

TFRID=TFR2

TFRID=TFR3

MTRACEID=X7W=W23 umL=Loppen umBType=3M=0MSUB=MSUB1

TFRID=TFR5

ABPOSTID=ABPOST1

ABPOSTID=ABPOST2

ABPOSTID=ABPOST3



1

2

3

SUBCKTID=S2NET=S15

1 2

SUBCKTID=S5NET="Bondpad"

1 2


W23=200

L15=179.4

L29=10.49

L34=407

W37=50

L37=719

W26=100

W29=406.3

W16=50

L22=407

L23=2499.57166228415

L183=34.57

Ljord=2000

Loppen=1622

DC supply

Resistor network

Grounded tune stub

Figure A.4: Matched amplifier branch


86

ABPOSTID=ABPOST1

ABPOSTID=ABPOST2

ABPOSTID=ABPOST3ABPOST

ID=ABPOST5

ABPOSTID=ABPOST6

ABPOSTID=ABPOST7

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ABRIDGE_GMICID=TL1W=W37 umL=171 um

ABRIDGE_GMICID=TL2

ABRIDGE_ GMICID=TL 7W=100 umL=2 21 u mEr=1



ABRIDGE_GMICID=TL14W=10 0 umL=204 um

DCVSID=V1V=4 V

1

2

3

4MCROSSID=TL 15W1=200 umW2=50 umW3=200 umW4=50 umMSUB=MSUB1

1

2

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1

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1

2

3

4

MCR OSSID=TL18W1 =100 umW2 =100 umW3 =100 umW4 =100 umMSUB=MSUB1

MLEFID=TL19W=W23 umL =250 um

ML EFID=TL2 1W=W2 3 umL=250 um

MLEFID=TL22W=2 00 u mL =2 umMSUB=MSU B1

MLINID=TL2 3W=200 umL=52 umMSUB=MSUB1


ML INID=TL2 5W=200 umL=52 umMSUB=MSUB1


MLINID=TL27W=2 00 u mL =52 um

ML INID=TL28W=200 umL=148 umMSUB=MSUB1




MLINID=TL32W=2 5 umL =100 umMSUB=MSU B1

ML INID=TL33W=25 umL=25 umMLIN

ID=TL34W=150 umL=50 um

MLINID=TL35W=20 0 umL=200 umMSUB=MSUB1

MLINID=TL 36W=50 umL=1 00 u m






MLINID=TL42W=W29 umL =L29 umMSUB=MSUB1

MLINID=TL43W=W37 umL =150 umMSUB=MSUB1





MLINID=TL48W=50 umL=100 0 umMSUB=MSUB1


MLINID=TL 50W=200 umL=2 00 u mMSU B=MSUB1

MLINID=TL51W=2 5 umL =100 umMSUB=MSUB1

MLINID=TL5 2W=25 umL=25 um


ML INID=TL5 4W=150 umL=50 um

MLINID=TL55W=5 0 umL =100 um


MLINID=TL 57W=W37 umL=5 umMSUB=MSUB1

ML INID=TL5 8W=W2 6 umL=100 umMSUB=MSUB1


MLINID =TL6 0W=W29 u mL=L2 9 umMSUB=MSUB1

MLINID=TL61W=W37 umL=5 u mMSUB=MSUB1

MLINID=TL 62W=50 umL=4 10 u mMSUB=MSUB1



MLINID=TL65W=50 u mL=415 umMSUB=MSUB1



MLINID =TL6 8W=W37 u mL=26 umMSUB=MSUB1


MLINID=TL70W=W37 umL =150 umMSUB=MSU B1

MLINID=TL71W=W37 umL =150 umMSUB=MSU B1











MLINID=TL82W=1 00 u mL =100 umMSUB=MSU B1

MLINID=TL 83W=100 umL=5 0 umMSUB=MSUB1



MLINID=TL8 6W=100 umL=28 5 umMSUB=MSUB1



MLINID=TL89W=1 00 u mL =50 umMSUB=MSUB1



















MLINID=TL108W=100 umL=50 u mMSUB=MSUB1


MLINID =TL1 10W=100 umL=50 umMSUB=MSUB1






MLINID=TL 116W=100 umL=2 10 u mMSUB=MSUB1





MLINID=TL121W=200 umL=461.9 u mMSUB=MSUB1





MLINID =TL1 26W=W37 u mL=15 0 umMSUB=MSUB1



MLINID =TL1 29W=100 umL=10 0 umMSUB=MSUB1

MLINID =TL1 30W=100 umL=12 00 u mMSUB=MSUB1



MLINID =TL1 33W=W37 u mL=25 0 umMSUB=MSUB1



MLINID=TL13 6W=W37 umL=250 umMSUB=MSUB1

MLINID=TL 137W=W37 umL=2 6 umMSU B=MSUB1




MLINID=TL 141W=W37 umL=5 umMSU B=MSUB1



MLINID=TL1 44W=W37 u mL=25 0 umMSUB=MSUB1



MLINID=TL 147W=W37 umL=2 50 u mMSU B=MSUB1

MLINID =TL1 48W=W37 u mL=26 umMSUB=MSUB1


MLINID=TL 150W=W37 umL=2 6 umMSUB=MSUB1

MLINID=TL1 51W=W37 u mL=15 0 umMSUB=MSUB1




ML INID=TL1 55W=W2 3 umL=250 um




MLINID =TL1 59W=W23 u mL=25 0 um

MLINID=TL 160W=W23 umL=2 50 u m

MLINID=TL161W=W23 umL =250 um


MTAPERID=TL 163W1=200 umW2=W26 umL=2 00 u mMSUB=MSUB1

MTAPERID=TL164W1=W26 umW2=W29 umL =200 umMSUB=MSUB1

MTAPERID=TL165W1=20 0 umW2=W26 umL=200 umMSUB=MSUB1

MTAPERID=TL166W1=W26 umW2=W29 umL=200 umMSUB=MSUB1MTAPER

ID=TL167W1=4 07 u mW2=W16 umL=L22 umMSUB=MSUB1

MTAPERID=TL16 8W1 =407 umW2 =W16 u mL=L22 umMSUB=MSUB1

MTAPERID=TL169W1=W29 umW2=40 7 umL=L34 umMSUB=MSUB1

MTAPERID =TL1 70W1=W29 umW2=407 umL=L3 4 umMSUB=MSUB1

MTAPERID=TL17 1W1 =150 umW2 =100 umL=150 umMSUB=MSUB1

MTAPERID=TL172W1=150 umW2=100 umL =150 umMSUB=MSU B1

MTAPERID=TL 173W1=200 umW2=50 umL=3 00 u mMSUB=MSUB1

12

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MTR ACEID=X4W=25 umL=191 umBType =2M=0


MTRACEID=X6W=407 umL=3 327 umBType=2M=0.25MSU B=MSUB1

MTRAC EID=X7W=1 00 u mL =200 umBTyp e=2M=0MSUB=MSUB1


MTRAC EID=X9W=1 00 u mL =200 umBTyp e=2M=0MSUB=MSUB1


MTRACEID=X1 1W=100 umL=200 umBTyp e=2M=0MSUB=MSUB1

MTRACEID=X12W=100 umL=20 0 umBType=2M=0MSUB=MSUB1

MTRACEID=X1 3W=100 umL=200 umBType=2M=0MSUB=MSUB1

MTRACEID=X1 4W=100 umL=200 umBTyp e=2M=0MSUB=MSUB1

MTRACEID=X1 5W=50 u mL=240 umBTyp e=2M=0MSUB=MSUB1

MTRACEID =X16W=50 umL=24 0 umBType=2M=0MSUB=MSUB1

MTRACEID=X17W=100 umL=2 00 u mBType=2M=0MSUB=MSUB1

MTRACEID=X18W=100 umL=20 0 umBType=2M=0MSUB=MSUB1

MTRACEID=X19W=10 0 umL=200 umBType =2M=0MSUB=MSUB1

MTRACEID=X20W=1 00 u mL =200 umBTyp e=2M=0MSUB=MSU B1

MTR ACEID=X21W=20 0 umL=2034 umBType =2M=0.5MSUB=MSUB1


MTRACEID =X23W=25 umL=10 0 umBType=2M=0MSUB=MSUB1


PEDESTALID =PEDESTAL2W=150 umL=15 0 um


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x2

PROBPUNKTID=PROB1

x2

PR OBPUNKTID=PR OB2

x2

PR OBPUNKTID=PR OB3

x2

PROBPUNKTID=PROB4

x2

PROBPUNKTID=PROB5

x2

PROBPUNKTID =PROB6

x2

PROBPUNKTID=PROB7

x2

PROBPUNKTID=PROB8

x2PROBPUNKT

ID=PROB9

SHORTID=J1

SHORTID=J2

SHORTID=J3

SH ORTID=J4

SHORTID=J5

SH ORTID=J6

SH ORTID=J7

SHORTID=J8

SHORTID=J9

SHORTID=J10

SHORTID=J11

SHORTID=J12

SH ORTID=J13

SHORTID=J14

SHORTID =J15

SHORTID=J16

TFCMID=TL203W=2 00 u mL =200 um

TFCMID=TL 204W=200 umL=2 00 u m

TFCMID=TL2 05W=200 umL=20 0 um

TFCMID =TL2 06W=200 umL=20 0 um

TFC MID=TL207W=150 umL=150 umMSUB=MSUB1


TFCMID=TL209W=1 50 u mL =150 um



TFCMID=TL2 12W=480 umL=48 0 um

TFCMID=TL213W=1 87 u m

TFCMID=TL21 4W=480 umL=480 um

TFCMID=TL21 5W=187 umL=187 um

TFRID=TFR1

TFRID=TFR2

TFRID=TFR3

TFRID=TFR4

TFRID=TFR5

TFRID =TFR6

TFRID=TFR7

TFRID=TFR8

TFRID=TFR9

TFRID=TFR10

TFRID=TFR11

TFRID=TFR12

TFRID=TFR13

TFRID=TFR14

TFRID=TFR15MSUB=MSUB1

TFRID=TFR16

TFRID=TFR17

1

2

3

MTEEID=TL2 16W1=W37 umW2=W37 umW3=W37 umMSUB=MSUB1

MTAPERID=MT1W1=W16 umW2=200 umL=300 umMSUB=MSUB1

MTAPERID=MT2W1=W16 umW2=20 0 umL=300 umMSUB=MSUB1

1

2

3

MTEEID=TL2 17W1=W37 umW2=W37 umW3=W37 umMSUB=MSUB1

1 2

3


1

2

3

MTEEID=TL2 19W1 =W37 u mW2 =W37 u mW3 =W37 u mMSUB=MSUB1

1 2

3

MTEEID=TL22 0W1=W3 7 umW2=W3 7 umW3=W3 7 umMSUB=MSUB1

1

2

3


1 2

3

MTEEID =TL2 22W1=W37 umW2=W37 umW3=W37 umMSUB=MSUB1

12

3

MTEEID=TL22 3W1=W3 7 umW2=W3 7 umW3=W3 7 umMSUB=MSUB1

1 2

3

MTEEID=TL2 24W1 =W37 u mW2 =W37 u mW3 =W37 u mMSUB=MSUB1 1

2

3

MTEEID=TL 225W1=W37 umW2=W37 umW3=W37 umMSU B=MSUB1

1 2

3


1 2

3


12

3

MTEEID =TL2 28W1=W37 umW2=W37 umW3=W37 umMSUB=MSUB1

12

3


MTRACEID=X24W=4 07 u mL =3491 umBTyp e=2M=0 .25MSUB=MSU B1

MTRACEID=X25W=W37 umL=1 02 u mBType=2M=0MSU B=MSUB1

MTRACEID=X26W=W3 7 umL=Ljord umBType=2M=0MSUB=MSUB1

MTRACEID=X27W=W3 7 umL=Ljord u mBType=2M=0MSUB=MSUB1

MTRACEID=X2 8W=W37 umL=102 umBType=2M=0MSUB=MSUB1

MTRACEID=X29W=W2 3 umL=Lop pen umBType=3M=0MSUB=MSUB1

MTRACEID=X30W=W23 umL=Loppen umBType =3M=0MSUB=MSUB1


PEDESTALID=PEDESTAL7W=1 40 u mL =140 um




PEDESTALID=PEDESTAL1 1W=407 umL=4 07 u m

TFRID=TFR18

TFRID=TFR19MSU B=MSUB1

TFRID=TFR20

ABRIDGE_GMICID=TL3W=100 umL=221 umEr=1

ABRIDGE_GMICID=TL4W=10 0 umL=221 umEr=1

ABPOSTID=ABPOST18

ABPOSTID=ABPOST19

ABPOSTID=ABPOST20

ABPOSTID =ABPOST21

ABPOSTID=ABPOST22

ABPOSTID =ABPOST23

ABPOSTID=ABPOST2 4

ABPOSTID=ABPOST37

ABPOSTID=ABPOST38

ABPOSTID=ABPOST39

ABRIDGE_GMICID=TL5W=1 00 u mL =221 um

ABRID GE_GMICID=TL6W=100 umL=221 um

ABPOSTID=ABPOST4

ABPOSTID=ABPOST1 0

ABPOSTID=ABPOST12

ABPOSTID=ABPOST13

ABPOSTID=ABPOST1 4

ABPOSTID=ABPOST15

ABPOSTID=ABPOST16

ABPOSTID=ABPOST25

ABPOSTID=ABPOST27

ABPOSTID =ABPOST28

ABPOSTID=ABPOST29

ABPOSTID =ABPOST30

ABPOSTID=ABPOST31

ABPOSTID=ABPOST3 2

1 2

34

SUBCKTID=S1N ET="Lan ge_4638_ 50Ohm_W50_s20"

1

2

3

SUBCKTID=S2NET=S16

12

3 4

SU BCKTID=S3NET="L ange_463 8_50Ohm_W50_ s2 0"

1

2

3

SUBCKTID=S4NET=S15

SUBCKTID=S5NET="spole _L575_N 13_W50_0_22GHz"

SUBCKTID=S6NET="spole _L575_N 13_W50_0_22GHz"

SUBCKTID=S7NET="spole_L 575_N13_ W50_ 0_22GHz"

SUBCKTID=S8NET="spole _L575_N1 3_W5 0_0_22GHz"

1 2

SUBCKTID=S9NET="Bondpad "

1 2


1 2

SUBCKTID=S11NET="Bond pad"

1 2

SU BCKTID=S1 2NET="Bond pad"

12

SUBCKTID=S13NET="RF_ pad"

1 2

SU BCKTID=S1 4NET="RF_pad"

POR TP=1Z=50 Ohm

PORTP=2Z=5 0 Ohm

W23=200

L15=179.4

L 29=10.49

L3 4=407

W37=50

L37=719

W26=100

W29=4 06.3

W16=50L22=407

L 23=249 9.57 16622841 5

L183=3 4.57

Ljo rd =2000

L oppen=1622

Figure A.5: Balanced amplifier stage

87

APPENDIX B: Stress sheets

Table B.1: Active component stress sheet Current [mA] Power [dBm] Voltage [V] Temperature [ºC] Description Type No

operated rated operated rated operated rated RF&DC

Power Dissipation coefficient

Therm res

[ºC/W]

Calculated

(Ta=+95ºC)

Comments

FET

EPA018A: Vds

4 < 6 upper stage

EPA018A: Vgs

-0.47 > -3

EPA018A: Ids

25 < 55

EPA018A: Igfs

-0.0006 < 1.5

EPA018A: Pin

17 20 185 104.3 Max 150ºC

FET EPA018A: Vds

4 < 6 lower stage

EPA018A: Vgs

-0.47 > -3

EPA018A: Ids

25 < 55

EPA018A: Igfs

-0.0006 < 1.5

EPA018A: Pin

17 20 185 104.3 Max 150ºC

Table B.2: Capacitor stress sheet Voltage Description Type No. Drawing No. Circuit Ref Value

[pF] Operated Rated

Comments

All capacitors

4.725 – 48.38

< 8 50

APPENDIX B: Stress sheets

88

Table B.3: Resistor stress sheet Voltage [V] Power [mW] Description Type No. Drawing

No. Circuit

Ref Value []

Operated Rated Operated Rated

Comments

Lower stage

Nominal bias TFR1 18.9 0.47 11.7 39.4

Output stability

shunt

TFR2 100.1 <40 49.4

Output stability series

TFR3 5.95 <20 30.0

Input stability 1 of 2

TFR23 210 3*10-4 0 44.8


TFR24 280 3*10-4 0 57.6

Upper stage

Nominal bias TFR5 18.9 0.47 11.7 39.4

Output stability

shunt

TFR6 100.1 <40 49.4

Output stability series

TFR7 5.95 <20 30.0


TFR21 210 3*10-4 0 44.8


TFR22 280 3*10-4 0 57.6

Lange coupler input

TFR14 50 <100 253.0

Lange coupler output

TFR19 50 <20 253.0

89

APPENDIX C: Targets/simulations The simulated results in Table C.1 have been accomplished by using nominal process parameters.

Table C.1: Targets/simulations

Parameter Target Simulated Comments Supply voltage +4 V +4 V Unipolar supply

voltage Current consumption

< 50 mA 50 mA

Frequency range 8 – 12 GHz 8 – 12 GHz The X-band

Gain variation within frequency range

±1 dB ±0.3 dB

S11 < -15 dB < -22 dB Input reflection

S21 > 8 dB > 8.4 dB Forward transmission

S12 < -20 dB < -24 dB Reverse transmission

S22 < -15 dB < -28 dB Output reflection

NF < 3 dB < 2.3 dB Noise figure

Pout, 1 dB > 5 dBm > 12.7 dBm 1-dB compression point

OIP3 > 13 dBm > 32 dBm Third-order output intercept point

Temperature range -55 – 95 ˚C -55 – 95 ˚C

Gain variation within temperature range

< 2 dB

1.3 dB

Mechanical length 9 mm 9 mm

K B1

> 1 > 0

> 2.9 > 0.2

Requirement for unconditional stability

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