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DESIGN OF A DIGITAL FRONT-END TRANSMITTER FOR OFDM-WLAN SYSTEMS USING FPGA

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  • 7/27/2019 DESIGN OF A DIGITAL FRONT-END TRANSMITTER FOR OFDM-WLAN SYSTEMS USING FPGA

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    DESIGN OF A DIGITAL FRONT-END TRANSMITTER FO R OFDM-WLANSYSTEMS USING FPGAM a osk Canet', Felip Vicedo', Javier Valls'. Vicenq Almenar3

    ' Dpto. Electronica, Universitat Politecnica de Valkncia, Gandia, Spain* Dpto. Fisica y Arquitectura Computadores, Universitat Miguel Hernandez, Elche, SpainDpto. Comunicaciones, Universitat Politecnica de Valencia, Gandia, Spaine-mail: [email protected]

    ABSTRACTThis paper deals with the implementation issues of adigital transmitter for OFDM based WLAN systems. Weexplore different solutions for signal generation inbaseband and in intermediate frequency taking intoaccount the effect of the analog conversion in the overallperformance. In order to minimize distortion of the cyclicprefix a new interpolation filter structure valid for OFDMsignals is presented. Finally, the cost in area for FPGAimplementation of every needed circuit is given.

    1. INTRODUCTIONNew WLAN standards in the 5 GH z band (HiperLAN 2and IEEE 802.11a) and in the 2.4 GHz band(IEEE 802.1 lg ) are based on Orthogonal FrequencyDivision Multiplexing (OFDM) transmission [1,2,3].They have been designed to provide data rates up to54 Mbps in order to support broadband multimediacommunications.Orthogonal Frequency Division Multiplexing(OFDM) has been selected as the modulation scheme dueto its good performance on highly dispersive channels,like the indoor scenarios where these standards will beused. The baseband signal can be easily generated using a64-IFFT, and then a guard interval (also called cyclicprefix) using the last 16 samples must be added to makethe system robust to multipath. Since the frequencysampling is 20 MHz, each symbol is 4 ps length (80samples), including a guard interval of 800ns. Tofacilitate implementation of filters and to achievesufficient adjacent channel suppression, only 52subcarriers are used: 48 are data carriers (withmodulations types from BPSK to 64-QAM) and 4 arepilots for phase tracking. This makes that subcarrierspacing is 312.5 kHz, and spacing between two outmostsubcarriers is 16.25 MHz. That is, in baseband, the highercarrier is centred at 8.125 MHz.

    In this paper we present the study and implementationof different solutions for OFDM signal generation in adigital front-end. We give alternatives for systems whosedigital part works until baseband or until intermediatefrequency (IF). Although this study has been carried outfor the design of a HiperLAN 2 (HL/2) transceiver onFPGA [4], it can be extended to the rest of OFDM basedWLAN standards.The paper is structured as follows. In this sectionmain characteristics of OFDM based WLAN systems hasbeen commented. Section 2 describes the transmittersubsystem where solutions for OFDM signal generation inbaseband and in IF are presented. Finally, in section 3some conclusions are stated. In section 2 it is describedthe implementation in FPGA of those necessary circuits.For this implementation we have used Virtex familydevices from Xilinx. Moreover, to benchmark ourdesigns, in each circuit we compare the area employed byit to that needed by Xilinx's tool Svstem Generator [5].

    2. TRANSMITTERAs it was commented above the OFDM signal can begenerated at a rate of 2 0 MHz by a 64-point IFFT and theaddition of a cy clic prefix of 16 samples. After this digitalsignal processing, sam ples must be converted to an analogsignal, in this section we discuss three different solutions.The first one is the most straightforward manner, itconsist in connecting two D/A converters (DAC) to bothphase and quadrature branches working at a rate of20 MH z. As we w ill see in subsection 2.1, although thissolution is the one which makes use of fewer resources inthe digital part, it causes a higher degradation in thegenerated signal that can only be compensated in part.The second solution is set out to solve those problemscommented above, this works also in baseband, andconsists in interpolating the OFDM signal from a rate of20 MHz to 40 MHz, in subsection 2.2 we propose a newfilter structure that performs the interpolation processwithout introducing inter-symbol interference (ISI).

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    Finally, subsection 2 .3 describes a possible solution fordigital IF signal generation.2.1. Baseband signal generation at 20 MHzIn this section we consider that the phase and quadratureoutputs are directly connected to the DAC. As it wasstated in the introduction, in order to facilitate theimplementation of filters, only 52 subcarriers areemployed: DC subcarrier and those in the higherfrequencies are set to zero. So, the highest frequencysubcarrier is centered at 8.125 MHz.In this solution there are two sources of distortion: theDAC, and the reconstruction analog filters. The first oneha s a frequency response with the well known sin(x)/xshape: due to this amplitude distortion the highestsubcarrier suffers from an attenuation of 2.5 dB respect tothe lowest one. At a first glance, it can be assumed thatthis attenuation can be compensated with other channeldistortions by receiver's equalizer. However, as can beseen in Figure 1 , this solution (dash dotted line) degradesthe performance of the system: a loss of more than 1 dB ata bit error rate (BER) of lo4 . So , to avoid this degradationit is necessary to pre-equalize this amplitude distortion inthe transmitter (dotted line in Figure 1).Pre-equalization can be performed in the transmitterat a higher implementation cost. Good performance isobtained (dotted line in Figure 1) if subcarriers attenuated1 dB or m ore by the DAC a re amplified before the IFFT.This amplification can be done by multiplication or byadjusting the look-up table used in the subcarriermapping. This last option consumes less FPGA resources.In both cases one bit more is needed to quantize the IFFTinput signal due to signal amplification: in a normaltransmitter 6 bits are enough [4].The second source of distortion comes from analogreconstruction filtering. In an OFDM system a cyclicprefix is employed to prevent ISI, so its length must beequal or higher than the length of the significant part ofthe channel impulse response [6]. In a real system the totalchannel impulse response, not only comes from themultipath channel, but also from all transmit and receivefilters. To check this effect a Butterworth analog filter hasbeen designed with specifications that minimize distortionin the passband signal and attenuate the spectrum imagesgenerated by the D/A reconstruction process. Thepassband ripple is fixed as 0.5 dB at 8.5 MHz (the highersubcarrier is centered at 8.125 MHz). The beginning ofthe stopband is set at 11.5 MHz since at 20 MH z the firstimage can be found. To calculate the attenuation at thispoint we take into account both the attenuation given bythe DAC (5.5 dB at 11.5 MH z), and the specifications o fthe transmission spectrum mask [11 that must be fulfilledby the output signal. Therefore, this value is fixed at 25dB. With these specifications a 12'h order Buttenvorthfilter is needed. We have checked the contamination of

    the cyc lic prefix due to this filter, obtaining that more than20 0 ns (4 samples) are distorted by the ana log filter.l o l ................. ............................................................................................... -................................... I ldeaisignal tj

    CflFig. 1.channel A for d ifferent transmitter configurationsPerformance of an HL/2 system in a multipath

    Next, as an example, we show what could happen ina HL/2 system whose standard sets as optional the use of ashort cyclic prefix of 8 sam ples (400 ns). In figure 1it isshown the performance of an HL/2 system (solid line withcircles) through a multipath channel model A (50 ns rmsdelay spread [7], this is a typical NLOS office buildingenvironm ent) when a 12'h orde r Butterworth filter is used.It can be seen that IS1 degrades the performance of thesystem since the total channel impulse response (theconvolution of the multipath channel with the transmitterfilter impulse response) is larger than the short prefix(40011s). In this examp le an ideal OFDM rece iver isassume d, therefore, in a real case, receiver front end filters(analog and digital) would increase the total distortion.2.2. Baseband signal generation at 40 MHzDespite leaving in the standards some subcarriers unusedto simplify the conversion to the analog domain, we haveseen that working at a sampling frequency of 2 0 MH zintroduces two problems: amplitude attenuation in somesubcarriers due to the DAC, and a degradation of morethan 20011s in the cyclic prefix due to the high o rderanalog reconstruction filters employed.An obvious solution for both problems is to use ahigher sample rate in the digital to analog conversion.However, this solution has a cost in the digital domain:more area will be employed to implement the necessaryinterpolation circuits, and there will be more powerconsumption due to the extra circuitry and the use ofhigher rate D/A converters.

    We have confirmed by simulation and experimentalresults that both distortions can be settled using a samplerate of only 40 MHz, and that there is no benefit in using ahigher frequency as in [8],where a sample rate of 80 M Hzis employed. Now the DAC attenuation at the higher

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    subcarrier is less than 0.6 dB (compared to 2.5 dB in theprevious case) and it is no longer necessary to pre-equalize. This simplifies the design of the transmitter.Moreover, first image appears centered at 40 MHz,therefore filter specifications can be relaxed: the stopbandbegins at 3 1.5 MHz and only 2 0 dB of attenuation a renecessary thanks to a DAC attenuation of more than12 dB. Only a 31d order B utterwo rth filter is needed ,whose impulse response distorts less than 50 ns (1sample). At a higher rate like 8 0 MHz the order of thefilter is the same, so the analog design is not simplified atthe expense of a higher complexity in the digital part.There are tw o ways of generating an interpolated bytwo OFDM signal: using an 128-IFFT or using aninterpolation filter. The digital filter option has the samedrawback as the previous analog filter: it shortens thesafeguard part from the cyclic prefix. Its im pulse responseconvolves with those of th e dispersive channel and analogfilters in the transceiver chain. So, IS1 can appear if thetotal impulse response is larger than the cyclic prefix.On the other hand, the 128-IFFT option generates anundistorted OFDM signal since in this case the cyclicprefix is generated copying the last 32 samples of theIFFT output. The main drawback of this solution is that an128-IFFT needs more than twice the area of a 64-FFT [9].In order to use as less as possible area in theinterpolation process we have designed a new filterstructure that interpolates each OFD M symbol using onlysamples from that sym bol, preventing in this w ay IS1 fromhappening. As this new structure takes into account theperiodicity of the OFDM signal, we have named this ascircular interpo lation filter.

    2.2.1. Circular interpolation f i l ter s tructureTo interpolate by 2, the first step is to design the halfbandfilter impulse response. We have used next filterspecifications: a passband distortion of less than 1%(0.17dB of ripple), a stopband attenuation of more than20 dB (due to spectrum transmission mask), and an oddnumber of coefficients (this makes that in a halfband filterhalf the coefficients are zero). An equiripple filter designof 241h order (25 coefficients) m eets the req uiremen ts (thisfilter has a passband ripple of 0.14 dB and a stopbandattenuation of 41 dB).In a conventional interpolation structure this filterwould be placed after the cyclic prefix generation block inthe transmitter chain. But, as we commented previously,in an OFDM signal this filtering would distort the guardinterval because the first 24 samples from the interpolatedguard interval are generated using samples from aprevious sym bol, destroying in this way the periodicity atthe beginning of the cyclic prefix [9].The proposed interpolation structure goes directly afterthe FFT output and, besides interpolating the OFDMsignal, it also generates the cyclic prefix. The main idea

    behind this structure is to calculate the interpolatedsamples making use of samples from the present OFDMsymbol: this preserves periodicity in the cyclic prefix.Figure 2 shows the hardware realization of this structure,an d Figure 3 shows those signals involved. 64 samplesfrom the FFT (named from 0 to 63) are stored in a dualport RAM, these samples are passed to the polyphasehalfband interpolator filter which gives 128 samples, 32of them are stored in a FIF O for cyclic prefix generation.

    addr-A

    4 2 MUXFIFORAMCountermod 64Fig. 2 HW realization of circular interpolation filter

    memory Ifull I I

    symbol 1 symbol 2Fig. 3 Control signals and number of output samplesInterpolation process begins when the RAM is filledwith 64 samp les from the FFT process: this is indicated bycontrol signal memo ry ul l . In this structure, the 32 cyclicprefix samples are generated first and stored in a FIFO to

    be read at the end, completing in this way the OFDMsymbol generation. So, the first sample to be passed fromthe RAM to the interpolation filter should be sample 48(the first sample of the cyclic prefix). But to cope withfilter delay (12 interpolated samples in our design) thefirst read sample must be 42 instead of 48 (6 samplesdelay before interpolation). As can be seen in Figure 3,this value is used to initialize the modulus 64 counter thataddresses the RAM. Then, after 24 output-clock cyclesmore, the filter output is valid: from this moment the filterregisters are filled only by samples of the present O FDMsymbol. Next, during 32 output-clock cycles, as can beseen in Figure 2 and 3, MUX output (controlled by signals e l ) is read from filter output, and FIFO (controlled bysignals we and r e ) begins to be filled with the first 32samples, then w e is deactivated. After 96 output-clockcycles more, 128 interpolated samples have beengenerated, and signals re an d se1 are activated to readsamples stored at the FIFO. Filter continues workingalthough its output is not used. 8 output-clock cycles later,

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    m e m o y j i l l is again activated and the process starts againfilling the filter with the next OFDM symbol samples.Let us see the implementation cost of this structure.The FIR filter employs a polyphase structure and makesuse of symmetries in filter coefficients; it has beenimplemented using distributed arithmetic. Fixed pointprecision has been evaluated [4] and only 8 bits arenecessary both for the OFDM signal and for coefficients.To reduce the use of HW resources polyphase subfilterswork serially; so, the minimum clock frequency is20.8 = 120 MHz, which can be achieved by Virtex-Efamily devices. Our final design needs 46 FPGA slices perbranch, whereas the same design done using SystemG e n e r a t o r needs 155 slices per branch.The control circuits (which work over both filterbranches) of the circular filter make use of 62 slices in anoptimized VHDL implementation, and 97 slices whenSystem Generator is employed. In both cases the FIFOcan be implemented using one BSRAM from the FPGA.To sum marize, our design makes use of 154 slices andone BSRAM , whereas Sys tem Genera to r implementationneeds 407 slices and one BSRAM .2.3. Digital IF signal generationIn this section we will deal with signal generation atintermediate frequency by digital means. This lastalternative could be employed in a Software DefinedRadio solution of a multistandard access point. Here, as anexample, an intermediate frequency of 70 MHz has beenused since, apart from being a common IF, it allows us toshow how FPGA can be employed in a high speedimplementation.To comply with Nyquist sampling theorem, outputsampling frequency must be 160 MH z or higher. So, toachieve a compromise between digital and analogimplementation costs we have chosen a sampling rate of200 MH z. In this case, an interpolation factor of 10 isneeded; this can be done in two steps: the first one by 2(using the scheme described in section 2.2) and the secondone by 5. This second stage can be done using a FIR filterof 14h order (p assband distortion lower than 1% andstopband attenuation greater than 30 dB).At a rate of200MHz, this filter is so short compared to the cyclicprefix th at distorts less than 80 ns. For this reason in thiscase the circular structure is not necessary.This filter has been implemented using a polyphasestructure and distributed arithmetic. To achieve theneeded throughput a digit-serial approach has beenemployed with a digit size of 2 bits. Coefficients arequantized with 8 bits. In this case our design employs 109slices, meanwhile Sys tem Genera to r implementationneeds 281 slices.The last circuit in the digital domain is the quadraturemixer. Here, a CORD IC operator has been employed [101.This approach saves area compared to schemes using a

    table based DDS (Direct Digital Synthesis) and a complexmultiplier. So, the CORDIC modulator makes use of 189slices in the FPGA, meanwhile the DDS solution usingSys tem Genera to r needs 271 slices.In the analog domain, OFDM signal centred at70 MH z is distorted by the DA C. In this case attenuationbetween higher and lower subcarriers is less than 0.8 dB ,which can be seen from the central subcarrier as anattenuation of 0.4 dB for the highest subcarrier, and a gainof 0.4 dB for the lowest subcarrier. These values are lowenough to be compensated by the receiver withoutperformance degradation. As regards the analog filter, inthis case a 3rd order bandpass Buttenvorth filter canattenuate the signal image centred at 1 30 MH z distortingonly less than 9 0 ns of the cyclic prefix.

    4. CONCLUSIONSThis paper shows that an OFDM signal for WLANsystems can be generated in baseband at a rate of 40 MHzwith low distortion in the analog reconstruction. Forinterpolation a new filter structure, called circular filter,has been proposed, this new structure does not distort thecyclic prefix as a normal filter would do. Generation inintermediate frequency, which could be used in aSoftware Defined Radio implementation, has also beendiscussed. Finally, we have given implementation cost onFPGA for every circuit, comparing our optimizedimplementation with that given by Xilinxs Sys temGenera to r

    5. ACKNOWLEDGEMENTSThis work was supported by the Ministerio de Cicencia yTecnologia under Research Project TIC2001-2688-CO3 and inpart by the Universitat Politecnica de Valencia.

    6 .REFERENCES[ l ] ETSI TS 101475v1.2.2, BroadbandRadio A ccess Networks(BRAN): HIPERLAN Type 2; Physical (PHY) layer, Sep. 2002[2] IEEE 802.1 la: Wireless LAN specifications: High-speedPhysical Layer in the 5 GHz[3] IEEE 802.1 lg: Wireless LAN spec ification s: Further HigherData Rate Extension in the 2.4 G Hz Band[4] F. Vicedo, M. Canet, J. Valls, and V. Almenar, FPGAdesign of an OFDM transceiver for HiperLAN 2, XIII SpanishURSI symposium, La Corufia, Spa in, Sep. 2003[5] Xilinx System Generator for DSP v2.2Reference Gu ide[6] R. Van Nee and R. Prasad, OFDM fo r Wireless MultimediaCommunications,Artech House, Lond on, 2002[7] J. Medbo et al., Channel Models for HIPERLAN 2, ETSIBRAN document number 3ERI085B, 1998[SI E. Grass et al., On the Sing le-Ch ip Implementation of aHiperlan 2 and IEEE 802.1 1a Capable Modem, IEEE PersonalCommunications,Dec. 2002[9] M. Faulker, The effect of filtering on the performance ofOFDM systems, IEEE Trans. on Veh. Tech., Sep. 2002[lo] F. Cardells, and J. Valls, High Performance QuadratureDigital Mixers for FPGA, FPL2002, Monpelier, France, 2002

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