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Design of a Dynamic On-Wafer High-Power I-V Characterization Setup for Power Semiconductor Devices Master/Semester Thesis (FS 2021) a) b) Fig. 1: a) Picture of the APS Curve tracer prototype used for high-current pulsed IV characterization, b) section of the wafer prober showing the inlet of the wafer chamber equipped with micro-manipulators and the microscope. Introduction The current-voltage (IV) characteristics of Power MOSFETs are typically measured by current-voltage (I-V) pulses using commercial parametric curve tracers (PCTs). At higher power ratings the duration of these pulses must be short enough to avoid self-heating of the devices, which would significantly distort the mea- surement results. Yet, during on-level high-current measurements the minimal pulse width is limited by the parasitic inductance of the cables, which are needed to connect to the device terminals (see grey and orange cables in Fig. 1b). To minimize the time required to magnetize this parasitic inductance an ultra-compact on-wafer dynamic characterization setup is required, which is directly placed on top of the wafer chamber and connected with needles to the pads of the semiconductor device under test. Scope of the Thesis The aim of this semester thesis is to revise the existing APS curve tracer depicted in Fig 1a and design a dynamic on-wafer high-power I-V setup. In addition, an already existing Matlab interface is to be extended to allow fully automated measurements. The work to be performed in the scope of this thesis can be divided in the following topics: • Testing of the existing prototype (10 %). • Design of the dynamic on-wafer I-V characterization setup (70 %). • Programming of the control interface (20 %). Contact For more details please contact: Supervisors: Roger Stark [email protected] ETL F 24.1 Professor: Prof. Dr. U. Grossner [email protected] ETL F 28
