Research presentation at the International Conference on Computer Science and Mechanical Engineering (IRAJ) in Pune in December 2013.
21
by: Nirav Desai. Work done as a student at University of Minnesota T • An effort is made to reduce dynamic and static power dissipation of static CMOS in this project. Introduction: • 16 bit arithmetic units are mainly found in microcontroller applications where speed is important from real-time constraints and low power methodologies dominate system design. • Static CMOS which has been traditionally used for digital logic design has become unattractive at advanced technology nodes due to high static and dynamic power dissipation. 1 • Design techniques using static CMOS such as Logical Effort have been developed that give the best delay for a logic chain.
Transcript
Prepared by: Nirav Desai. Work done as a student at University of Minnesota Twin Cities
• An effort is made to reduce dynamic and static power dissipation of static CMOS in this project.
Introduction:
• 16 bit arithmetic units are mainly found in microcontroller applications where speed isimportant from real-time constraints and low power methodologies dominate system design.
• Static CMOS which has been traditionally used for digital logic design has becomeunattractive at advanced technology nodes due to high static and dynamic power dissipation.1
• Design techniques using static CMOS such as Logical Effort have been developed thatgive the best delay for a logic chain.
Brent Kung Adder Transistor Level Design
Inverter Design Optimization
• NMOS Width = 90nm• PMOS / NMOS Length = 50nM• Vdd = 1.1V• Current Averaged Over One Period of 2 ns• Optimal PMOS Width = 165nM• βinverter = 165/90 = 1.834• Sizing for NAND, NOR and XOR Changed appropriately120 140 160 180 200 220 240 260 280 300
40
50
60
70
80
90
100
110
PMOS Width (nM)
TD*I
avg
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
VDD
Vin Vout
CL
Design Equations for Brent Kung AdderGi = Ai AND Bi … (1)Pi = Ai XOR Bi … (2)Gi
1=Gi + Pi AND Gi-1 … (3)Pi
1=Pi AND Pi-1 … (4)
Brent Kung Adder Gate Level Diagram
1. Input Block with Pre Computation
Input Adder Chain 1
Input Adder Chain 2
Input Adder Chain 3
Input Adder Chain 4
1X
1X
1X
1X
1.224X
1.562X
1.23X
1.274X
1.097X
1.553X
1.108X
1.034X
3.883X
3.043X
2.943X
10.1683X
10.8506X
36X
40X
Output Buffers to driveCapacitive Loads
Output Buffers to driveCapacitive Loads
Pi*Pi-1
Gi + Pi*Gi-1
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Gate Level Diagram
2. Intermediate Dot Product Blocks
Intermediate Adder Chain 1
Intermediate Adder Chain 21X
1X
1X
1X
1.72X
6X
4X
16X
16X
Output Buffers to driveCapacitive Loads
Pi*Pi-1
Gi + Pi*Gi-1
Design Equations for Brent Kung AdderGi = Ai AND Bi … (1)Pi = Ai XOR Bi … (2)Gi
1=Gi + Pi AND Gi-1 … (3)Pi
1=Pi AND Pi-1 … (4)
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Gate Level Diagram
3. Output Block for Post Computation
1.182X1.117X
Ci-1
Pi
Output Buffers to driveCapacitive Loads
Si
Design Equations for Brent Kung AdderGi = Ai AND Bi … (1)Pi = Ai XOR Bi … (2)Gi
1=Gi + Pi AND Gi-1 … (3)Pi
1=Pi AND Pi-1 … (4)
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Transistor Level Design
1. Input Block with Pre Computation
Input Adder Block Chain 1
Gate Number 1.000 2.000 3.000 4.000 5.000Stage G Stage F Stage B Stage H Gate H
Gate Name BUFFER INVERTER NOR INVERTER NAND LOAD hg value 1.000 1.000 1.646 1.000 1.352 36.000 2.225 36.000 6.943 556.248 3.540f value 3.540 3.540 2.151 3.540 2.618648b value 2.893 2.400 1.000 1.000 1.000 1.000S Value 1.000 1.224 1.097 3.883 10.16831 36.000
Input Adder Block Chain 2
Gate Number 1.000 2.000 3.000 4.000Stage G Stage F Stage B Stage H Gate H
Gate Name BUFFER INVERTER XOR NAND LOAD hg value 1.000 1.000 1.893 1.295 13.748 2.451 13.748 12.359 416.510 4.518f value 4.518 4.518 2.386 3.488b value 2.893 2.400 1.780 1.000 1.000S Value 1.000 1.562 1.553 3.043 13.748
Input Adder Block Chain 3
Gate Number 1.000 2.000 3.000Stage G Stage F Stage B Stage H Gate H
Gate Name BUFFER INVERTER NOR LOAD hg value 1.000 1.000 1.646 3.941 1.646 3.941 6.943 45.038 3.558f value 3.558 3.558 2.162b value 2.893 2.400 1.000S Value 1.000 1.230 1.108 3.941
Input Adder Block Chain 4
Gate Number 1.000 2.000 3.000 4.000 5.000Stage G Stage F Stage B Stage H Gate H
Gate Name BUFFER INVERTER XOR NAND INVERTER LOAD hg value 1.000 1.000 1.893 1.295 1.000 40.000 2.451 40.000 6.943 680.832 3.686f value 3.686 3.686 1.947 2.847 3.686447b value 2.893 2.400 1.000 1.000 1.000 1.000S Value 1.000 1.274 1.034 2.943 10.85056 40.000
3.94084
Logical Effort Design for Signal Chains
labeled in previous slide #2
Gi = logical effortFi = fan outSi = sizingBi = Branching in
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Transistor Level Design
2. Intermediate Dot Product Blocks
Intermediate Adder Block Chain 1
Gate Number 1.000 2.000 Stage G Stage F Stage B Stage H Gate HGate Name INVERTER NAND LOAD hg value 1.000 1.352 1.000 1.352 6.000 1.000 8.112 2.848f value 2.848 2.107 2.848b value 1.000 1.000 1.000S Value 1.000 2.107 6.000
Intermediate Adder Block Chain 2
Gate Number 1.000 2.000 Stage G Stage F Stage B Stage H Gate HGate Name BUFFER NAND LOAD hg value 1.000 1.352 2.848 1.352 2.848 2.000 7.701 2.775f value 2.775 2.053b value 2.000 1.000S Value 1.000 1.026
Logical Effort Design for Signal Chains
labeled in previous slide #2
Gi = logical effortFi = fan outSi = sizingBi = Branching in
Brent Kung Adder Transistor Level Design
XOR GATE
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Layout
Input Block with Pre Computation
Input Inverters for Bit 0 and Bit 1
Output BuffersPEX waveforms show
larger size may be needed
XORNAND10X
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Layout
XOR 1.553X
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Layout
Intermediate Dot Product Generator
Output BuffersPEX Waveforms
show largerSize may be necessary
here
Brent Kung Adder Layout
Output Stage with Buffers
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Layout
Full Layout: 49.5um X 48.6um
Brent Kung Adder Worst Case Delay
Input Pattern: A: FFFF B: 0000 -> 0001
Dotted Lines show Carry Bits 15 and 14
Carry Bit 15 Carry Bit 14Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Output waveforms after parasitic extraction from layout: Sum Bit 0
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Output waveforms after parasitic extraction from layout: Sum Bit 14
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Brent Kung Adder Simulated Performance
Voltage (V) Delay Max-C14 (nS)
Power Max (mW)
Power-Delay
Product (xE-12)
1.1 0.359 6.73 2.41
0.9 0.503 2.95 1.483
0.7 0.937 0.924 0.865
Simulations with maximally sized 1 stage buffers as determined by Logical Effort Designof individual chains
Voltage (V) Delay Max-C14 (nS)
Power Max (mW)
Power-Delay
Product (xE-12)
1.1 0.403 5.186 2.089
0.9 0.569 2.277 1.295
0.7 1.069 0.692 0.739
Simulations with minimally sized 1 stage buffers
Without Parasitic Extraction and Interconnect Parasitics buffering doesn’t improve performance significantly.
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
Sr. No. Group Name Adder Type Technology Adder Delay
Power Consumption Power Delay Product Column1
1[1] University of Waterloo Department of ECE
16 bit Kogge Stone FPGA 45nM 419ps 13.29mW 5.57E-12
2 This work16 bit Brent Kung Adder
NCSU 45nM Free PDK ASIC 359ps 6.73mW 2.41E-12
3[4] University of Texas, Tyler Department of EE
16 bit Kogge Stone Spartan 3e 90nM 6.286ns -- --
4 [2] VIT University, Vellore16 bit Kogge Stone SPARTAN 3e 90nM 599ns 46.16uW 2.76E-11
5 [2] VIT University, Vellore16 bit Brent Kung Adder Spartan 3e 90nM 762ns 32.465uW 2.47E-11
16 bit Brent Kung Adder Virtex 2 130nM 26.94ns 1.15W 3.10E-08
7[3] Concordia University Department of ECS
16 bit Kogge Stone Virtex 2 130nM 25.59ns 1.5546W 3.97E-08
Comparison with other similar works:
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
References: Comparison with other similar works:
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
References: 1. K. Nose and T. Sakurai, “Optimization of VDD and VTH for low power high speed applications,” in ACM/IEEE Design Automation Conference (DAC) Digest of Technical Papers, 2000, pp. 469-474From: Sub-threshold Design for Ultra Low-Power SystemsAlice Wang, Benton Highsmith Calhoun, Anantha P. Chandrakasan
2. Logical Effort by Ivan Sutherland, Bob Sproull and David Harris (Book)
3. Digital Integrated Circuits by Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic (Book)
4. A high-density sub-threshold SRAM with data-independent bit line leakage and virtual-ground replica schemeTae-Hyoung Kim, Jason Liu, John Keane, Chris Kim, University of MinnesotaISSCC 2007
5. The Design of CMOS Radio-Frequency Integrated Circuits by Thomas Lee (Book)
Work done as a student at the University of Minnesota, Twin Cities by Nirav Desai [email protected]
