Design of an Ultra Fast Voltage Comporator

8/10/2019 Design of an Ultra Fast Voltage Comporator

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EE 414

TERM PROJECT FINAL REPORT

EREN AYDIN: 1740588

SÜLEYMAN FATİH KARA: 1741214



Design of an Ultrafast, Low Power, High Sensitivity, Rail to Rail Output CMOS Comparator at

180 nm UMC CMOS Technology

Abstract: This report presents design of a comparator at 180 nm UMC CMOS technology. Thedesigned comparator can work at 100 MHz with 1 mV resolution. Moreover it has 950 ps propagation

delay when if rail to rail input is given when 1 pF capacitive load is connected. Furthermore the

designed comparator dissipates less than 1 mW power. The designed comparator includes twenty

transistors. The designed comparator includes an uncompensated opamp, digital inverter stages and

a bias generator. The remaining parts of the report explain design procedure and simulation results.

INTRODUCTION

Voltage comparators are the circuits that compare one analog signal with the other and give

a high or low value. They are used in converting analog signal to digital one like producing

PWM or can be used to produce digital noise. In this project we are supposed to design a

voltage comparator satisfying given specifications 180 nm UMC CMOS technology. To

design the circuit and simulate the designed circuit Cadence is used. The designed circuit

satisfies the given specifications.

I. DESIGN PROCEDURE

In the proposal report a different circuit was proposed. However the proposed circuit needs a three

phase clock. To generate three phase clock internally is a tough job since the clocks produced are

needed to have high frequencies and producing high frequency clocks demands high power.

Furthermore since we use clock, the circuit is not a continuous comparator it can evaluate onecomparison at one clock cycle. It is another reason of high frequency clock requirement. Therefore if

external clock is not available, to design a clocked comparator is not logical. That is why we gave up

designing clocked comparator.

After giving up designing clocked comparator we concentrated on open loop uncompensated

opamps. Uncompensated opamps can be used as comparator. If V+>V- it gives positive output and if

V->V+ it gives negative output. To improve its driving capability and speed we thought to add digital

inverters with stage ratios. We tried using a number of topologies we read from articles but some

specifications are usually failed. Finally we analyzed circuits and omitted unnecessary parts and

arranged W/L ratios of the transistors. The designed circuit satisfies all requirements.

Figure 1: Block Diagram of Designed Comparator





b) Common Source Amplifier Stage

This stage is used to increase the gain of the amplifier stage. Gain of the differential stage is not

enough. Therefore a single input and single output gain stage is used. Designing a commonsource amplifier without resistors was a little bit hard. In this stage two transistors are used and

both transistors are needed to be in saturation region. To keep them in saturation, output

common voltage is needed to be arranged very well. It is required to give about zero volts when

differential amplifier is grounded and connected to this stage. To do this, W/L ratios of nmos and

pmos transistors are swept and the optimum values are arranged. The gain of this stage is not as

high as differential stage and propagation delay of this stage is so low which is about 100 ps.

Total propagation delay of differential stage and this stage is about 300 ps.

Figure 4: Common Source Amplifier

VDD=1.65 Volts

VSS=-1.65 Volts

Vbias: -372 mV

M1: (W/L) = (400n/340n)

M2: (W/L)= (800n/340n)



c) Bias Generation Stage

The designed amplifiers are needed to be biased. To bias the amplifiers vbias is needed to be

produced using VDD and VSS voltages. Since project specifications do not contain any informationabout temperature or supply independence, a very basic biasing circuit is designed. The biasing

circuit includes 3 nmos transistors. Two of them are diode connected and the other one is in linear

region. Changing the resistance of the nmos which is in linear region desired voltage value is

obtained. To decrease power consumption (W/L) ratios of the transistors in this stage are arranged

as small as possible. Total current passing from this stage is about 4 uA. After adding bias circuit,

small changes are done W/L ratios of gain stages.

Figure 5: Bias Generator Circuit

VDD=1.65 Volts

VSS=-1.65 Volts

Vbias: -372 mV

M1: (W/L) = (240n/3.2u)

M2: (W/L) = (240n/2.01u)

M3: (W/L) = (240n/2u)



d) Inverter Stages

This stage is the heart of the designed system. Very small differences at the input are gained thanks

to differential amplifier and common source amplifier. The gained signal is converted to rail to rail

output thanks to inverter stage. Moreover this stage plays the most crucial role in propagation delay.

To decrease propagation delay our inverters should be very fast so that they can fully charge the

capacitive load immediately. Therefore the width of the transistors driving 1 pF load should be large.

However large transistors make capacitive loading effect to previous stages and the system becomes

slower. To solve this problem, more than one inverter is used and the widths of used inverters are

increased by three. This multi inverter technique was mentioned in EE413 class and ideal proportion

between inverters was told three. That is why we chose stage ratios three and put some inverters. To

decide where to stop, we checked propagation delay before adding one more inverter. At 5

th

stagepropagation delay was 950 ps, so I did not using try 6

th inverter. Each inverter is needed to be

symmetric to have symmetric propagation delay. To do this for each inverter size of pmos is swept

and optimized value is obtained. It is very interesting that, size of pmos/nmos is not constant for

each stage. That is why I multiplied size of nmos by three and found ideal pmos size sweeping width

of pmos.

Figure 6: Inverter Stages

M1: (940n/340n) M6: (240n/340n)

M2: (2.3u/340n) M7: (720n/340n)

M3: (6.54u/340n) M8: (2.16u/340n)

M4: (20.04u/340n) M9: (8.8u/340n)

M5: (61.1u/340n) M10: (19.8u/340n)



Figure7: The overall circuit with blocks

Figure 8: The overall circuit



II. SIMULATION RESULTS

Lots of simulations are done while designing overall circuit. In this stage, some simulations showing

performance of the designed circuit will be given.

a)

Propagation Delay

When 10MHz rail to rail input is given to one of the inputs and the other one is grounded, total

propagation delay is about 950 ps.

Figure 9: Propagation delay calculation at 10 MHz

If we increase frequency to 40 MHz, propagation delay is not affected from this frequency change. It

is still same. If input voltage value becomes smaller, propagation delay increases. For example for 1

mV peak square wave input causes 3 ns propagation delay.

Figure 10: Propagation Delay for 1 mV Input at 10 MHz



b) Speed

The circuit can work until 200 MHz. Different inputs are given to the circuit with different frequencies

and it is checked whether the circuit is working or not. Smaller voltages will be at resolution part.

Figure 11: 100 MHz rail to rail input is given

Figure 12: 200 MHz rail to rail input is given



c) Resolution

The designed circuit can work properly with 200 uV resolution at 10 MHz, 500 uV resolution at 40

MHz and 1 mv resolution at 100 MHz.

Figure 13: 10 MHz 1 mV input is given

Figure 14: 10 MHz 200 uV input is given



Figure 15: 1 mV 40 MHz signal is given

Figure 16: 500 uV 40 MHz input is given



Figure 17: 1 mV 100 MHz input signal is given

d) Power Dissipation

Power dissipation is measured in different cases. First of all static power consumption is measured,

then power dissipation with different magnitude and frequency combinations are measured.

Figure 18: Static Power Dissipation



Static power dissipation of the circuit is 669 uW.

Moreover different input combinations are measured.

Figure 19: Current graph when rail to rail input is applied at 10 MHz

Figure 20: Power dissipation calculation for the given case in Figure 19

Power dissipation is 434 uW for rail to rail input at 10 MHz.



Figure 21: Current graph when 1 mV input is applied at 10 MHz

Figure 22: Power dissipation when 1 mV input is applied at 10 MHz

Power dissipation for this case is 783.7 uW.



Figure 23: Power dissipation for rail to rail input at 40 MHz

Power dissipation for this case is 973 uW.

Figure 24: Power dissipation for 1 mV 40 MHz input

For this case power dissipation is 1.3 mW. However when we look at static power dissipation and 10

MHz dynamic power dissipation values, the designed circuit satisfies power dissipation condition.



e) AC Analysis

AC analysis could not be performed to output of inverter stages but it could be performed to one

stage after gain stage.

Figure 25: AC Analysis to the circuit

-3dB frequency of the circuit is 57.8 MHz.

DC gain is 57 dB.

f)

VTC

Sweeping DC input of the comparator voltage transfer characteristics of the comparator can be

obtained. In Figure 26 VTC of the comparator may be seen.

Figure 26: Voltage Transfer Characteristics of the Comparator



When we look at the VTC closer we see a very sharp transition region.

Figure 27: Closer look at VTC of the comparator

As understood from VTC, there is input common mode offset. In fact the transition is needed to be at

0 V input but it is observed at about 160 uV. We can check input DC offset looking at VTC. We can

calculate observing corresponding input voltage corresponding 0 V output voltage.

Figure 28: Input offset voltage calculation

Input offset voltage is calculated as 165 uV.

Transition region is observed between 158 uV and 167 uV input voltages. It is a very sharp transitionregion.



CONCLUSON

In this project we designed a comparator whose specifications are defined. The designed circuit

satisfies all specifications. The designed circuit has 950 ps propagation delay if 1 pF capacitive load is

connected to the output stage. Moreover its resolution is 200 uV at 10 MHz and 500 uV at 40 MHz

and 1 mV at 100 MHz. If rail to rail input is given, the circuit can work at 200 MHz. It dissipated 669uW static power. At 10 MHz if rail to rail input is given 434 uW power is dissipated and if 1 mV input

is given 783 uW power is dissipated. The -3dB frequency of the circuit is 57 MHz and DC gain is 67 dB.

If we look at the VTC of the comparator it can be seen that a very sharp transition is occurring

between states and there is 165 uV input offset voltage at the designed circuit. As a result the

designed circuit satisfied more than given specifications.

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Design of an Ultra Fast Voltage Comporator

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