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Design of the front-end digitization electronics for a G-APD-based Cherenkov telescope camera V. Commichau 1 , L. Djambazov 1 , O. Grimm 1,* , H.P. von Gunten 1 , B. Krumm 2 , W. Lustermann 1 , D. Neise 2 , M. Ribordy 3 , U. Röser 1 , J. Schneider 1 , P. Vogler 1 , K. Warda 2, Q. Weitzel 1 – for the FACT collaboration – 1 ETH Zürich, Institute for Particle Physics, Schafmattstrasse 20, 8093 Zurich, Switzerland 2 Universität Dortmund, Experimental Physics 5, Otto-Hahn-Str. 4, 44221 Dortmund, Germany 3 École Polytechnique Fédérale de Lausanne, Laboratory for High Energy Physics, 1015 Lausanne, Switzerland Trigger Primitives x 1 Event ID x 1 Ethernet Switch x320 Slow control Fiber x 40 Bias Supply outside camera FTU Trigger Unit Time Marker Trigger Clock FAD DRS4 Digitizer FPA Preamp G-APD x1440 x 40 FTM Trigger Master Reset x 40 x 2 FFC Fast Signal Distrib. x1440 x1 / x2 x40 USB Backplane Busy Imaging Air Cherenkov Telescopes from: S. Commichau, PhD thesis, ETH Zürich (2007) Cherenkov light emission First interaction at ≈20 km altitude 0.3º 0.9º 1º Camera image Statistical analysis of image parameters Gamma/hadron separation benefits from sub-ns time resolution γ-ray energy ≈15% resolution for large telescope Arrival direction (source location) ≈10 arcmin resolution No photons from space with wavelength shorter than UV reach ground Direct detection only in space or on high-altitude balloons Cost implies size and weight limit Event rate very low above ≈50 GeV (Crab nebula >30 GeV: ~0.2 photons/cm 2 /year) Above ≈60 GeV: resulting air showers attain detectable size Detection through emitted Cherenkov light Atmosphere behaves as 27 radiation length deep calorimeter Challenge is discrimination against hadronic showers (γ/p ratio <10 -4 ) and muons Typical camera images (MAGIC) γ candidate Hadron FACT – Overview First G-APD Cherenkov Telescope Full-scale camera for long-term monitoring of variable Gamma-ray sources and technology demonstration 4.5º field-of-view (0.11º per pixel), 1440 pixels Operation also under twilight/moon (background rate up to 5 GHz per pixel) Power consumption ≈1 kW Gain stabilization to ≈5% with feedback Installation on former HEGRA CT3 telescope at La Palma (9.2 m 2 mirror) Solid light concentrators Digitization and triggering integrated in camera DRS4 analog pipeline chip (PSI development) Timing better than 300 ps (rms) Data transfer via Ethernet Majority-trigger logic of non-overlapping patches 320 channel bias supply 0-90 V USB interface Custom developed Geiger-mode Avalanche Photo-diode Hamamatsu S10362-33-50C MPPC 3x3 mm area, 50x50 μm pixel, gain 7.5x10 5 U operation = 70V, C total = 320 pF R quench ~200 kΩ, C cell ~ 80 fC → τ recharge = 16 ns Nominal over-voltage U over ~7.5x10 5 e-/C cell =1.5 V ADC AD9238BSTZ-40 12 bit, 2 V range Current-to voltage conversion Transistor in base configuration as current buffer Conversion to voltage over two parallel 390 Ω resistors LVDS Repeater <65 ps jitter 6.8 mV 3.4 mV 13.6 mV Science targets Source discovery Accelerating mechanisms in pulsars and AGN Signatures of new particles Transverse intensity distribution on the ground Electronics Block Diagram Light Sensor Sensor Bias FPA - Amplifier FAD - Digitization x4.5 1.5 mV 6.8 mV 7.5 μA x1 x390 Ω/2 Enable from FTU 5.9 mV 1.3 mV x4.5 x1/5.4 Amplification before summing Output impedance of operational amplifier at signal frequencies ~10 Ω Resistor network between stages results in signal attenuation by ~1/5.4 Summing for trigger generation Analog signals from 9 channels summed and clipped by cable reflection Total gain for trigger 1.6 mV/μA Trigger decision reported over LVDS to FTU (trigger front-end) Clipping cable -5.9 mV -3 mV -12.1 mV Gain 0.9 -13.5 mV x-1 x1/2 X4.5 X0.9 Threshold set by FTU to FAD High precision time marker Time marker (TIM) generated by FTM, transported differentially over category 6 Ethernet cables Backup in case of problems with DRS phase locked loop TIM after test pulse Single-ended to differential conversion Signal attenuated by resistors and input/output impedance between FPA and FAD by ~0.5 Converter set to gain 2 x2 from FPA Calibration voltage from DAC on FAD IN 0 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 S T O P S H IF T R E G IS T E R R E A D S H IF T R E G IS T E R W S R O U T C O N F IG R E G IS T E R R S R L O A D D E N A B L E W S R IN D W R IT E D S P E E D P L L O U T D O M IN O W AV E C IR C U IT P L L A G N D D G N D A V D D D V D D D TA P R E F C L K P L L L C K A 0 A 1 A 2 A 3 E N A B L E O U T 0 O U T 1 O U T 2 O U T 3 O U T 4 O U T 5 O U T 6 O U T 7 O U T 8 / M U X O U T B IA S O -O F S R O F S S R O U T R E S E T S R C L K S R IN F U N C T IO N A L B L O C K D IA G R A M M U X W R IT E S H IF T R E G IS T E R W R IT E C O N F IG R E G IS T E R C H A N N E L 0 C H A N N E L 1 C H A N N E L 2 C H A N N E L 3 C H A N N E L 4 C H A N N E L 5 C H A N N E L 6 C H A N N E L 7 C H A N N E L 8 M U X LV D S DRS4 analog pipeline chip Developed at PSI, Switzerland (http://drs.web.psi.ch/). Chip integration follows PSI VME mezzanine design Common mode from DAC on FAD x2 Sampling frequency 2 GHz Reference clock from FTM) Digital control FPGA Xilinx XC3SD3400A-4FGG676C 50 MHz frequency Stops DRS sampling when triggered Informs trigger master (FTM) when unable to accept triggers Controls DRS4 and ADC (generates clocks) Sets DAC on FAD (input common mode, calibration, output offset) Receives event number over RS485 from FTM Interfaces with Wiznet chip Measures reference clock Reads temperature sensors Data transfer Ethernet interface with Wiznet W5300 chip (100 Mbit/s) 8 TCP/IP sockets used cyclically for sending event data Socket 0 for receiving command FAD boards connected to two Gigabit switches (D-Link DGS-1224T), data transfer to counting house over fibers (Huber+Suhner MO104) Electronics on 12-layer boards for thermal design reasons. Fast digital signals routed via Cat.6 Ethernet cables Boards mounted to custom-build water cooled crates. Thermal interface uses Calmark Card-Loks ROI 1024 100 G-APD dark counts digitized with FAD Double avalanche generated by optical cross-talk Noise after DRS4 calibration 1.5-2 mV rms Total gain 1.8 mV/μA Single avalanche pulse shape 7.5 μA Initial current 1.5 V/200 kΩ G-APD Bias FPA Circuit for bias input and signal out-coupling Measured throughput (10 FAD boards) Peak current of single avalanche 4x9 channel input Trigger from FTU to FTM FTU mezzanine Midplane connector - Signals to FAD - RS-485 to FTM - Power supply * Corresponding author, email [email protected] ~60 MByte/sec Trigger rate with 100 bins region-of-interest ~700 Hz Midplane connector - Signals from FPA - RS-485 to FTM - Power supply Ethernet J-TAG Fast digital signals
