Design of the front-end digitization electronics for aG-APD-based Cherenkov telescope camera
V. Commichau1, L. Djambazov1, O. Grimm1,*, H.P. von Gunten1, B. Krumm2, W. Lustermann1, D. Neise2, M. Ribordy3, U. Röser1, J. Schneider1, P. Vogler1, K. Warda2, Q. Weitzel1
– for the FACT collaboration –1ETH Zürich, Institute for Particle Physics, Schafmattstrasse 20, 8093 Zurich, Switzerland
2Universität Dortmund, Experimental Physics 5, Otto-Hahn-Str. 4, 44221 Dortmund, Germany3École Polytechnique Fédérale de Lausanne, Laboratory for High Energy Physics, 1015 Lausanne, Switzerland
TriggerPrimitives x 1
Event ID
x 1
EthernetSwitch
x320
Slowcontrol
Fiber
x 40
BiasSupplyoutside camera
FTUTriggerUnit
TimeMarker
Trigger
Clock
FADDRS4Digitizer
FPAPreamp
G-APDx1440
x 40
FTMTriggerMaster
Reset
x 40 x 2
FFCFastSignalDistrib.
x1440 x1 / x2x40
USB
Backplane
Busy
Imaging Air Cherenkov Telescopes
from: S. Commichau, PhD thesis, ETH Zürich (2007)
Cherenkov lightemission
First interactionat ≈20 km altitude
0.3º
0.9º
1º
Camera image
Statistical analysis of image parameters
Gamma/hadron separationbenefits from sub-ns time resolution
γ-ray energy≈15% resolution for large telescope
Arrival direction (source location)≈10 arcmin resolution
No photons from space with wavelength shorter than UV reach ground
Direct detection only in space or on high-altitude balloonsCost implies size and weight limitEvent rate very low above ≈50 GeV (Crab nebula >30 GeV: ~0.2 photons/cm2/year)
Above ≈60 GeV: resulting air showers attain detectable size
Detection through emitted Cherenkov lightAtmosphere behaves as 27 radiation length deep calorimeterChallenge is discrimination against hadronic showers (γ/p ratio <10-4) and muons
Typical camera images (MAGIC)
γ candidate Hadron
FACT – OverviewFirst G-APD Cherenkov Telescope
Full-scale camera for long-term monitoring of variable Gamma-ray sources and technology demonstration
4.5º field-of-view (0.11º per pixel), 1440 pixelsOperation also under twilight/moon (background rate up to 5 GHz per pixel)Power consumption ≈1 kWGain stabilization to ≈5% with feedbackInstallation on former HEGRA CT3 telescope at La Palma (9.2 m2 mirror)
Solid light concentrators
Digitization and triggering integrated in camera
DRS4 analog pipeline chip (PSI development)Timing better than 300 ps (rms)Data transfer via EthernetMajority-trigger logic of non-overlapping patches
320 channel bias supply0-90 VUSB interfaceCustom developed
Geiger-mode Avalanche Photo-diode Hamamatsu S10362-33-50C MPPC
3x3 mm area, 50x50 μm pixel, gain 7.5x105
Uoperation = 70V, Ctotal = 320 pFRquench ~200 kΩ, Ccell ~ 80 fC → τrecharge = 16 nsNominal over-voltage U
over~7.5x105 e-/Ccell=1.5 V
ADCAD9238BSTZ-40
12 bit, 2 V range
Current-to voltage conversionTransistor in base configuration as current bufferConversion to voltage over two parallel 390 Ω resistors
LVDS Repeater<65 ps jitter
6.8 mV
3.4 mV
13.6 mV
Science targets
Source discovery
Accelerating mechanisms in pulsars and AGN
Signatures of new particles
Transverse intensitydistribution on the ground
Electronics Block Diagram Light Sensor Sensor Bias
FPA - Amplifier
FAD - Digitization
x4.5
1.5 mV 6.8 mV
7.5 μA
x1 x390 Ω/2Enablefrom FTU
5.9 mV1.3 mV
x4.5x1/5.4
Amplification before summingOutput impedance of operational amplifier atsignal frequencies ~10 Ω
Resistor network between stages results in signalattenuation by ~1/5.4
Summing for trigger generationAnalog signals from 9 channels summed and clipped by cable reflectionTotal gain for trigger 1.6 mV/μA
Trigger decision reported over LVDS to FTU (trigger front-end)
Clipping cable
-5.9 mV -3 mV -12.1 mV
Gain 0.9
-13.5 mV
x-1 x1/2 X4.5 X0.9
Thresholdset by FTU
to FAD
High precision time markerTime marker (TIM) generated by FTM, transported differentially over category 6 Ethernet cablesBackup in case of problems with DRS phase locked loop
TIM after test pulse
Single-ended to differential conversionSignal attenuated by resistors and input/output impedancebetween FPA and FAD by ~0.5Converter set to gain 2
x2
from FPA
Calibration voltagefrom DAC on FAD
I N 0
I N 1
I N 2
I N 3
I N 4
I N 5
I N 6
I N 7
I N 8
S T O P S H I F T R E G I S T E R
R E A D S H I F T R E G I S T E R
W S R O U T
C O N F I G R E G I S T E R
R S R L O A D
D E N A B L E
W S R I N
D W R I T E
D S P E E D P L L O U T
D O M I N O W A V E C I R C U I T
P L L
A G N D
D G N D
A V D D
D V D D
D T A PR E F C L KP L L L C K A 0 A 1 A 2 A 3
EN
AB
LE
O U T 0
O U T 1
O U T 2
O U T 3
O U T 4
O U T 5
O U T 6
O U T 7
O U T 8 /M U X O U T
B I A SO - O F S
R O F SS R O U T
R E S E TS R C L K
S R I N
F U N C T I O N A L B L O C K D I A G R A M
M U X
WR
ITE
SH
IFT
RE
GIS
TE
R
WR
ITE
CO
NF
IG R
EG
IST
ER
C H A N N E L 0
C H A N N E L 1
C H A N N E L 2
C H A N N E L 3
C H A N N E L 4
C H A N N E L 5
C H A N N E L 6
C H A N N E L 7
C H A N N E L 8
M U X
L V D S
DRS4 analog pipeline chipDeveloped at PSI, Switzerland (http://drs.web.psi.ch/).Chip integration follows PSI VME mezzanine design
Common modefrom DAC on FAD x2
Sampling frequency 2 GHzReference clock from FTM)
Digital controlFPGA Xilinx XC3SD3400A-4FGG676C
50 MHz frequencyStops DRS sampling when triggeredInforms trigger master (FTM) when unable to accept triggersControls DRS4 and ADC (generates clocks)Sets DAC on FAD (input common mode, calibration, output offset)Receives event number over RS485 from FTMInterfaces with Wiznet chipMeasures reference clockReads temperature sensors
Data transfer
Ethernet interface with Wiznet W5300 chip (100 Mbit/s)
8 TCP/IP sockets used cyclically for sending event dataSocket 0 for receiving command
FAD boards connected to two Gigabitswitches (D-Link DGS-1224T),data transfer to counting houseover fibers (Huber+Suhner MO104)
Electronics on 12-layer boards for thermal design reasons. Fast digital signals routed via Cat.6 Ethernet cablesBoards mounted to custom-build water cooled crates. Thermal interface uses Calmark Card-Loks
ROI 1024 100
G-APD dark counts digitized with FAD
Double avalanche generated by optical cross-talkNoise after DRS4 calibration 1.5-2 mV rms
Total gain1.8 mV/μA
Single avalanche pulse shape
7.5 μA
Initial current1.5 V/200 kΩ
G-APD
Bias
FPA
Circuit for bias input andsignal out-coupling
Measured throughput(10 FAD boards)
Peak current ofsingle avalanche
4x9 channelinput
Trigger fromFTU to FTM
FTUmezzanine
Midplane connector
- Signals to FAD- RS-485 to FTM- Power supply
*Corresponding author, email [email protected]
~60 MByte/secTrigger rate with 100 binsregion-of-interest ~700 Hz
Midplane connector
- Signals from FPA- RS-485 to FTM- Power supply
Ethernet
J-TAG
Fast digitalsignals
