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Chapter 7 Chapter 7 Designing Sequential Designing Sequential Logic Circuits Logic Circuits Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03 2.1: 12/24/03
Chapter 7Chapter 7
Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits
Rev 1.0: 05/11/031.1: 5/23/031.2: 5/30/032.1: 12/24/03
Sequential LogicSequential Logic(1) Finite State
Machine (FSM)(2) Pipelined System
2 storage mechanisms:
- Positive feedback (SRAM)
- Charge-based (DRAM)
Naming ConventionsNaming Conventions
In our textbook:a latch is Level-sensitive flip-flopa register is Edge-triggered flip-flop
There are many different naming conventions
For instance, many books call Edge-triggered elements flip-flops (asynchronous JK, SR) This leads to confusion
Latch v.s. RegisterLatch v.s. RegisterLatchstores data when clock is low (or high)
D
Clk
Q D
Clk
Q
Registerstores data when clock rises (on edges)
Clk Clk
D D
Q Q
LatchesLatches
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
transparenthold
holdhold
transparent transparent
Timing DefinitionsTiming Definitions
t
CLK
t
D
tc - q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
• Setup time (T_su): the time before the clock edge that the D input has to be stable
• Hold time (T_hold): the time after tue clock edge that the D input has to main stable
• Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.
Characterizing TimingCharacterizing Timing
Clk
D Q
tC -Q
Clk
D Q
tC -Q
tD -Q
Register Latch
Maximum Clock FrequencyMaximum Clock Frequency
FF’s
LOGIC
tp,comb
φ
Also:Tcd,reg + tcd,logic >= thold
tcd: Contamination Delay = Minimum delay of the function
tclk-Q + tp,comb + tsetup <= T
CLK
T
tclk-Q + tp,comb + tsetup
MuxMux--Based LatchesBased LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=
MuxMux--based Latch (TG)based Latch (TG)
CLK
CLK
CLK
D
Q
MuxMux--based Latch (NMOS)based Latch (NMOS)
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
Writing into a Static LatchWriting into a Static Latch
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
MasterMaster--Slave (EdgeSlave (Edge--Triggered) RegisterTriggered) Register
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
CLK
Two opposite latches trigger on edgeAlso called “master-slave latch Pair “
Negative Latch Positive Latch Master Slave
MasterMaster--Slave RegisterSlave RegisterMultiplexer-based latch pair
Q M
Q
D
CLK
T 2I2
T 1I1
I3 T 4I5
T 3I4
I6I5
INVpdTXpdQC
Hold
TXpdINVpdSU
TTITTT
TTIITIT
,,63
,,2311
0
3
+=+==
+×=+++=
−
Setup Time of MSSetup Time of MS--RegisterRegister
D
Q
QM
CLK
I2 2 T2
2 0.5
Vol
ts
0.0
0.2 0.4time (nsec)
(a) Tsetup 5 0.21 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
DQ
QM
CLK
I2 2 T2
2 0.5V
olts
0.0
0.2 0.4time (nsec)
(b) Tsetup 5 0.20 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
•I2-T2 : I2 output to T2•Check input of T2 and output of T2 are the same
ClkClk--Q DelayQ Delay
D
Q
CLK
2 0.5
0.5
1.5
2.5
tc - q(lh)
0.5 1 1.5 2 2.50time, nsec
V o l t s tc - q(hl)
Reduced Clock Load (only 4 CLK load)Reduced Clock Load (only 4 CLK load)MasterMaster--Slave PositiveSlave Positive--edge Registeredge Register
D QT1 I 1
CLK
CLK
T2
CLK
CLKI2
I 3
I4
c.f: 8 Clock loads in conventional Mater-Slave Register Design
Avoiding Clock OverlapAvoiding Clock OverlapCLK
CLK
AB
(a) Schematic diagram
(b) Overlapping clock pairs
X
D
Q
CLK
CLK
CLK
CLK
SR FlipSR Flip--Flop: CrossFlop: Cross--Coupled PairsCoupled Pairs
Forbidden State
QRS Q
Q00 Q
101 0
010 1011 0
S Q
R Q
Cross-coupled NORs
S
R
Q
Q
NOR-based Set-Reset
Flop-Flop
S
QR
Q
Cross-coupled NANDs
Clocked NORClocked NOR--based SR Flipbased SR Flip--FlopFlop
M1
M2
M3
M4
Q
M5S
M6CLK
M7 R
M8 CLK
VDD
Q
Added Clock Control
This asynchronous SR FFis NOT used in datapaths any more,but is a basic building memory cell
S Q
R Q
Cross-coupled NORs
Sizing IssuesSizing Issues
Output voltage dependenceon transistor width
Transient response
4.03.53.0W/L5 and 6
(a)
2.52.00.0
0.5
1.0
1.5
2.0
Q (V
olts
)
time (ns)
(b)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
1
2
W = 1 mµ
3
Volts
Q S
W = 0.9 mµW = 0.8 mµ
W = 0.7 mµW = 0.6 mµ
W = 0.5 mµ
Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic (charge-based)CLK
CLK
CLK
D
Q
Static
C1/C2: Gate cap, DiffusionCap, and Gate-drain couplingcapacitance
Clock OverlapClock OverlapT0-0: T1 and T2 on
Race ConditionNode B cannot be overwritten
by passed D value
Making a Dynamic Latch PseudoMaking a Dynamic Latch Pseudo--StaticStatic
D
CLK
CLK
D
Adding a weak feedback inverter (keeper)
Clocked CMOS (CClocked CMOS (C22MOS)MOS)
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
Slave Stage
“Keepers” can be added to make circuit pseudo-static
New Value of invertedCL1
Previous value stored in CL2
OutputQ
EvaluateHigh-impedance: Hold
Slave
HoldEvaluateMaster
10Clock
Insensitive to ClockInsensitive to Clock--OverlapOverlap
M1
D Q
M4
M2
0 0
VDD
X
M5
M8
M6
VDD
(a) (0-0) overlap
M3
M1
D Q
M2
1
VDD
X
M71
M5
M6
VDD
(b) (1-1) overlap
Will fail in slow rise/fall time of CLOCK Signal!
True SingleTrue Single--Phase Clocked Register (TSPC)Phase Clocked Register (TSPC)
CLKIn
VDD
CLK
VDD
In
Out
CLK
VDD
CLK
VDD
Out
Negative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
A register can be constructed by cascading Positive and Negative Latches 12 transistors are used!
Positive EdgePositive Edge--triggered Register in TSPCtriggered Register in TSPC
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
(a) (b) (c)
CLK=0: (a) Latch D value, (b) Precharge, (c) Open/HoldCLK=1: (a) Open, (b) Evaluate, (c) Update Q value
TSPCTSPC--based Positive Edgebased Positive Edge--Triggered DFFTriggered DFF
From Referenced Textbooks: [1] “CMOS Integrated Circuits: Analysis and Design,” 3rd Ed., by Sung-Mo Kang and Yusuf Leblebici, McGraw-Hill, 2003.
Pipelined Systems using Dynamic Pipelined Systems using Dynamic CMOS CircuitsCMOS Circuits
PipeliningPipeliningRE
GRE
G
REGlog
a
CLK
CLK
CLK
Out
b
REG
REG
REGlog
a
CLK
CLK
CLK
REG
CLK
REG
CLK
Out
b
Reference Pipelined
T_(non-pipe) = 3 x T_(pipeline)
PipeliningPipelining
)(pipelined),,max(pipeline)(non
sulogpd,abspd,addpd,qcmin,
sulogicpd,qcmin
tttttT
tttT
pipe ++=
−++=
−
−
At the expense of “Latency (input-to-output delay)”
Not good for interactive communications
Dynamic LatchDynamic Latch--based Pipelinebased Pipeline
F G
CLK
CLK
In Out
C1 C2
CLK
C3
CLK
CLK
Compute F compute G
Be carefulof Race!
C2MOS LatchC2MOS Latch--based Pipelinebased Pipeline
Race-free as long as function F (implemented by static logic) between the Latches are Non-inverting!
Potential Race Condition Potential Race Condition during 0during 0--00
Review of NPReview of NP--Domino Logic Domino Logic (NORA CMOS Logic)(NORA CMOS Logic)
NPNP--Domino Logic ExampleDomino Logic Example
ab
c d e
out
edcabdedcbaOut ++=+⋅+⋅= )(
NORA CMOS NORA CMOS
(a) Evaluation at Phi=1(b) Evaluation at Phi=0(c) Pipelined NORA CMOS
system
Example of NORAExample of NORA--CMOSCMOS
CLK Module
Need alternative CLK and CLK Modules
Example of NORAExample of NORA--CMOS CMOS NOR2 + INV = OR2
Combine dynamic CMOS and Static CMOS!
Review of TSPC RegisterReview of TSPC Register
CLKIn
VDD
CLK
VDD
In
Out
CLK
VDD
CLK
VDD
Out
Negative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
A register can be constructed by cascading Positive and Negative Latches 12 transistors are used!
Including Logic in TSPC Including Logic in TSPC
CLKIn CLK
VDDVDD
QPUN
PDN
CLK
VDD
Q
CLK
VDD
In1
In1 In2
In2
AND latchExample: logic inside the latch
Used in High-performance CPU (DEC Alpha) designs!
Pipelined TSPC CMOS SystemPipelined TSPC CMOS System
(a) Compared with NORA CMOS, we need two extra transistors per stage. But we can operate at a true singe-phase clock signal.
(b) Very attractive from system-design point of view.
SummarySummarySequential/pipelined circuits need good latches and registers for speed performance.
Dynamic circuits can realize the pipelined system in a very efficient and compact way. But it should be designed with extreme care.
Current trend is NOT to use dynamic CMOS for normal-speed operations in large-scaled designs
dynamic CMOS is not good for re-design, maintain, and verification.
