12 bit High Speed ADC proposal
development in Grenoble (LPSC)
a) Full 1.5 bit/stage Pipeline ADC
b) 2.5 bit/stage + 1.5 +1.5 bits +….+
1.5bits+2 bits from 25 MHz to 40 MHz
c) A new Architecture low latency SAR
ADC.
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Pipeline ADC design: the baseline (25-30MHz)
Critical issuesAmplifier design
Capacitance matching
CM control
Noise issue, distorsion
….
Latency = 7 clock period; thanks to interleaving Sampling/Hold
2
• Transfer function Expression
–Charge Transfer
3
Bottom plate sampling + Boosted Switch
- Charge injections control with this « bottom plate sampling »
- Clock feedthrough compensation.
M1
M2
CLK
CLK ‘
Input Signal
Vg = Vi+Vdd
Vi
Vi
4
Full 1.5 bit/stage @25MSPS
12 bit Pipeline ADC
Parameters
Technology 2-poly 4-metal .35 um CMOS
Power Supply(V) 3.3 V
Area2.5 mm*1.2 mm (chip),
1.7 mm*0.6 mm (core)
Resolution 12 b
Sampling freq. 25 MS/s
Input Dynamic range 2 Vpp
DNL 1 LSB
INL ±4 LSB
SNR 56 dB (fin=1 MHz)
SFDR 61 dB (fin=1 MHz)
ENOB 9.1 bits
Power consumption (mW) 37 mW
FoM 9 pJ.V/éch.
5
This was embedded as IP for CTA Collaboration
The NECTAR0 ChipUniv. of Barcelona
LPSC Grenoble (ADC 12 bits 25 MHz)
CEA/Irfu
6
Improving the Pipeline ADC design
1. Increasing the number of bit/stage => amplifier more difficult
2. Improve the bandwidth up to 40 MHz => amplifier design
3. Analog linearity correction => Dynamic Element Matching (for capacitors)
4. Digital correction => research is going on
7
DEM diagram of a 2.5 bit MDAC stage
Improving linearity, Latency, & going to 40MHz
…
From comparator
output
To DAC control
Command control
RandomGenerator
1TG
8
Road map to Pipeline 40 MSPS
• Reduce C value to ease amplifier design
• Use more 2.5 bit MDAC stages
• More bits in the last stage 4 bits (flash)
• We expect 100 ns Latency time
9
How one can get better latency
time? <100 ns
PIPE line lead intrinsically to more latency
We are working on a new architecture of ADC
With latency better than pipeline
10
New low latency architecture
Flash-SAR ADC
FLASH ADC
SAR ADC
6 bit 7 bit
OFFSET CORRECTION
12 bit
Data
Analog input
clk
> 200MHz
Latency about 45ns
11
Timing diagram for different input
signalclk
smpl
flash
cmd1
cmd2
cmd3
cmd4
cmd5
cmd6
cmd7
Conv_1 Conv_2 Conv_3
7 periods Tlatency = 45 ns @ Tclk=200MHz
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