Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic Reza Faghih Mirzaee a,n , Tooraj Nikoubin b , Keivan Navi c,d , Omid Hashemipour d a Department of Computer Engineering, Science and Research Branch, Islamic Azad University,1938673535 Tehran, Iran b Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, Texas, USA c Department of Electrical and Computer Engineering, University of California, Irvine, USA d Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran article info Article history: Received 30 October 2012 Received in revised form 9 August 2013 Accepted 19 August 2013 Keywords: MVL Ternary logic Static DCVSL CNTFET Ternary noise injection circuit Nanoelectronics abstract Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis. & 2013 Elsevier Ltd. All rights reserved. 1. Introduction Logic style directly affects the performance factors in digital electronics. There are several well-known logic styles such as Complementary Pass-transistor Logic (CPL), Double Pass-transistor Logic (DPL), Dual Value Logic (DVL), etc. Each one has its own pros and cons, making it distinctive for a specific application. Differ- ential Cascode Voltage Swing (DCVS) [1] is another common method of circuitry, which is advantageous in terms of high layout density and extended logic flexibility [2]. Static DCVS circuits may consume more power than traditional CMOS architectures due to nonsymmetrical turn-on and turn-off paths. Nevertheless, they form a robust and reliable structure, and have several potential applications in fault-tolerant systems because of their inherent self-checking capability. The built-in signal redundancy can be used to provide error detection [3]. Moreover, the DCVS logic shows higher reliability for the failure prone very-deep submicron and future nanoelectronic technologies in comparison with stan- dard CMOS logic [4]. All of these logic styles have widely been employed and studied in binary logic. However, binary logic does not efficiently and correspondingly respond to real-world applications. Multiple- Valued Logic (MVL), also known as Many-Valued Logic, is an alternative solution to binary logic drawbacks. Elena Dubrova has perfectly described MVL in [5] as a colored picture rather than a black and white one. It has the potential of becoming the dominant logic in VLSI applications in near future. It reduces the amount of interconnections inside and outside of the chip, increases computational speed, and provides great density of memorized information [5,6]. Among many MVL systems, ternary logic, represented by radix-3, is the most efficient [7,8]. Many previously presented ternary circuits are based on con- ventional MOSFET [9,10] or bipolar [11] technologies. However, the figure of merit is somehow limited due to the fact that these devices are inherently single-threshold [12], and are not entirely suitable for MVL. Since MOSFET has faced many challenges and difficulties in nanoscale regime such as short-channel effects, reduced gate controllability, high leakage power dissipation, and large parametric variations [13], new nanodevices such as Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA), and Carbon Nanotube Field Effect Transistor (CNTFET), have been presented to tackle these problems. CNTFET [14] is a highly appreciated nanoscale device due to its intrinsic similarities to traditional MOSFET. CNTFET operates far faster, and it even consumes less power due to its ballistic transport and low off-current properties [15,16]. As a result, they are very appropriate for high-frequency and low-voltage applications. Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.08.010 n Corresponding author. Tel./fax: þ98 21 44869724 E-mail addresses: [email protected] (R. Faghih Mirzaee), [email protected] (T. Nikoubin), [email protected] (K. Navi), [email protected] (O. Hashemipour). Please cite this article as: R. Faghih Mirzaee, et al., Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.08.010i Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Transcript
Differential Cascode Voltage Switch (DCVS) Strategiesby CNTFET Technology for Standard Ternary Logic
a Department of Computer Engineering, Science and Research Branch, Islamic Azad University, 1938673535 Tehran, Iranb Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, Texas, USAc Department of Electrical and Computer Engineering, University of California, Irvine, USAd Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran
a r t i c l e i n f o
Article history:Received 30 October 2012Received in revised form9 August 2013Accepted 19 August 2013
Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust andreliable circuits. Two main strategies are studied in this paper to form static DCVS-based standardternary fundamental logic components in digital electronics. While one of the strategies leads to fewertransistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nmCNTFET technology at various realistic conditions such as different power supplies, load capacitors,frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even inthe presence of PVT variations. In addition, new noise injection circuits for ternary logic are alsopresented to perform noise immunity analysis.
& 2013 Elsevier Ltd. All rights reserved.
1. Introduction
Logic style directly affects the performance factors in digitalelectronics. There are several well-known logic styles such asComplementary Pass-transistor Logic (CPL), Double Pass-transistorLogic (DPL), Dual Value Logic (DVL), etc. Each one has its own prosand cons, making it distinctive for a specific application. Differ-ential Cascode Voltage Swing (DCVS) [1] is another commonmethod of circuitry, which is advantageous in terms of high layoutdensity and extended logic flexibility [2]. Static DCVS circuits mayconsume more power than traditional CMOS architectures due tononsymmetrical turn-on and turn-off paths. Nevertheless, theyform a robust and reliable structure, and have several potentialapplications in fault-tolerant systems because of their inherentself-checking capability. The built-in signal redundancy can beused to provide error detection [3]. Moreover, the DCVS logicshows higher reliability for the failure prone very-deep submicronand future nanoelectronic technologies in comparison with stan-dard CMOS logic [4].
All of these logic styles have widely been employed and studiedin binary logic. However, binary logic does not efficiently and
correspondingly respond to real-world applications. Multiple-Valued Logic (MVL), also known as Many-Valued Logic, is analternative solution to binary logic drawbacks. Elena Dubrova hasperfectly described MVL in [5] as a colored picture rather than ablack and white one. It has the potential of becoming thedominant logic in VLSI applications in near future. It reduces theamount of interconnections inside and outside of the chip,increases computational speed, and provides great density ofmemorized information [5,6]. Among many MVL systems, ternarylogic, represented by radix-3, is the most efficient [7,8].
Many previously presented ternary circuits are based on con-ventional MOSFET [9,10] or bipolar [11] technologies. However, thefigure of merit is somehow limited due to the fact that thesedevices are inherently single-threshold [12], and are not entirelysuitable for MVL. Since MOSFET has faced many challenges anddifficulties in nanoscale regime such as short-channel effects,reduced gate controllability, high leakage power dissipation, andlarge parametric variations [13], new nanodevices such as SingleElectron Transistor (SET), Quantum-dot Cellular Automata (QCA),and Carbon Nanotube Field Effect Transistor (CNTFET), have beenpresented to tackle these problems.
CNTFET [14] is a highly appreciated nanoscale device due to itsintrinsic similarities to traditional MOSFET. CNTFET operates farfaster, and it even consumes less power due to its ballistic transportand low off-current properties [15,16]. As a result, they are veryappropriate for high-frequency and low-voltage applications.
Contents lists available at ScienceDirect
journal homepage: www.elsevier.com/locate/mejo
Microelectronics Journal
0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved.http://dx.doi.org/10.1016/j.mejo.2013.08.010
Another great advantage is its flexibility in adjusting thresholdvoltage of a transistor. This unique feature makes CNTFET an idealdevice for MVL circuitry. Threshold voltage is simply tunable byaltering diameter of CNTs (DCNT), laid under the gate terminal. Eq. (1)shows the relationship between the threshold voltage and DCNT [17].
V th ¼Eg
2� e¼
ffiffiffi3
p
3� a� Vπ
e� DCNT� 0:43DCNT
ð1Þ
where a (E0.249 nm) is the carbon-to-carbon atom distance, Vπ(E3.033 eV) is the carbon π–π bond energy in the tight bondingmodel, and e is the unit electron charge. Moreover, DCNT is a functionof chiral vectors (n1, n2) (Eq. (2)) [17].
A differential ternary approach has been introduced in [18] fordynamic logic. Although the utilization of dynamic logic leads to afast and compact circuit, it suffers from charge sharing problem,poor noise tolerance, and high switching activity. Two non-standard (negative and positive) Inverter/Buffer structures havebeen presented in [19] on the basis of static DCVS architecture.Then, a ternary multiplexer selects the appropriate input andprovides a standard ternary output. DCVS mid-outputs are dataselectors of the multiplexer. The entire DCVS STI/STB designcontains 28 transistors. New standard ternary gates have beenpresented in [20,21], in which capacitors perform voltage divisionto generate logic value ‘1’. Despite the fact that it eliminates staticpower dissipation and reduces average power consumption, thepresented structures suffer from poor driving power which leadsto slow operation. They are not capable of working properly whenfacing high load capacitors due to charge sharing problem.
Several CNTFET-based ternary designs have recently beenpresented in the literature [8,21–26]. Resistive-load, CNTFET-based ternary circuits have been proposed in [22]. They requirelarge resistors (Z100 MΩ) which are not feasible to be integratedinto CNTFET technology. Ternary adders presented in [23,24] areon the basis of performing voltage division among input variableswhich is a great technique to reduce transistor count. However,the voltage range is already divided in MVL systems. Additionalvoltage divisions cause reduced noise margin, and high vulner-ability to noise and voltage variations. The proposed ternaryinverter in [25] requires Vdd=2 and �Vdd voltage references. As aresult, extra interconnections are needed. Furthermore, havingmultiple on-chip voltages brings additional physical constraints interms of placement and routing [27]. Finally, high-performanceCNTFET-based ternary designs have been presented in [8] and [26].
In this paper, static DCVS-based standard ternary gates (Inverter/Buffer, AND/NAND, OR/NOR), which are fundamental components ofevery arithmetic or logic units, are proposed with the use of CNTFETtechnology. The DCVS structure has an intrinsic advantage of produ-cing both f and f outputs in a parallel manner. The proposed cells arealso advantageous in terms of robustness, transistor-count, andability of working properly in low voltages and high frequencies.The final proposed design benefits from high driving power as well.Various experiments were put into practice to measure the level oftolerance to PVT variations. Eventually, new noise injection circuitsare presented exclusively for ternary logic. They generate noisepulses to investigate noise immunity of ternary circuits. The pro-posed designs also show low sensitivity to noise, and PVT variations.
The rest of the paper is organized as follows: DCVS strategiesfor ternary logic are studied in Section 2. Section 3 presents novelDCVS-based ternary Inverter/Buffer circuits in detail. New DCVS-based NAND/AND and NOR/OR circuits are proposed in Section 4.PVT variation effects and noise immunity are analyzed in Section5. Finally, Section 6 concludes the paper.
2. Static DCVS-based strategies for standard ternary logic
Ternary functions are defined by f: Tn-T [28], where T is aternary domain, and n is a nonnegative integer which specifies thenumber of input arguments, taken by the ternary function. Ternaryis a base-3 numeral system. A Ternary digIT (Tit) contains log2(3)¼1.5849 bits of information. There are two ways to express aninteger value in ternary digits. The balanced ternary (also knownas signed or ternary-symmetrical number system) has the values{�1, 0, 1}3; whereas the unbalanced ternary (also known aspositive or unsigned) is symbolized by the {0, 1, 2}3 set [5]. Forexample, the decimal number 21 is written in balanced ternarynotation as (1110)3, and in unbalanced ternary notation as (210)3.
The use of balanced versus unbalanced ternary encodingdepends both on the intended application and on the physicalsystem that will realize the logic operation [29]. Unbalancedternary is an extension of binary encoding system which is mostlytaken into consideration for ternary circuitry [18–26]. In digitalelectronics, logic value ‘1’ is realized by Vdd=2, whereas Vdd andGND (0 V) voltage levels correspond to logic values ‘2’ and ‘0’,respectively. Passive electronic components such as resistors [8,26]or capacitors [20,21] are employed to perform voltage division inorder to generate logic value ‘1’. Although the usage of capacitorsas voltage dividers brings about less static power dissipation, usingresistors leads to higher driving power and circuit robustness.
DCVS refers to a CMOS-type logic family which requiresn-channel transistors to implement the logic and p-channelcross-coupled bootstrap transistors which pull one of the outputshigh. Two different static DCVS-based strategies are considered inthis paper to implement a standard ternary function (f). The firstone is depicted in Fig. 1a. Two complementary outputs (f and f ) aregenerated in a single DCVS structure almost simultaneously. Two
Fig. 1. Static DCVS strategies to design standard ternary functions. (a) The firststrategy with the use of outer sub-circuits (Design 1). (b) The second strategy withthe integrated sub-circuits (Design 2).
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pairs of resistors perform voltage division in case both f and f areequal to logic value ‘1’. There are three possible scenarios:
(1) f¼ ‘0’:o' In this case, the right(left)-side pull-down network hasto be switched on(off). The output node f becomes ‘0’ throughthe right path. Therefore, the left-side pull-up network (T1)switches on and connects the other output node to the powersupply rail (f ¼ ‘2’).
(2) f¼ ‘1’:1': Both outputs (f and f ) have the same logic value inthis situation. Therefore, the pull-down networks of both sideshave to be on. The output nodes connect to the groundthrough the right and the left paths. T1 and T2 switch onconcurrently. The resistors divide voltage, and hence bothoutputs become ‘1’. The threshold voltages of T1 and T2 haveto be adjusted in a way that both transistors remain switched-on when their gate terminal is Vdd=2. Thus, the transistors aremarked with 1.5/2, above which they switch off.
(3) f¼ ‘2’:2': The whole scenario is almost the same as the first onein a counterpart manner. This time, the left-side pull-downnetwork has to be on. The output node f connects to theground through the left path. T2 switches on, and the outputnode f becomes ‘2’.
Consequently, the right(left)-side pull-down network has to beswitched on whenever f (f ) is either ‘0’ or ‘1’. Two sub-circuits arerequired to control the switching activity of these networks. Theytake ternary inputs and return a single binary output, whichdetermines whether the related network is switched on or off. Inthe following sections, it will be shown that these sub-circuits areactually Positive Ternary Inverters (PTI) of f and f .
The second strategy is a modified version of the first one, whichis illustrated in Fig. 1b. The basic concept is quite the same asbefore. The outer sub-circuits, which were mentioned in the firststrategy, are integrated into the pull-down networks of the DCVSstructure. In this strategy, the sub-circuits PTI(f) and PTI(f ) arereplaced with Negative Ternary Buffers (NTB). In addition, only thepull-down networks are adequate in order to set up a pathbetween the output node and the ground. Therefore, the numberof transistors diminishes dramatically in the second designmethodology.
Insufficient driving power is a weak point of DCVS structure[30,31]. This drawback can simply be rectified by supplementingfinal inverters which increase current drivability. This is a commontechnique in binary DCVS-based circuits as well [31,32]. Twoternary inverters are added to the final nodes of the design formedby the first strategy (Fig. 2) to improve the driving power. Theeffectiveness of this technique will be shown in the followingsections, especially in the presence of large loads.
Fig. 2. The third strategy of forming static DCVS-based standard ternary circuitswith stronger driving capability (Design 3).
Table 1Functionality of negative ternary, positive ternary, and standard ternary inverters.
ANegative TernaryInverter (NTI)
Positive TernaryInverter (PTI)
Standard TernaryInverter (STI)
0 2 2 21 0 2 12 0 0 0
Table 2Truth table of standard ternary inverter (STI) and standard ternary Buffer (STB).
A f¼STI(A) f ¼STB(A) PTI(f) PTI (f ) NTB (f) NTB(f )
0 2 0 0 2 2 01 1 1 2 2 0 02 0 2 2 0 0 2
Fig. 3. The proposed DCVS-based STI/STB circuits, (a) Design 1, which is based onthe first strategy, (b) Design 2, which is based on the second strategy.
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Finally, transistors are exploited to divide voltage [24]. Asignificant area saving is achieved when external resistors arereplaced by transistors. Unlike MOS devices, n-channel and p-channel transistors with the same geometry have the same carriermobility and consequently the same resistance in CNTFET tech-nology [33].
3. The proposed DCVS-based standard ternary Inverter/Buffer
There are three types of ternary inverters (Table 1). Thestandard ternary inverter (STI) is the most common (Eq. (3)). PTIand NTI are also defined by Eqs. (4) and (5), respectively.
STI¼ 2�A ð3Þ
PTI¼ 2�A if A¼ 0;22 if A¼ 1
�ð4Þ
NTI¼ 2�A if A¼ 0;20 if A¼ 1
�ð5Þ
The functionalities of an STI, a Standard Ternary Buffer (STB), aswell as the required sub-circuits are shown in Table 2. The firstproposed DCVS STI/STB is depicted in Fig. 3a, which complies withthe first strategy. Both outputs are generated within a single DCVScircuit with the usage of 14 transistors. In figures, each transistor ismarked with the number of CNTs under the gate terminal andtheir diameters.
As mentioned in Section 2, when f¼ ‘0’ or f¼ ‘1’, the right-sidepull-down network has to be switched-on. The required logic is aPTI which takes f as the input (Table 2). However, the sub-circuit isnot actually PTI(f). It is a structure which generates the properoutput directly from the input variable (A). The following briefdescription explains the switching activity of pull-down networks(PDN) on both sides:
(1) A¼ ‘0’:(a) f¼STI(A)¼ ‘2’-PTI(f)¼ ‘0’-The right-side PDN is off.
(b) f ¼STB(A)¼ ‘0’-PTI(f )¼ ‘2’-The left-side PDN is on.(2) A¼ ‘1’:
(a) f¼STI(A)¼ ‘1’-PTI(f)¼ ‘2’-The right-side PDN is on.(b) f ¼STB(A)¼ ‘1’-PTI(f )¼ ‘2’-The left-side PDN is on.
(3) A¼ ‘2’:(a) f¼STI(A)¼ ‘0’-PTI(f)¼ ‘2’-The right-side PDN is on.(b) f ¼STB(A)¼ ‘2’-PTI(f )¼ ‘0’-The left-side PDN is off.
The second proposed DCVS STI/STB is depicted in Fig. 3b. It isbased on the second strategy, in which the outer sub-circuits areintegrated into the DCVS tree. Similar to the first design, the right-side pull-down network has to be on whenever f¼ ‘0’ or f¼ ‘1’.Nevertheless, the integrated section is part of the design whoselogic function (Table 2) corresponds to the operation of NTB(f). Infact, it generates the appropriate output from the input variable A.Only the pull-down network is needed to be integrated in order tocause the output node f to be connected to or disconnected fromthe ground. Four transistors are eliminated because of this integra-tion process, and hence the entire circuit has only 10 transistors. Asmentioned before, four transistors are utilized as voltage dividers(resistors). In order to obtain higher resistivity, doped CNT source-and drain-side extension regions (Lss and Ldd) of these transistorsare lengthened by 90 nm. The distance between adjacent CNTs(Pitch) is also set by 4 nm for these transistors.
Eventually, two ternary inverters are supplemented to the finalnodes of the first design in order to strengthen driving capability.The final design (Design 3) is demonstrated in Fig. 4. It has 26transistors.
The proposed designs as well as previously presented STI andSTB circuits are simulated by using Synopsys HSPICE 2008 and theCompact SPICE Model for 32 nm CNTFET-based circuits, includingall nonidealities [34]. This standard model has been designed forunipolar, MOSFET-like CNTFET devices, in which each transistormay have one or more CNT(s). The design presented in [19] is alsosimulated with 32 nm feature size standard nanoscale CMOStechnology. Ternary Fanout-of-4 inverters (TFO4) are used asoutput loads for both STI and STB outputs to provide a realistic
Fig. 4. The final proposed DCVS-based STI/STB with stronger driving capabilities (Design 3).
Table 3Simulation results of STI/STB circuits.
Design Delay STI (ps) Delay STB (ps) Power (lW) Energy consumption (fJ)
simulation setup. Simulations are carried out in 0.65 V powersupply at room temperature.
In ternary logic, the voltage range (between Vdd and Ground) isdivided into two equal zones. The measurement of the delayparameter takes place from the moment that the input signalreaches 50% of the voltage zone which causes the output signal togain the proper value, to the moment that the output signalreaches 50% of the proper voltage zone. The average powerconsumption during all transitions is also reported. Finally, theenergy consumption (also known as Power-Delay Product (PDP)[35]) is a trade-off between delay and power factors, which iscalculated by Eq. (6). Table 3 exhibits the simulation results. Tomeasure how fast STI and STB circuits charge and discharge largeoutput loads, they are simulated by using output load capacitors,ranged from 1 up to 4 fF. The results of this experiment are plottedfor STI and STB outputs in Fig. 5a and b, respectively.
Energy Consumption¼Maximum Cell Delay�Average Power Consumption ð6Þ
The third proposed circuit (Design 3) is the fastest circuitamongst the DCVS-based structures. While the first and thesecond proposed cells show high delay, final ternary inverters inthe third design provide adequate driving current to charge anddischarge large output loads. Speed degradation is the result of the
transmission-gate structure for constructing ternary multiplexerin [19]. The entire circuit is on the basis of non-standard ternaryoutputs (Binary outputs), which is the reasonwhy it consumes lowpower. However, it needs a Vdd=2 voltage reference in order toproduce a standard ternary output. Any additional power supplyleads to extra interconnection inside and outside the chip which isagainst initial MVL targets. In spite of very fast operation, theternary buffer presented in [26] consumes undesirable power,resulting in low performance. Two cascaded ternary inverters of[8] are considered as a ternary buffer. The problem is that any loadcapacitor on the first output lies along the critical path of thesecond output. Therefore, STB experiences higher delay time thanSTI (Fig. 5a versus b). DCVS-based architectures are beneficial ingenerating both outputs almost simultaneously. Finally, althoughthe STI and STB circuits presented in [21] operate very efficiently,they fail to operate properly in the presence of large loadcapacitors. Voltage drop reaches to the amount that causesmalfunction. Reduced noise margin and poor driving capabilityare the main drawbacks of these circuits.
The Voltage Transfer Characteristic (VTC) curve illustrates howa circuit responses to specific input voltages. Fig. 6a shows the VTCcurve of the STI presented in [8]. It has been improved to a greatdegree in the design presented in [26] (Fig. 6b). The turningpoints in transition areas are located near Vdd=3 and ð2� VddÞ=3.
Fig. 5. Delay versus load capacitor, (a) STI output, (b) STB output.
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Fig. 6. VTC curves, (a) STI presented in [8], (b) STI presented in [26], (c) the first andthe third proposed DCVS STI/STB, (d) the second proposed DCVS STI/STB.
Table 4Noise margin of standard ternary inverters.
The VTC curves of the proposed designs are plotted in Fig. 6c andd. The turning points are shifted in order to achieve higher noisemargins. Besides, VTC curves of the first proposed design benefitfrom symmetry and very steep curves in the transition regions forboth STI and STB functions. This leads to lower average staticpower dissipation, and it is the reason why the second designconsumes more power than the first one although it has fewertransistors. The static power is the dominant factor in the givenstructures, not the dynamic power. The third proposed design hasthe same VTC curve as the first one.
The Noise Margin (NM) is the quantity by which a signalexceeds the minimum amount for proper operation. It has to be
calculated four times [36] in ternary logic (Eqs. (7) to (10)). Theminimum amount indicates noise margin (Eq. (11)). The equationsare derived from the classical definition of noise margin [37]. TheVIL and VIH are the input voltages that give the slope of the VTCcurve as �1 (ðdVout=dV inÞ ¼ �1). The acceptable noise margin is atleast 10% of the voltage zone range [38]. If a signal exceeds theacceptable noise margin, a violation in the performance is con-sidered to have happened. Table 4 shows noise margin of the givenand the previous STIs in 0.65 V power supply. The first proposeddesign has the highest noise margin, which is approximately 33%higher than the noise margin of the one presented in [26]. Thehigher noise margin, the more robust and reliable a circuit is.
The VTC curves of the second proposed DCVS-based STI andSTB are not very steep at the beginning. When the input signalstarts increasing, the right-side pull-down network starts switch-ing on gradually, whereas the left-side pull-down networkswitches off far quicker due to the existence of an input inverter.It causes a sudden signal inversion. The non-ideal VTC curve bringsabout lower noise margin for the second design in comparisonwith the first one. However, it still functions correctly with anacceptable noise margin width.
4. The proposed DCVS-based standard ternary AND/NAND andOR/NOR
The truth table of a Standard Ternary AND (ST-AND) togetherwith a Standard Ternary NAND (ST-NAND) is shown in Table 5.Table 6 exhibits the truth table of ST-OR and ST-NOR. ST-AND andST-OR functions are also defined by Eqs. (12) and (13), respectively.Both DCVS ternary strategies are used to design novel min/maxcircuits. The first proposed structures, shown in Fig. 7, areimplemented with 20 transistors each. The integration process inthe second presented structures (Fig. 8) results in the eliminationof six transistors. Therefore, two functions are generated in aparallel manner within a single circuit with the usage of only 16transistors. How they operate is quite the same as the way theproposed DCVS STI/STB structures do.
ST�AND¼ minðA;BÞ ð12Þ
ST�OR¼ maxðA;BÞ ð13ÞFig. 8. The proposed DCVS ternary circuits following the second strategy (Design2), (a) ST-AND/NAND, (b) ST-OR/NOR.
Table 7Simulation results of the proposed DCVS ST-AND/NAND at 100 MHz.
Design Delay (ps) ST-AND/ST-OR Delay (ps) ST-NAND/ST-NOR Power (lW) Energy consumption (fJ)
Finally, two ternary inverters (as illustrated in Fig. 2) could beadded to the final nodes of the first design to create cells withstronger driving capabilities. Although the number of transistorsincreases by 12 (36 transistors as a whole), the circuits operate farefficiently (Table 7). These new circuits are referred as ‘Design 3’.
The proposed designs are simulated in the same conditionspresented in Section 3. Simulation results are shown in Table 7.The delay parameters are almost the same for both outputs in aDCVS structure. This is a great advantage, especially when bothoutputs are required in the following circuit (Fig. 9a). Although it ispossible to employ an inverter to obtain the complementaryoutput (Fig. 9b), any load capacitors on the first output node lieson the critical path of the second output. The unbalancedpropagation-delays will cause significant signal distortions andunwanted glitches in the chain of combinational circuits.
This phenomenon is investigated to visualize the effects. Fig. 9aand b illustrates the same circuits with two different cascadingdesigns. Fig. 9c shows the output signal when the first proposedDCVS ST-AND/NAND structure is used. The balanced propagation-delays for TAND and TNAND functions at the first stage cause anegligible signal distortion at the second stage (Output1), whereasthe usage of ST-NAND and STI circuits, presented in [26], bringsabout a significant glitch (Fig. 9d) despite the fact that they havehigher driving power.
The given structures are also simulated at 1 GHz operationfrequency. Table 8 shows the results, which demonstrate theircapability of working in low voltages and high frequencies at thesame time. Input signal waveform, which is fed to the circuit, aswell as output signals for the proposed DCVS ST-AND/NAND cells
are depicted in Fig. 10. The zoomed rising edge of the outputsignals are shown in Fig. 11. It exhibits rising edge of the ST-ANDoutputs when the input signal switches from ‘0’ to ‘1’ (Fig. 11a) andalso when it switches from ‘1’ to ‘2’ (Fig. 11b). The sharper signalsrise and fall, the faster a circuit operates and the less leakagepower is dissipated.
5. PVT variations and noise immunity analysis'
The effects of Process, Voltage, and Temperature (PVT) variationsas well as noise immunity are investigated in this section. Theproposed DCVS STI/STB and ST-AND/NAND circuits are simulated ina vast range of power supply voltages (0.55 V to 0.8 V). In addition,insusceptibility to temperature variations is another important issue.Therefore, simulations are repeated in different ambient tempera-tures ranged from 0 1C to 70 1C. The results of these experiments areillustrated in Figs. 12 and 13. The proposed circuits operate reliably incase of voltage and temperature variations.
As the feature size scales down into nanoranges, the processvariations become a serious concern, which negatively affect therobustness and performance of the circuits. Inaccurate chipfabrication causes imprecise diameters. To test the sensitivity ofthe proposed circuits to process variations, Monte Carlo transientanalysis with a reasonable number of 30 iterations for eachsimulation is performed. The simulation is repeated 10 timesand the largest deviation is saved as the result. The statisticalsignificance of 30 iterations is quite high. If a circuit operatescorrectly for all the 30 iterations, there is a 99% probability that
Fig. 9. Two different cascading designs, (a) using the proposed DCVS circuits, (b) using the ST-NAND and STI circuits presented in [26], (c) Output1, (d) Output2.
Table 8Simulation results of the proposed DCVS ST-AND/NAND at 1 GHz.
Design Delay (ps) ST-AND/ST-OR Delay (ps) ST-NAND/ST-NOR Power (lW) Energy consumption (fJ)
Fig. 10. Signal waveforms for the proposed DCVS ST-AND/NAND (Design 1, Design 2, and Design 3).
Fig. 11. The zoomed rising edge of the ST-AND output when the input signal a¼ ‘2’ and the input signal b switches (a) from ‘0’ to ‘1’, (b) from ‘1’ to ‘2’.
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over 80% of all possible component values operate properly[39]. Distribution of the diameter is assumed as Gaussian with 6-sigma distribution, which is a reasonable assumption for largenumbers of fabricated CNTs [40]. Furthermore, a standard deriva-tion of 0.04 nm to 0.2 nm is taken into consideration for each
mean diameter value [41]. The experimental results are plotted inFig. 14. This experiment demonstrates the proper operation of theproposed circuits in spite of process variations.
Instead of a single parametric sweep, simultaneous process andvoltage (Fig. 15a), process and temperature (Fig. 15b), voltage and
Fig. 12. Energy consumption versus power supply variations.
Fig. 13. Energy consumption versus power supply variations.
Fig. 14. Maximum energy consumption variation versus DCNT variations.
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Please cite this article as: R. Faghih Mirzaee, et al., Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology forStandard Ternary Logic, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.08.010i
temperature (Fig. 15c) variations are taken into account to mea-sure how robust the third proposed DCVS ST-AND/NAND is.Moreover, maximum delay, power, and energy consumption(PDP) variations are reported in Table 9, while up to 50 1C ambienttemperature, up to 50 mV voltage, and up to 0.2 nm DCNT varia-tions are taken into consideration. The proposed circuit operatesreliably in the presence of all these variations at the same time.
Noise tolerance is the term prevalently used to describe theability of logic circuits to function properly in the presence ofnoise. Noise pulses are characterized by their width and
amplitude. A noise pulse with adequate width and amplitudemay cause an undesired switching. Noise immunity curve (NIC)[42] is used to measure the tolerance of a logic gate to noise.A noise injection circuit is employed to create an input noisepulse. Each point on the noise immunity curve implies that highernoise amplitude with the relevant noise width will cause anoutput glitch. Therefore, a higher NIC implies a more tolerant gateto noise.
A noise injection circuit has been presented in [43] for binarylogic. It takes a rising edge and produces a tuneable noise pulse.Necessary modifications are made in this paper to alter the circuitexclusively for ternary logic (Fig. 16). Four different noise pulsescould be taken into consideration in ternary logic. Rising noisepulses from logic values ‘0’ and ‘1’ could be generated by thecircuits presented in Fig. 16a and b, respectively. The final binaryinverter in Fig. 16a is replaced with a ternary one to create a risingnoise pulse from logic value ‘1’ (Fig. 16b). On the other hand,falling noise pulses may cause a different behavior of the circuitwhose tolerance is being tested. Noise injection circuits depictedin Fig. 16c and d generate falling noise pulses by taking a fallingedge as an input. All noise injection circuits are in accord with theone presented in [43]. Thus, they benefit from controllability.Noise width and amplitude are tuneable by Vc and Vdd,n, respec-tively. The Vdd,n parameter has to be varied near the value of Vdd=2in the first (Fig. 16a) and the third (Fig. 16c) circuits, whereas it hasto be tuned close to Vdd in the second (Fig. 16b) and the fourth(Fig. 16d) ones.
All four noise injection circuits are applied and the lowest NICis reported. The noise width and amplitude should be significantenough to cause malfunction in the circuit following the circuitbeing tested. Noise immunity curves are plotted in Fig. 17 for theproposed ternary designs. NICs are illustrated in separate diagramsfor better visibility and clarification. Average noise thresholdenergy (ANTE) [44] is a standard used to quantify the noiseimmunity. How it is calculated is shown in Eq. (14), where E()denotes the expectation operator, Vnoise is noise amplitude, andTnoise is noise width, which is time duration between the 50%points of the impulse [45]. The ANTE metrics are shown inTable 10 for the proposed designs.
ANTE¼ EðV2noise � TnoiseÞ ð14Þ
6. Conclusion
New standard ternary gates have been presented in this paperbased on the well-known DCVS logic style. Two main differentstrategies have been studied in this paper. The first one has theadvantage of higher noise margin and consuming less power, butwith the price of more transistors and longer critical path incomparison with the second strategy. The use of final ternaryinverters led to decreased delay time and enhanced driving power.Although DCVS-based circuits might not be perfect in terms ofdelay and power consumption, they are advantageous in generat-ing both the output function as well as the inverted output in aparallel manner. This feature not only eliminates unwantedglitches in the chain of combinational circuits, but it also makesthese circuits highly appropriate for fault-tolerant applications.
The proposed designs have been simulated in various condi-tions. Experimental results demonstrate their ability of workingproperly in low voltages and high frequencies, and robustness inpresence of PVT variations. A comprehensive noise analysis havealso included in this paper for ternary logic. Noise margincalculation has been performed for the given ternary inverters.In addition, new noise injection circuits have been proposed inorder to test noise immunity.
Fig. 15. Simultaneous parametric variations for the third proposed DCVS ST-AND/NANDcell (Design 3), Maximum energy consumption variation versus (a) DCNT and voltagevariations, (b) DCNT and temperature variations, (c) Voltage and temperature variations.
Table 9Maximum delay, power, and PDP variations of the third proposed DCVS ST-AND/NAND versus simultaneous DCNT, voltage, and temperature variations.
Maximum delayvariation(ps) ST-AND
Maximumdelay variation(ps) ST-NAND
Maximumpowervariation (lW)
Maximum energyconsumptionvariation (fJ)
224.85 183.32 0.679 0.2068
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