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Digital Circuits II

Introduction to VHDL

Part 1References:

1) Digital Electronics, 9th editon, by William Kleitz, published by Pearson

2) VHDL for Programmable Logic, 1996, by Kevin Skahill, published by Addison

Wesley

3) VHDL Made Easy, 1997, by David Pellerin and Douglas Taylor, Prentice Hall

Spring 2015

Paul I-Hai Lin, Professor of ECET

Dept. of Computer, Electrical and Information Technology

Indiana University-Purdue University Fort Wayne

Prof. Paul Lin

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Topics of Discussion

An overview of VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language)

Basic Building Blocks of VHDL Design

VHDL Examples

Programming Altera FPGA Using VHDL

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An Overview of VHDL

VHDL (Very-High-Speed-Integrated-Circuit Hardware

Description Language)

VHDL Language for Documentation, Synthesis, Simulation for both digital devices and systems

A product of the VHSIC program founded by the U.S. Department of Defense in 1970s and 1980s.

VHDL standard IEEE 1164 was adopted in 1993

• An industry standard for the description, modeling, and synthesis

of digital circuits and systems

• A simulation language

• A design entry language

• A verification language

• A netlist language

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An Overview of VHDL

Why use VHDL

• Power and Flexibility

• Device-independent design

• Portability

• Benchmarking capabilities

• ASCI migration

• Quick time to market and low cost

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An Overview of VHDL

Basic Building Blocks of VHDL Design

• Design Library

• Entity Declaration

• Architecture Body

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VHDL Design Entry and Simulation

VHDL Design Process, ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/VHDL/Quartus_

II_Introduction.pdf

1. Creating a project

2. Design entry using VHDL code editor

3. Synthesizing a circuit specified in VHDL code

4. Fitting a synthesized circuit into an Altera FPGA

5. Assigning the circuit inputs and outputs to specific pins on the FPGA

6. Simulating the designed circuit

7. Programming and configuring the FPG pins on the Altera DE0 board

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Examples of VHDL Example 1:

• Figure 4-13 (a): two input AND gate

• Figure 4-13 (b): VHDL code

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY fig4_13 IS

PORT(

a, b: IN std_logic;

x: OUT std_logic);

END fig4_13;

ARCHITECTURE arc OF fig4_13 IS

BEGIN

x<= a AND b;

END arc; Prof. Paul Lin 7

VCCa INPUT

VCCb INPUTxOUTPUT

AND2

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VHDL Simulation – AND Gate, Using Altera Quartus II

Step 1. Start Altera Quartus II software program

Step 2. File > New Project > Fig4_13

Step 3. File > New > Design Files > VHDL File

Step 4. Enter the following VHDL code, and save it as Fig4_13.vhd

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY fig4_13 IS

PORT(

a, b: IN std_logic;

x: OUT std_logic);

END fig4_13;

ARCHITECTURE arc OF fig4_13 IS

BEGIN

x<= a AND b;

END arc;

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VHDL Simulation – AND Gate, Using Altera Quartus II

Step 5. Assignment > Settings > Simulator Settings > Functional

Step 6. Processing > Start Compilation

Step 7. Processing > Generate Functional Simulation Netlist

Step 8. File > New > Verification/Debugging Files > Vector

Waveform File; save it as Fig4_13.vwf

Step 9. Edit > End Time (16 us); Edit > Grid size (1 us); View > Fit in

Window

Step 10. Node Finder > Filter (Design Entry all names) > List (to see

all nodes a, b, x)

Step 11. Drag all nodes to Fig4_13.vwf

Step 12. Select a node, Edit > Value > Clock (set it to 1 us clock)

Step 13. Select b node, Edit > Value > Clock (set it to 2 us clock)

Step 14. Processing > Start Simulation

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Simulation Result – Fig4_13

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Example 2. VHDL Design Entry and Simulation

Use the Boolean1 project from Lab 1 Part 1 and Lab 2:

x = ab + cd

Step 1: Start Quartus II 9.1 Web Edition program

Step 2: File > Open Projects > Boolean1

Step 3: Create a new VHDL Design File

File > New > Design Files > VHDL File > OK

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VCCa INPUT

VCCb INPUT

VCCc INPUT

VCCd INPUT

xOUTPUT

AND2

inst

AND2

inst1

OR2

inst2

PIN_J6

PIN_H5

PIN_H6

PIN_G4

PIN_J1

Example 2. VHDL Design Entry and Simulation

Step 4: Enter the VHDL Program; save it as “boolean1.vhd” and

add a check mark next to: “Add file to the current project”

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY boolean1 IS

PORT(

a, b, c, d: IN std_logic;

x: OUT std_logic);

END boolean1;

ARCHITECTURE arc OF boolean1 IS

BEGIN

x<= (a AND b) OR (c AND d);

END arc;

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Example 2. VHDL Design Entry and Simulation

Step 5: Remove the previously created Boolean1.bdf file [Block Design

File]

Assignments > Settings

CHOOSE “Category file”, HIGHLIGHT the Boolean1.bdf

PRESS Remove > OK

Step 6: Compile the Project

Processing > Generate Functional Simulation Netlist

Processing > Start Compilation

Step 7: Open Boolean1.vwf

Processing > Start Simulation

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Example 2. VHDL Design Entry and Simulation

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Example 3. VHDL Design Entry and Simulation

Use Altera Quartus II software to design the FPGA logic to implement the Boolean equation x = ab + cd.

Use the Boolean1 project from Lab 1 and Lab 2

Step 1: Start Quartus II 9.1 Web Edition program

Step 2: File > Open Projects > Boolean1

Step 3: Create a new VHDL Design File

File > New > Design Files > VHDL File > OK

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VCCa INPUT

VCCb INPUT

VCCc INPUT

VCCd INPUT

xOUTPUT

AND2

inst

AND2

inst1

OR2

inst2

PIN_J6

PIN_H5

PIN_H6

PIN_G4

PIN_J1

Example 3. VHDL Design Entry and Simulation

Step 4: Enter the VHDL Program

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY boolean1 IS

PORT(

a, b, c, d: IN std_logic;

x: OUT std_logic);

END boolean1;

ARCHITECTURE arc OF boolean1 IS

BEGIN

x<= (a AND b) OR (c AND d);

END arc;

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Example 3. VHDL Design Entry and Simulation

Step 5: File > Save As > Boolean1.vhd

Add a check mark next to: “Add file to the current project”

Save

Step 6: Remove the previously created Boolean1.bdf file [Block Design

File]

Assignments > Settings

CHOOSE “Category file”, HIGHLIGHT the Boolean1.bdf

PRESS Remove > OK

Step 7: Compile the Project

Processing > Generate Functional Simulation Netlist

Processing > Start Compilation

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Example 3. VHDL Design Entry and Simulation

Step 8: Open Boolean1.vwf

Processing > Start Simulation

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Example 4. VHDL Design Entry and Simulation

Use Altera Quartus II software to design the FPGA logic to implement the Boolean equation X = A’BC + ABC’.

Design the logic using the block editor to create a VHDL file called ex4_4.vhd.

File > New > VHDL File

Enter the following VHDL code

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ex4_4 IS

PORT(

a, b, c: IN std_logic;

x: OUT std_logic);

END ex4_4;

ARCHITECTURE arc OF ex4_4 IS

BEGIN

x<= (NOT a AND b AND c) OR (a AND b AND NOT c);

END arc; Prof. Paul Lin 19

Example 4. VHDL Design Entry and Simulation

Use Altera Quartus II software to design the FPGA logic to implement the Boolean equation X = A’BC + ABC’.

Assignment > Settings > Simulation Mode: Functional;

Processing > Start Compilation

Processing > Generate Functional Simulation Netlist

Create ex4_4.vwf file

• File > Verification/Debugging Files > Vector Waveform File

• Edit > End Time (16 us)

• Edit > Grid Size (1 us)

Node Finder > Filter “Design Entry all name”; click “List” to show all

nodes

Drag all nodes: a, b, c, x and place into ex4_4.vwf

• a node: Edit > Value > Clock (set to 1 us)

• b node: Edit > Value > Clock (set to 2 us)

• c node: Edit > Value > Clock (set to 4 us)

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Example 4. VHDL Design Entry and Simulation

Processing > Start Simulation

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Summary & Conclusion

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