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Digital Fundamentals

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Digital Fundamentals. CHAPTER 3 Logic Gates. Logic Gates . Inverter AND Gate OR Gate Exclusive-OR Gate NAND Gate NOR Gate Exclusive-NOR Gate. The Inverter. Truth table 0 = LOW 1 = HIGH. Boolean expression. Pulsed waveforms. The Inverter . - PowerPoint PPT Presentation
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Floyd Floyd Digital Fundamentals, 9/e Digital Fundamentals, 9/e Copyright ©2006 by Pearson Copyright ©2006 by Pearson Education, Inc. Education, Inc. Upper Saddle River, New Jersey Upper Saddle River, New Jersey 07458 07458 All rights reserved. All rights reserved. Slide 1 Digital Fundamentals Digital Fundamentals CHAPTER 3 CHAPTER 3 Logic Gates Logic Gates
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Page 1: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 1

Digital FundamentalsDigital Fundamentals

CHAPTER 3 CHAPTER 3 Logic GatesLogic Gates

Page 2: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 2

Logic Gates Logic Gates

• InverterInverter• AND GateAND Gate• OR GateOR Gate• Exclusive-OR GateExclusive-OR Gate• NAND GateNAND Gate• NOR GateNOR Gate• Exclusive-NOR GateExclusive-NOR Gate

Page 3: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 3

The InverterThe Inverter

Page 4: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 4

The Inverter The Inverter

Boolean expressionTruth table0 = LOW1 = HIGH

Pulsed waveforms

The output of an inverter is always the The output of an inverter is always the complement (opposite) of the input.complement (opposite) of the input.

Page 5: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 5

The AND GateThe AND Gate

Page 6: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 6

The AND Gate The AND Gate

Boolean expression

Truth table0 = LOW1 = HIGH Pulsed waveforms

The output of an AND gate is HIGH only The output of an AND gate is HIGH only when all inputs are HIGH.when all inputs are HIGH.

Page 7: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 7

The AND Gate The AND Gate

3-Input AND Gate3-Input AND Gate

4-Input AND Gate4-Input AND Gate

Page 8: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 8

The OR GateThe OR Gate

Page 9: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 9

The OR Gate The OR Gate

Boolean expression

Truth table0 = LOW1 = HIGH

The output of an OR gate is HIGH The output of an OR gate is HIGH whenever one or more inputs are HIGHwhenever one or more inputs are HIGH

Pulsed waveforms

Page 10: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 10

The OR Gate The OR Gate

3-Input OR Gate3-Input OR Gate

4-Input OR Gate4-Input OR Gate

Page 11: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 11

The NAND GateThe NAND Gate

Page 12: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 12

The NAND GateThe NAND Gate

Boolean expression

Truth table0 = LOW1 = HIGH

The output of a NAND gate is HIGH The output of a NAND gate is HIGH whenever one or more inputs are LOW.whenever one or more inputs are LOW.

Pulsed waveforms

Page 13: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 13

The NAND Gate The NAND Gate

3-Input NAND Gate3-Input NAND Gate 4-Input NAND Gate4-Input NAND Gate

Page 14: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 14

The NOR GateThe NOR Gate

Page 15: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 15

The NOR Gate The NOR Gate

Boolean expression

Truth table0 = LOW1 = HIGH

The output of a NOR gate is LOW The output of a NOR gate is LOW whenever one or more inputs are HIGH.whenever one or more inputs are HIGH.

Pulsed waveforms

Page 16: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 16

The NOR Gate The NOR Gate

3-Input NOR Gate3-Input NOR Gate 4-Input NOR Gate4-Input NOR Gate

Page 17: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 17

Exclusive-OR and Exclusive-NOR GatesExclusive-OR and Exclusive-NOR Gates

Page 18: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 18

Exclusive-OR Gate Exclusive-OR Gate

Boolean expression

Truth table0 = LOW1 = HIGH

The output of an XOR gate is HIGH The output of an XOR gate is HIGH whenever the two inputs are different.whenever the two inputs are different.

Pulsed waveforms

Page 19: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 19

Exclusive-NOR Gate Exclusive-NOR Gate

Boolean expression

Truth table0 = LOW1 = HIGH

The output of an XNOR gate is HIGH The output of an XNOR gate is HIGH whenever the two inputs are identical.whenever the two inputs are identical.

Pulsed waveforms

Page 20: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 20

Programmable LogicProgrammable Logic

Page 21: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 21

Programmable LogicProgrammable Logic

• Programmable AND arrayProgrammable AND array• Programmable link technologyProgrammable link technology• Device programmingDevice programming• In-system programming (ISP)In-system programming (ISP)

Page 22: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 22

Programmable LogicProgrammable Logic

• Programmable AND arrayProgrammable AND array

Page 23: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 23

Programmable LogicProgrammable Logic

Programmable link technologyProgrammable link technology• Fuse technologyFuse technology• Anti-fuse technologyAnti-fuse technology• EPROM technologyEPROM technology• EEPROM technologyEEPROM technology• SRAM technologySRAM technology

Page 24: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 24

Programmable LogicProgrammable Logic

Device programmingDevice programming• Design entryDesign entry

– Text entryText entry– Graphic (schematic) entryGraphic (schematic) entry

Page 25: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 25

Programmable LogicProgrammable Logic

• In-system programming (ISP)In-system programming (ISP)– Joint Test Action Group (JTAG)Joint Test Action Group (JTAG)– Imbedded processor Imbedded processor

Page 26: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 26

Fixed-Function LogicFixed-Function Logic

Page 27: Digital Fundamentals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.Slide 27

Fixed-Function Logic Fixed-Function Logic

• CMOSCMOS• TTLTTL


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