Digital Integrated Circuits A Design Perspective

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© Digital Integrated Circuits2nd Timing Issues

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Timing IssuesTiming Issues

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolić

January 2003

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Synchronous TimingSynchronous Timing

CombinationalLogic

R1 R2Cin Cout Out

In

CLK

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Timing Timing DefinitionsDefinitions

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Latch ParametersLatch Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

PWmtsu

td-q

Delays can be different for rising and falling data transitions

T

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Register ParametersRegister Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

T

tsu

Delays can be different for rising and falling data transitions

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Clock UncertaintiesClock Uncertainties

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty

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Clock NonidealitiesClock Nonidealities

Clock skew Spatial variation in temporally equivalent clock

edges; deterministic + random, tSK

Clock jitter Temporal variations in consecutive edges of the

clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS

Long term tJL

Variation of the pulse width Important for level sensitive clocking

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Clock Skew and JitterClock Skew and Jitter

Both skew and jitter affect the effective cycle time Only skew affects the race margin

Clk

Clk

tSK

tJS

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Clock SkewClock Skew

# of registers

Clk delayInsertion delay

Max Clk skew

Earliest occurrenceof Clk edgeNominal – /2

Latest occurrenceof Clk edge

Nominal + /2

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Positive and Negative SkewPositive and Negative Skew

R1In

(a) Positive skew

CombinationalLogicD Q

tCLK1CLK

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogicD Q

tCLK1

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

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Positive SkewPositive Skew

CLK1

CLK2

TCLK

TCLK

th

2

1

4

Launching edge arrives before the receiving edge

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Negative SkewNegative Skew

CLK1

CLK2

TCLK

TCLK +

2

1

4

3

Receiving edge arrives before the launching edge

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Timing ConstraintsTiming Constraints

R1

D QCombinational

LogicIn

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Minimum cycle time:T - = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive )

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Timing ConstraintsTiming ConstraintsR1

D QCombinational

LogicIn

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Hold time constraint:t(c-q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives lateRace between data and clock

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Impact of JitterImpact of Jitter

CLK

-tji tter

TC LK

t j itter

CLK

InCombinat ional

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter

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Longest Logic Path in Longest Logic Path in Edge-Triggered SystemsEdge-Triggered Systems

Clk

T

TSU

TClk-QTLM

Latest point of launching

Earliest arrivalof next cycle

TJI +

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Clock Constraints in Clock Constraints in Edge-Triggered SystemsEdge-Triggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU < T – TJI,1 – TJI,2 -

Tc-q + TLM + TSU + + 2 TJI < TSkew can be either positive or negative

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Shortest PathShortest Path

ClkTClk-Q TLm

Earliest point of launching

Data must not arrivebefore this time

ClkTH

Nominalclock edge

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Clock Constraints Clock Constraints in Edge-Triggered Systemsin Edge-Triggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < TH + TJI,2 +

Tc-q + TLM < TH + 2TJI+

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How to counter Clock Skew?How to counter Clock Skew?

RE

G

RE

G

R

EG

.

RE

G

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing

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Flip-Flop – Based TimingFlip-Flop – Based Timing

Flip-flop

Logic

Flip-flop delay

Skew

Logic delay

TSU

TClk-Q

Representation after M. Horowitz, VLSI Circuits 1996.

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Flip-Flops and Dynamic LogicFlip-Flops and Dynamic Logic

Logic delay

TSU

TClk-Q

Logic delay

TSU

TClk-Q

PrechargeEvaluateEvaluatePrecharge

Flip-flops are used only with static logic

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Latch timingLatch timing

D

Clk

Q

tD-Q

tClk-Q

When data arrives to transparent latch

When data arrives to closed latch

Data has to be ‘re-launched’

Latch is a ‘soft’ barrier

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Single-Phase Clock with LatchesSingle-Phase Clock with Latches

Latch

Logic

Clk

P

PW

Tskl Tskl TsktTskt

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Latch-Based DesignLatch-Based Design

L1Latch

Logic

Logic

L2Latch

L1 latch is transparentwhen = 0

L2 latch is transparent when = 1

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Slack-borrowingSlack-borrowing

QDIn CLB_A QD QD

CLK1

L1 L2 L1

CLK2 CLK1

CLB_Btpd,A tpd,B

CLK1

CLK2

TCLK

a b c d e

tpd,A

a valid b val id

tDQtpd,B

c valid d valid

tDQ

e valid

slack passed to next stage

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Latch-Based TimingLatch-Based Timing

L1Latch

Logic

Logic

L2Latch

L1 latch

L2 latch

Skew

Can tolerate skew!

Longpath

Shortpath

Static logic

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Clock DistributionClock Distribution

CLK

Clock is distributed in a tree-like fashion

H-tree

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More realistic H-treeMore realistic H-tree

[Restle98]

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The Grid SystemThe Grid System

D r iv e r

D r iv e r

Dri

ver

Driv

er

G C L K G C L K

G C L K

G C L K

•No rc-matching•Large power

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Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million Transistors

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)

Uses Two Level Clock Distribution:

• Single 6-stage driver at center of chip

• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4

Total driver size: 58 cm!

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21164 Clocking21164 Clocking 2 phase single wire clock,

distributed globally 2 distributed driver channels

Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width

Local inverters for latching Conditional clocks in caches to

reduce power More complex race checking Device variation

trise = 0.35ns tskew = 150ps

tcycle= 3.3ns

Clock waveform

Location of clockdriver on die

pre-driver

final drivers

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Clock Drivers

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Clock Skew in Alpha ProcessorClock Skew in Alpha Processor

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2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width

Local clocks can be gated “off” to save power

Reduced load/skew Reduced thermal issues Multiple clocks complicate race

checking

trise = 0.35ns tskew = 50ps

tcycle= 1.67ns

EV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz – 0.35 micron CMOS600 MHz – 0.35 micron CMOS

Global clock waveform

PLL

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21264 Clocking21264 Clocking

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EV6 Clock ResultsEV6 Clock Results

GCLK Skew(at Vdd/2 Crossings)

ps5101520253035404550

ps300305310315320325330335340345

GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)

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EV7 Clock HierarchyEV7 Clock Hierarchy

GCLK(CPU Core)L2

L_C

LK(L

2 C

ache

)

L2R

_CLK

(L2

Cac

he)

NCLK(Mem Ctrl)

DLL

PLL

SYSCLK

DLL

DLL

+ widely dispersed drivers

+ DLLs compensate static and low-frequency variation

+ divides design and verification effort

- DLL design and verification is added work

+ tailored clocks

Active Skew Management and Multiple Clock Domains

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Self-timed and Asynchronous Self-timed and Asynchronous DesignDesign

Functions of clock in synchronous design

1) Acts as completion signal

2) Ensures the correct ordering of events

Truly asynchronous design

2) Ordering of events is implicit in logic

1) Completion is ensured by careful timing analysis

Self-timed design

1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol

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Synchronous Pipelined DatapathSynchronous Pipelined Datapath

In

tpd,reg tpd1

D

R1

Q

CLK

LogicBlock #1

tpd2

D

R2

QLogic

Block #2

tpd3

D

R3

Q D

R4

Q

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Self-Timed Pipelined DatapathSelf-Timed Pipelined Datapath

R2 OutF2In

tpF2

Start Done

R1 F1

tpF1

Start Done

R3 F3

tpF3

Start Done

Req Req Req Req

Ack Ack Ack ACKHS HS HS

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Completion Signal GenerationCompletion Signal Generation

LOGIC

NETWORK

DELAY MODULE

In Out

Start Done

Using Delay Element (e.g. in memories)

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Completion Signal GenerationCompletion Signal Generation

Using Redundant Signal Encoding

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Completion Signal in DCVSLCompletion Signal in DCVSL

PDN

B0

PDN

In1In1In2In2

B1

Start

Start

VDD VDD

DoneB0

B1

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Self-Timed AdderSelf-Timed Adder

P0

C0

P1

G0

P2

G1

P3

G2 G3

VDD

Start

Start

P0

C0

P1

K0

P2

K1

P3

K2 K3

VDD

Start

Start

C0 C1 C2 C3 C4 C4

C4C0 C1 C2 C3 C4

VDD

Start

C4

C3

C2

C1

C4

C3

C2

C1

Start Done

(a) Differential carry generation

(b) Completion signal

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Completion Signal Using Current SensingCompletion Signal Using Current Sensing

Min Delay Generator

StartGNDsense

VDD

Inputs

Current Sensor

Static CMOS Logic

Inpu

t R

egis

ter

Done

Output

A

B

tdelay

toverlap

tpd-NOR

tMDG

Start

A

B

Done

Output valid

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Hand-Shaking ProtocolHand-Shaking Protocol

11

3RECEIVERSENDER

ReqReq

Ack

Data

Ack

Data

(a) Sender-receiver configuration

(b) Timing diagram

cycle 1 cycle 2

Sender’s actionReceiver’s action

Two Phase Handshake

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Event Logic – The Muller-C ElementEvent Logic – The Muller-C ElementA B Fn1

0

0

1

1

0

1

0

(b) Truth table(a) Schematic

1

0

Fn

Fn

1

F

A

B

S

FF

R

QA

B

(a) Logic

(b) Majority Function

(c) Dynamic

A B

B

B

A

VDD

B

FA

B

VDDVDD

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2-Phase Handshake Protocol2-Phase Handshake Protocol

Advantage : FAST - minimal # of signaling events (important for global interconnect)

Disadvantage : edge - sensitive, has state

Senderlogic

Receiverlogic

Data

Handshake logic

Data ready Data accepted

CReq

Ack

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Example: Self-timed FIFOExample: Self-timed FIFO

All 1s or 0s -> pipeline empty

Alternating 1s and 0s -> pipeline full

C C

R1In Out

En

Acki

Reqi

R2 R3

CReq0

Acko

Done

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2-Phase Protocol2-Phase Protocol

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ExampleExample

From [Horowitz]

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ExampleExample

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ExampleExample

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ExampleExample

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4-Phase Handshake Protocol4-Phase Handshake Protocol

Slower, but unambiguous

Also known as RTZ

1 1

2

3 5

4Req

Ack

Data

Cycle 1 Cycle 2

Sender’s action

Receiver’s action

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4-Phase Handshake Protocol4-Phase Handshake ProtocolImplementation using Muller-C elements

Handshake logic

Data ready Data accepted

ReqS

Ack

C C

Senderlogic

Receiverlogic

Data

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Self-Resetting LogicSelf-Resetting Logic

PrechargedLogic Block(L1)



completiondetection

(L1)

completiondetection

(L2)

completiondetection

(L3)

VDD

A B C

intout

Post-chargelogic

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Clock-Delayed DominoClock-Delayed Domino

PulldownNetwork

CLK1

GND

CLK2 (to next stage)

Q1 (also D2)

D1

VDD

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Asynchronous-Synchronous InterfaceAsynchronous-Synchronous Interface

Asynchronoussystem

Synchronous system

Synchronization

fCLK

fin

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Synchronizers and ArbitersSynchronizers and Arbiters

Arbiter: Circuit to decide which of 2 events occurred first

Synchronizer: Arbiter with clock as one of the inputs

Problem: Circuit HAS to make a decision in limited time - which decision is not important

Caveat: It is impossible to ensure correct operation

But, we can decrease the error probability at the expense of delay

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A Simple Synchronizer A Simple Synchronizer

• Data sampled on rising edge of the clock

• Latch will eventually resolve the signal value,but ... this might take infinite time!

CLK

int

I2

I1D Q

CLK

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Synchronizer: Output Trajectories Synchronizer: Output Trajectories

Single-pole model for a flip-flop

2.0

1.0

0.00 100 200 300

Vou

t

time [ps]

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Mean Time to FailureMean Time to Failure

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ExampleExampleTf = 10 nsec = T

Tsignal = 50 nsec

tr = 1 nsec

t = 310 psecVIH - VIL = 1 V (VDD = 5 V)

N(T) = 3.9 10-9 errors/secMTF (T) = 2.6 108 sec = 8.3 yearsMTF (0) = 2.5 sec

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Influence of NoiseInfluence of Noise

Initial Distribution

p(v)

0 VIL VIH

T

Uniform distributionaround VM

Still Uniform

logarithmic reduction

Low amplitude noise does not influence synchronization behavior

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Typical SynchronizersTypical Synchronizers

1

2

Q

Q

1

2

Using delay line

2 phase clocking circuit

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Cascaded Synchronizers Reduce MTFCascaded Synchronizers Reduce MTF

Sync Sync SyncIn O1 O2 Out

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ArbitersArbiters

Req1

Req2

Req1

Req2

Ack1

Ack2Arbiter

Ack1

Ack2

(a) Schematic symbol

(b) Implementation

A

B

Req1

Req2

A

B

Ack1 t

(c) Timing diagramVT gap

metastable

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PLL-Based SynchronizationPLL-Based Synchronization

DigitalSystem

Divider

CrystalOscillator

PLL

Chip 1

DigitalSystem

PLL

Chip 2

fsystem = N x fcrystal

fcrystal 200<Mhz

Data

ClockBuffer

referenceclock

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PLL Block DiagramPLL Block Diagram

Phasedetector

Chargepump

Divide byN

Loopfilter

VCO

Referenceclock

Localclock

SystemClock

Up

Down

v

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Phase DetectorPhase Detector

ref

localclock

localclock

Output

Output

ref

VDD

-180 -90 90 180 phase error (deg)

Output (Low pass filtered)(a)

(c)

(b)

Output before filtering

Transfercharacteristic

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Phase-Frequency DetectorPhase-Frequency Detector

(c) Timing waveforms

(a) schematic (b) state transition diagram

A

B

UP

DN

A

B

UP

DN

D Q

D Q

A

B

Rst

Rst

UP

DN

UP = 0DN = 1

UP = 0DN = 0

UP = 1DN = 0

B

B A

A

A B

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PFD Response to FrequencyPFD Response to Frequency

A

B

UP

DN

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PFD Phase Transfer CharacteristicPFD Phase Transfer Characteristic

VDD

phase error (deg)

Average (UP-DN)

2

2

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Charge PumpCharge Pump

VDD

UP

DN

To VCO Control Input

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PLL SimulationPLL Simulation

00.0

0.2

0.4

0.6

0.8

1.0

1 2 3 4 5

Con

trol

Vo

ltage

(V

)

Time ( s)

ref

div

vco

ref

div

vco

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Clock Generation using DLLsClock Generation using DLLs

PhaseDet

ChargePump

Filter

DL

PD CP VCO÷N

Delay-Locked Loop (Delay Line Based)

Phase-Locked Loop (VCO-Based)

U

D

U

D

fREF

fO

fO

fREF

Filter

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Delay Locked LoopDelay Locked Loop

Phasedetect

Chargepump

VCDLFREF

PH

U

DC

VCTRL

FO

REF

OUT

UP

DN

Delay

PH

VCTRL

(a)

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DLL-Based Clock DistributionDLL-Based Clock Distribution

VCDL

CP/LF

PhaseDetector

VCDL

CP/LF

PhaseDetector

DigitalCircuit

•••

DigitalCircuit

•••

GLOBAL CLK

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Digital Integrated Circuits A Design Perspective

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