Digital System Design Lab Report - VHDL ECE

NATIONAL INSTITUTE OF TECHNOLOGYCALICUT

Department of Electronics and Communication Engineering

Monsoon 2016

EC6101 DIGITAL SYSTEM DESIGN LAB REPORT

SUBMITTED BY

BHUKYA RAMESH NAIK

DSD LAB REPORT MONSOON 2016

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INDEX

MODULE MODELPROGRAMPAGE

I. DATA FLOW MODEL

1. HALF ADDER 4

2. FULL ADDER 7

3. COMPARATOR (4 BIT) 11

4. SHIFT REGISTER (16 BIT AND 64 BIT) 15

5. MULTIPLEXER 2x1 WITH TRISTATING 19

6. DECODER 2x4 WITH TRI STATING 22

II. BEHAVIORAL MODEL

1. COUNTER (UP/DOWN DECADE) 26

2. BCD SUBTRACTOR AND ADDER 31

3. FLIP FLOPS (JK FF,D FF,T FF) 35

4. MEMORY 47

5. LIFO STACK 51

6. FIFO STACK 55

III. STRUCTURAL MODEL

1. FULL ADDER 59

2. 4 BIT BINARY ADDER 64

3. 4 BIT COUNTER 69

4. 4 BIT COUNTER (GENERATE STATEMENT) 75

5. 4 BIT SHIFT REGISTER 80

6. 4 BIT RING COUNTER 85

7. 4 BIT TWISTED RING COUNTER 90

IV. DESIGN OF 16 x 4 MEMORY 95

V. DESIGN OF 64 x 8 MEMORY 99


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MODULE PROGRAMPAGE

VI : USE A FF AS A COMPONENT THE DESIGN OF WHICH IS PLACED IN ANOTHER

LIBRARY. BIND IT USING A CONFIGURATION, AND DESIGN A 16 BIT COUNTER. 103

VII: WRITE A NUMBER OF FUNCTIONS AND STORE IN A PACKAGE .USE THESE FUNCTIONS

FROM A DIFFERENT DESIGN LIBRARY (FIND APPLICATIONS TO USE THE FUNCTIONS)

A) CONVERSION FROM BIT VECTOR TO INTEGER AND VICE VERSA. 107

B) COUNTING THE NUMBER OF ZEROS (AND NUMBER OF ONES). 107

C) FINDING THE BIGGEST OF 10 INTEGERS 107

VIII: DESIGN THE FOLLOWING AS STATE MACHINES

A) UP/DOWN COUNTER COUNTING FROM 0 TO 5. 113

B) A CLOCK SERIAL ADDER FOR FOUR BITS 117

C) A SEQUENCE DETECTOR TO DETECT THE SEQUENCE 1001. 120

IX: WRITE A TESTBENCH FOR A 4X1 MULTIPLEXER (DUT). ALL THE INPUT COMBINATIONS ARE STORED IN A FILE “INPUT.TXT”. TESTBENCH SHOULD READ INPUTS FROM THE FILE AND APPLY IT TO THE DUT AND STORE THE RESULT IN ANOTHER FILE NAMED “OUTPUT.TXT”. USE THE RELEVANT PACKAGES FOR FILE HANDLING. 124

X: HARDWARE IMPLEMENTATION (USE SPARTAN 3E FPGA KIT AND SHOW THE

RESULT ON THE HARDWARE). DESIGN THE FOLLOWING CONSIDERING THEM AS

STATE MACHINES

A) 8 BIT SHIFT REGISTER 128

B) UP/DOWN DECADE COUNTER 132


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MODULE I: Design the following in Data flow model.

1.HALF ADDER:

Aim: To implement a half adder using VHDL in data flow model.

Software:Xilinx ISE Design Suite 13.2 with ISim (VHDL/Verilog) simulator.

Theory of operation: This program can add input Boolean variables A and B. According to

that it can generates the Sum and the Carry output. It uses one XOR-gate to generate SUM and

one AND-gate to generate Carry.

Truth Table:

VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity half_df is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end half_df;

architecture Behavioral of half_df is

begin

s<=a xor b;

c<=a and b;

end Behavioral;

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Sum= A XOR B

Carry = A and B


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Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_half_df IS

END tb_half_df;

ARCHITECTURE behavior OF tb_half_df IS

COMPONENT half_df

PORT(

a : IN std_logic;

b : IN std_logic;

s : OUT std_logic;

c : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

--Outputs

signal s : std_logic;

signal c : std_logic;

BEGIN

uut: half_df

PORT MAP (

a => a,

b => b,

s => s,

c => c

);

stim_proc: process

begin

a<='0';b<='0';

wait for 100 ns;

a<='0';b<='1';

wait for 100 ns;

a<='1';b<='0';

wait for 100 ns;

a<='1';b<='1';

wait for 100 ns;

end process;

END;


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RTL and TechnologySchematic Diagrams:

Fig:RTL Schematic Fig:Technology Schematic

Simulation Waveform:

Fig:Simulation Waveform

Result:

The half adder is designed and same is verified using dataflow model.


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2.FULL ADDER:

Aim: To implement a full adder using VHDL in data flow model.


Theory of operation: This program can add input Boolean variables A ,B and Cin.

According to that it can generates the Sum and the Carry output. It uses two XOR-gates to

generate Sum and one AND-gate, one OR-gate and one XOR-gate to generate carry.

Truth Table:

VHDL Code

library IEEE;


entity fulladder is


b : in STD_LOGIC;

cin : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

begin

sum<= a xor b xor cin;

carry<= (a and b) or (b and cin) or (cin and a);

end Behavioral;

A B CIN Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Sum=A xor B xor Cin Carry =(A and B) or (B and Cin) or (Cin and A)


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Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_fulladder IS

END tb_fulladder;

ARCHITECTURE behavior OF tb_fulladder IS

COMPONENT fulladder

PORT(

a : IN std_logic;

b : IN std_logic;

cin : IN std_logic;

sum : OUT std_logic;

carry : OUT std_logic

);

END COMPONENT;

--Inputs



signal cin : std_logic := '0';

--Outputs

signal sum : std_logic;

signal carry : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fulladder PORT MAP (

a => a,

b => b,

cin => cin,

sum => sum,

carry => carry

);

-- Stimulus process

stim_proc: process

begin

a<='0';b<='0';cin<='0';

wait for 100 ns;

a<='0';b<='0';cin<='1';

wait for 100 ns;

a<='0';b<='1';cin<='0';

wait for 100 ns;

a<='0';b<='1';cin<='1';

wait for 100 ns;

a<='1';b<='0';cin<='0';

wait for 100 ns;


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a<='1';b<='0';cin<='1';

wait for 100 ns;

a<='1';b<='1';cin<='0';

wait for 100 ns;

a<='1';b<='1';cin<='1';

wait for 100 ns;

wait;

end process;

END;

RTL and Technology Schematic Diagrams:

Fig:RTL Schematic


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Fig:Technology Schematic



Result:

The full adder is designed and same is verified using dataflow model.


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3.COMPARATOR:

Aim: To implement a comparator using VHDL in data flow model.


Theory: A digital comparator is a hardware electronic device that takes two numbers as input

in binary form and determines whether one number is greater than, less than or equal to the other

number.

Truth Table:

Inputs A>B A<B A=B

A3>B3 X X X H L L

A3=B3 A2>B2 X X H L L

A3=B3 A2=B2 A1>B1 X H L L

A3=B3 A2=B2 A1=B1 A0>B0 H L L

A3=B3 A2=B2 A1=B1 A0=B0 L L H

A3<B3 X X X L H L

A3=B3 A2<B2 X X L H L

A3=B3 A2=B2 A1<B1 X L H L

A3=B3 A2=B2 A1=B1 A0<B0 L H L

Table: 4-bit comparator

VHDL Code

library IEEE;


entity comparator4bit_when_else is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

l : out STD_LOGIC;

e : out STD_LOGIC;

g : out STD_LOGIC);

end comparator4bit_when_else;

architecture Behavioral of comparator4bit_when_else is


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begin

l<='1' when (a<b) else '0';

g<='1' when (a>b) else '0';

e<='1' when (a=b) else '0';

end Behavioral;

Test Bench

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

ENTITY tb_fourbit_when_else IS

END tb_fourbit_when_else;

ARCHITECTURE behavior OF tb_fourbit_when_else IS

COMPONENT comparator4bit_when_else

PORT(

a : IN std_logic_vector(3 downto 0);

b : IN std_logic_vector(3 downto 0);

l : OUT std_logic;

e : OUT std_logic;

g : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(3 downto 0) := (others => '0');

signal b : std_logic_vector(3 downto 0) := (others => '0');

--Outputs

signal l : std_logic;

signal e : std_logic;

signal g : std_logic;

BEGIN

uut: comparator4bit_when_else PORT MAP (

a => a,

b => b,

l => l,

e => e,

g => g

);

-- Stimulus process


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stim_proc: process

begin

a<="1111";b<="1000";

wait for 100 ns;

a<="0111";b<="1000";

wait for 100 ns;

a<="1111";b<="1111";

wait for 100 ns;

end process;

END;


Fig:RTL Schematic


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Result:

The 4 bit comparator is designed and same is verified using dataflow model.


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4.Shift Register 16 bit and 64 bit:

Aim: To implement Shift register 16 bit and 64 bitusing VHDL in data flow model.


Theory of operation: This program shift right the value stored in the input register by 1 bit

position when positive edge of the clock encountered and stores the new value in an output

register.

VHDL Code

library IEEE;


entity shitreg16and64bit is

Port ( i,j : in STD_LOGIC;

clk : in STD_LOGIC;

shift16,shift64 : in STD_LOGIC;

q1:out STD_LOGIC_vector(15 downto 0);

q2 : out STD_LOGIC_vector(63 downto 0));

end shitreg16and64bit;

architecture Behavioral of shitreg16and64bit is

signal s:std_logic_vector(15 downto 0):=x"FFFF";

signal y:std_logic_vector(63 downto 0):=x"FFFFFFFFFFFFFFFF";

begin

s<=i & s(15 downto 1) when clk='1' and clk'event and shift16='1'else s;

q1<=s;

y<=y(62 downto 0)& j when clk='1' and clk'event and shift64='1' else y;

q2<=y;

end Behavioral;

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_shift16and64bit IS

END tb_shift16and64bit;

ARCHITECTURE behavior OF tb_shift16and64bit IS

COMPONENT shitreg16and64bit

PORT(

i : IN std_logic;

j : IN std_logic;

clk : IN std_logic;

shift16 : IN std_logic;


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shift64 : IN std_logic;

q1 : OUT std_logic_vector(15 downto 0);

q2 : OUT std_logic_vector(63 downto 0)

);

END COMPONENT;

--Inputs

signal i : std_logic := '0';

signal j : std_logic := '0';

signal clk : std_logic := '0';

signal shift16 : std_logic := '0';

signal shift64 : std_logic := '0';

--Outputs

signal q1 : std_logic_vector(15 downto 0);

signal q2 : std_logic_vector(63 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

uut: shitreg16and64bit PORT MAP (

i => i,

j => j,

clk => clk,

shift16 => shift16,

shift64 => shift64,

q1 => q1,

q2 => q2

);

-- Clock process definitions

clk_process :process

begin

clk <= '1';

wait for clk_period/2;

clk <= '0';


end process;

-- Stimulus process

stim_proc: process

begin

i<='0';shift16<='1';j<='0';shift64<='1';wait for 10 ns;








j<='0';shift64<='1';wait for 10 ns;




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wait;

end process;

END;


Fig:RTL Schematic


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Result:

Shift registers of 16 bit and 64 bit are designed and same are verified using dataflow model.


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5.MULTIPLEXER WITH TRI-STATE:

Aim: To implement Multiplexer 2x1 with tri-stateinput using VHDL in data flow model.


Theory of operation: This program builds a 2:1 multiplexer which functions only when the

tri-state input is high else enter into high impedance state. That is tri-state is like an enable if it is

‘1’ then output will depend on select line and if tri-state is 0 then output remain in high

impedance state.

VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity mux_2x1_tristate is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

s : in STD_LOGIC;

en: in std_logic;

o : out STD_LOGIC);

end mux_2x1_tristate;

architecture Behavioral of mux_2x1_tristate is

begin

o<=((not s) and i0) or (s and i1) when en='1' else '0';

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_mux_2x1_tristate IS

END tb_mux_2x1_tristate;

ARCHITECTURE behavior OF tb_mux_2x1_tristate IS

COMPONENT mux_2x1_tristate

PORT(

i0 : IN std_logic;

i1 : IN std_logic;

s : IN std_logic;

en: IN std_logic;

o : OUT std_logic

);

END COMPONENT;

--Inputs

signal i0 : std_logic := '0';

signal i1 : std_logic := '0';


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signal en: std_logic:='0';

signal s : std_logic := '0';

--Outputs

signal o : std_logic;

BEGIN

uut: mux_2x1_tristate PORT MAP (

i0 => i0,

i1 => i1,

en=>en,

s => s,

o => o

);

-- Stimulus process

stim_proc: process

begin

i0<='1';i1<='0';en<='0';

s<='1'; wait for 100 ns;


i0<='1';i1<='0';en<='1';



end process;

END;


Fig:RTL Schematic


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Result:

Multiplexer 2:1with tristate enable is designed and same are verified using dataflow model.


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6.DECODER WITH TRISTATE:

Aim: To implement Decoder 2x4 with tri-state input using VHDL in data flow model.


Theory of operation: This program builds a 2x4 decoder which functions only when the tri-

state input is high else enter into high impedance state. That is tri-state is like an enable if it is ‘1’

then output will depend on inputs and if tri-state is 0 then output remain in high impedance state.

VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity decoder2x4_tristate is


b : in STD_LOGIC;

enable : in STD_LOGIC;

z : out STD_LOGIC_VECTOR (3 downto 0));

end decoder2x4_tristate;

architecture Behavioral of decoder2x4_tristate is

begin

z(3)<=(a and b) when enable='1' else 'Z';

z(2)<=(a and (not b))when enable='1' else 'Z';

z(1)<=((not a) and b)when enable='1' else 'Z';

z(0)<=((not a) and (not b) )when enable='1' else 'Z';

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_decoder2x4_tristate IS

END tb_decoder2x4_tristate ;

ARCHITECTURE behavior OF tb_decoder2x4_tristate IS

COMPONENT decoder2x4_tristate

PORT(

a : IN std_logic;

b : IN std_logic;

enable : IN std_logic;

z : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;


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--Inputs



signal enable : std_logic := '0';

--Outputs

signal z : std_logic_vector(3 downto 0);

BEGIN

uut: decoder2x4_tristate PORT MAP (

a => a,

b => b,

enable => enable,

z => z

);

-- Stimulus process

stim_proc: process

begin

a<='0';b<='0';enable<='1';

wait for 100 ns;

a<='0';b<='1';enable<='0';

wait for 100 ns;

a<='1';b<='0';enable<='1';

wait for 100 ns;

a<='1';b<='1';enable<='0';

wait for 100 ns;

a<='0';b<='0';enable<='0';

wait for 100 ns;

a<='0';b<='1';enable<='1';

wait for 100 ns;

a<='1';b<='0';enable<='0';

wait for 100 ns;

a<='1';b<='1';enable<='1';

wait for 100 ns;

wait;

end process;

END;


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Fig:RTL Schematic



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Result:

Decoder 2x4 with tristate enable input is designed and same are verified using dataflow model.


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MODULE II: Design the following in Behavioral model (Process model).

1.BINARY UP/DOWN DECADE COUNTER:

Aim: To simulate 4 bit UP/DOWN decade counter using VHDL in process model.


Theory of operation: A counter which is reset at 10th clock pulse is called decade counter.

The decade counter is otherwise is called divide by 10 counter, MOD-10 counter or BCD

counter. A decade counter is one that counts in decimal digits, rather than binary. A decade

counter is a binary counter that is designed to count to 1010, or 10102.It counts from 0 to 9 and

then resets to zero. The counter output can be set to zero by the reset input. The count then

increments or decrements on each clock pulse until it reaches 1001 (decimal 9).

Truth Table:

UP decade count DOWN decade count

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

On 10th clock pulse it is reset to “0000”

1 0 0 1

1 0 0 0

0 1 1 1

0 1 1 0

0 1 0 1

0 1 0 0

0 0 1 1

0 0 1 0

0 0 0 1

0 0 0 0

On 10th clock pulse it is reset to “1001”


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VHDL Code

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decade_counter is

Port ( reset : in STD_LOGIC;

clk : in STD_LOGIC;

qout_up:out std_logic_vector(3 downto 0);

qout_down:out std_logic_vector(3 downto 0));

end decade_counter;

architecture Behavioral of decade_counter is

signal count1:std_logic_vector(3 downto 0):=x"0";

signal count2:std_logic_vector(3 downto 0):=x"9";

begin

process(clk,reset)

begin

if(reset='1')then

count1<=x"0";

count2<=x"9";

elsif(rising_edge(clk) and count1<10 and count2>0) then

count1<=count1+1;

count2<=count2-1;

end if;

qout_up<=count1;

qout_down<=count2;

end process;

end Behavioral;

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY tb_decade_counter IS

END tb_decade_counter;

ARCHITECTURE behavior OF tb_decade_counter IS

COMPONENT decade_counter

PORT(

reset : IN std_logic;

clk : IN std_logic;

qout_up : OUT std_logic_vector(3 downto 0);

qout_down : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;


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--Inputs

signal reset : std_logic := '0';


--Outputs

signal qout_up : std_logic_vector(3 downto 0);

signal qout_down : std_logic_vector(3 downto 0);


BEGIN

uut: decade_counter PORT MAP (

reset => reset,

clk => clk,

qout_up => qout_up,

qout_down => qout_down

);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

reset<='1';wait for 10 ns;

reset<='0';wait for 200 ns; wait;

end process;

END;


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Fig:RTL Schematic



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Result:

Decade up/down counter is designed and same are verified using behavioral model.


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2. BCD SUBTRACTOR AND ADDER:

Aim:To simulate a 4 bit BCD subtractor and adder using VHDL in process model.


Theory of Operation:

In this code, each decimal digit, 0 troughs 9, is coded by a 4-bit binary number. It is also

called natural binary code because of the 8-4-2-1 weighs attached to it. There are six illegal

combinations in this code (1010, 1011, 1100, 1101, 1110 and 1111).

FOR BCD Addition :

The BCD addition is performed individually adding the corresponding digits of the

decimal numbers expressed in 4-bit binary groups starting from the LSD. If there is a carry out of

one group to the next group or if the result is illegal code, then 610 (0110) is added to the sum

term of that group and the resulting carry is added to the next group (This is done trough to skip

the six illegal conditions).

FOR BCD Subtraction:

The BCD Subtraction is performed by subtracting the digits of each 4-bit group of the

subtrahend from the corresponding 4-bit group of the minuend in binary starting from the LSB.

If there is a borrow from the next group, then 610 (0110) is subtracted from the difference term of

this group (This is done trough to skip the six illegal conditions).

VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_unsigned.ALL;

entity bcd_add_sub is

port(a,b : in std_logic_vector(3 downto 0);

mode : in std_logic;

sign : out std_logic;

output : out std_logic_vector(4 downto 0)

);

end bcd_add_sub;


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architecture Behavioral of bcd_add_sub is

begin

process(a,b,mode)

variable x:std_logic_vector(4 downto 0):="00000";

begin

if(mode='1') then

x:=('0'& a)+('0'& b);

if(x>9) then

x:=x+6;

sign<='0';

else

x:=x;

sign<='0';

end if;

elsif(mode='0') then

if(a>b or a=b) then

x:=('0'& a)-('0'& b);

sign<='0';

else

x:=('0'&b)-('0'& a);

sign<='1';

end if;

end if;

output<=x;

end process;

end Behavioral;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL;

ENTITY tb_bcd_add_sub2 IS

END tb_bcd_add_sub2;

ARCHITECTURE behavior OF tb_bcd_add_sub2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bcd_add_sub

PORT(

a : IN std_logic_vector(3 downto 0);

b : IN std_logic_vector(3 downto 0);

mode : IN std_logic;

sign : OUT std_logic;

output : OUT std_logic_vector(4 downto 0)


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);

END COMPONENT;

--Inputs

signal a : std_logic_vector(3 downto 0) := (others => '0');

signal b : std_logic_vector(3 downto 0) := (others => '0');

signal mode : std_logic := '0';

--Outputs

signal sign : std_logic;

signal output: std_logic_vector(4 downto 0);

BEGIN


uut: bcd_add_sub PORT MAP (

a => a,

b => b,

mode => mode,

sign => sign,

output => output

);

-- stimulus process

stim_proc: process

begin

a<="0101";b<="0011"; mode<='1'; wait for 50 ns;






end process;

END;


Fig:RTL SchematicFig:Technology Schematic


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Result:

BCD adder and subtracter is designed and same is verified using behavioral model.


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3.1 JK FLIP-FLOP:

Aim: To simulate JK flip-flop using VHDL in process model.

Theory of Operation:The JK flip-flop augments the behavior of the SR flip-flop (J=Set,

K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the

combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a

command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-

flop, i.e., change its output to the logical complement of its current value.

Truth Table:

VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity jkflip is

Port ( j : in STD_LOGIC;

k : in STD_LOGIC;

clk : in STD_LOGIC;

q : out STD_LOGIC;

qbar : out STD_LOGIC);

end jkflip;

architecture Behavioral of jkflip is

signal state:std_logic:='0';

signal input:std_logic_vector(1 downto 0);

begin

input<=j&k;

process(j,k,clk)

begin

if(rising_edge(clk)) then

case input is

when "01"=> state<='0';

when "10"=>state<='1';


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when "11"=>state<=not state;

when others=> null;

end case;

end if;

end process;

q<=state;

qbar<=not state;

end Behavioral;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_jkflip IS

END tb_jkflip;

ARCHITECTURE behavior OF tb_jkflip IS

COMPONENT jkflip

PORT(

j : IN std_logic;

k : IN std_logic;

clk : IN std_logic;

q : OUT std_logic;

qbar : OUT std_logic

);

END COMPONENT;

--Inputs

signal j : std_logic := '0';

signal k : std_logic := '0';


--Outputs

signal q : std_logic;

signal qbar : std_logic;



BEGIN


uut: jkflip PORT MAP (

j => j,

k => k,

clk => clk,

q => q,

qbar => qbar

);


ECED Page37



begin

clk <= '1';


clk <= '0';


end process;

stim_proc: process

begin

j<='1';k<='0';wait for 50 ns;

j<='0';k<='1';wait for 50 ns;

j<='1';k<='1';wait for 50 ns;

j<='0';k<='0';wait for 50 ns;

end process;

END;


Fig:RTL Schematic


ECED Page38




Result:

JK flip flop is designed and same is verified using behavioral model.


ECED Page39

3.2 D FLIP-FLOP:

Aim: To simulate D flip-flop using VHDL in process model.

Theory of Operation:It is also known as a data or delay flip-flop. The D flip-flop captures

the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the

clock). That captured value becomes the Q output. At other times, the output Q does not change.

Truth Table:

VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity dflip is

Port ( a,reset : in STD_LOGIC;

clk : in STD_LOGIC;

q,qbar : inout STD_LOGIC);

end dflip;

architecture Behavioral of dflip is

signal state:std_logic:='0';

begin

process(clk,reset)

begin

if(reset='1')then

state<='0';

elsif(clk='0'and clk'event)then

state<=a;

end if;

end process;

q<=state;

qbar<=not state;

end Behavioral;

TEST BENCH


ECED Page40

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_dflip IS

END tb_dflip;

ARCHITECTURE behavior OF tb_dflip IS

COMPONENT dflip

Port ( a,reset : in STD_LOGIC;

clk : in STD_LOGIC;

q,qbar : inout STD_LOGIC);

END COMPONENT;

--Inputs

signal a,reset : std_logic := '0';


--Outputs

signal q,qbar : std_logic;



BEGIN


uut: dflip PORT MAP (

a => a,

reset=>reset,

clk => clk,

q => q,

qbar=>qbar

);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

reset<='1';a<='0';wait for 100 ns;

reset<='0';a<='1';wait for 100 ns;

a<='0';wait for 100 ns;



end process;

END;


ECED Page41


Fig:RTL Schematic



ECED Page42



Result:

D flip flop is designed and same is verified using behavioral model.


ECED Page43

3.3T FLIP-FLOP:

Aim: To simulate t flip-flop using VHDL in process model.

Theory of Operation:If the T input is high, the flip-flop changes state ("toggles") whenever

the clock input is high. If the T input is low, the flip-flop holds the previous value.

Truth Table:

VHDL CODE

library IEEE;


entity tflipflop is

Port ( t : in STD_LOGIC;

clk : in STD_LOGIC;

reset : in STD_LOGIC;

q : out STD_LOGIC;


end tflipflop;

architecture Behavioral of tflipflop is

signal temp:std_logic;

begin

process(t,clk,reset)

begin

if (reset='1') then

temp<='0';

elsif(clk='1' and clk'event)then

case t is

when '1'=>temp<='0';

when '0'=>temp<='1';

when others=>null;

end case;

end if;

end process;

q<=temp;


ECED Page44

qbar<= not temp;

end Behavioral;

TEST BENCH

LIBRARY ieee;


ENTITY tb_tflipflop IS

END tb_tflipflop;

ARCHITECTURE behavior OF tb_tflipflop IS

COMPONENT tflipflop

PORT(

t : IN std_logic;

clk : IN std_logic;

reset : IN std_logic;

q : OUT std_logic;

qbar : OUT std_logic

);

END COMPONENT;

--Inputs

signal t : std_logic := '0';


signal reset : std_logic := '0';

--Outputs

signal q : std_logic;

signal qbar : std_logic;



BEGIN


uut: tflipflop PORT MAP (

t => t,

clk => clk,

reset => reset,

q => q,

qbar => qbar

);



begin

clk <= '1';


clk <= '0';


end process;

-- Stimulus process

stim_proc: process

begin

t<='1';reset<='1'; wait for 100 ns;


ECED Page45

t<='0';reset<='0';wait for 100 ns;

t<='0'; wait for 100 ns;



wait;

end process;

END;


Fig:RTL Schematic




ECED Page46


Result:

T flip flop is designed and same is verified using behavioral model.


ECED Page47

4.MEMORY 16 BIT

Aim: To simulate memory 16 bit using VHDL in process model .

Theory of Operation:In computing, memory refers to the physical devices used to

storeprograms (sequences of instructions) or data (e.g. program state information) on a

temporary orpermanent basis for use in a computer or other digital electronic device. This stored

data or programcan be randomly read or write by some command signal. The command signal

should be READ orWRITE.

Truth Table:

VHDL CODE

library IEEE;


entity memory is

Port ( din : in STD_LOGIC_VECTOR (15 downto 0) ;

dout : out STD_LOGIC_VECTOR (15 downto 0) ;

read1 : in STD_LOGIC;

clk : in std_logic;

writ1 : in STD_LOGIC);

end memory;

architecture Behavioral of memory is

signal memory16 : std_logic_vector(15 downto 0):=x"0000" ;

begin

process(clk)

begin

if(clk='1' and clk'event) then

if(writ1='1' and read1='0') then

memory16<=din;

elsif(read1='1' and writ1='0') then

dout<=memory16;

end if;

end if;

end process;

end Behavioral;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;LIBRARY ieee;


ENTITY tb_mem IS

END tb_mem;


ECED Page48

ARCHITECTURE behavior OF tb_mem IS


COMPONENT memory

PORT(

din : IN std_logic_vector(15 downto 0);

dout : OUT std_logic_vector(15 downto 0);

read1 : IN std_logic;

clk : IN std_logic;

writ1 : IN std_logic

);

END COMPONENT;

--Inputs

signal din : std_logic_vector(15 downto 0) := (others => '0');

signal read1 : std_logic := '0';


signal writ1 : std_logic := '0';

--Outputs

signal dout : std_logic_vector(15 downto 0);



BEGIN


uut: memory PORT MAP (

din => din,

dout => dout,

read1 => read1,

clk => clk,

writ1 => writ1

);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

din<=x"0001"; read1<='1';writ1<='0';

wait for 100 ns;

din<=x"0001"; read1<='0';writ1<='1';

wait for 100 ns;

din<=x"0010"; read1<='1';writ1<='0';


ECED Page49

wait for 100 ns;

din<=x"0011"; read1<='0';writ1<='1';

wait for 100 ns;

din<=x"0011"; read1<='1';writ1<='0';

wait for 100 ns;

end process;

END;


Fig:RTL Schematic




ECED Page50


Result:

16 bit memory is designed and same is verified using behavioral model.


ECED Page51

5. LIFO:

Aim: To simulate memory LIFO bit using VHDL in process model.

Theory of Operation:Stand for "Last In, First Out." LIFO is a method of processing data in

which the last items or data entered are the first to be removed. This is the opposite of FIFO

(First In, FirstOut)in which items are removed in the order they have been entered.

To better understand LIFO, imagine stacking a deck of cards by placing one card on topof the

other, starting from the bottom. Once the deck has been fully stacked, you begin to removethe

cards, starting from the top. This process is an example of the LIFO method, because the

lastcards to be placed on the deck are the first ones to be removed.The LIFO method is

sometimes used by computers when extracting data from an array ordata buffer.

VHDL CODE

library IEEE;


use IEEE.STD_LOGIC_Arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL;

entity lifo is

Port ( clk,pop,push : in STD_LOGIC;

stack_full,stack_empty: out std_logic;

data_in : in STD_LOGIC_VECTOR (15 downto 0);

data_out : out STD_LOGIC_VECTOR (15 downto 0));

end lifo;

architecture Behavioral of lifo is

type stack is array(7 downto 0) of std_logic_vector(15 downto 0);

signal temp:stack;

begin

write_1:process(clk,data_in,push,pop)

variable a: integer :=0;

begin

if clk'event and clk='1' then

if push='1' and pop='0' then

if a<8 then

temp(a)<= data_in;

a:=a+1;

stack_full<='0';

else

stack_full<='1';

end if;

end if;

end if;

end process write_1;

read_1:process(clk,data_in,push,pop)

variable b: integer :=7;

begin



ECED Page52

if pop='1' and push='0' then

if b>=0 then

data_out<=temp(b);

b:=b-1;

else

stack_empty<='1';

end if;

end if;

end if;

end process read_1;

end Behavioral;

TEST BENCH

LIBRARY ieee;


USE ieee.std_logic_arith.ALL;

ENTITY tb_lifo IS

END tb_lifo;

ARCHITECTURE behavior OF tb_lifo IS


COMPONENT lifo

PORT(

clk : IN std_logic;

pop : IN std_logic;

push : IN std_logic;

stack_full : OUT std_logic;

stack_empty : OUT std_logic;

data_in : IN std_logic_vector(15 downto 0);

data_out : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

--Inputs


signal pop : std_logic := '0';

signal push : std_logic := '0';

signal data_in : std_logic_vector(15 downto 0) := (others => '0');

--Outputs

signal stack_full : std_logic;

signal stack_empty : std_logic;

signal data_out : std_logic_vector(15 downto 0);



BEGIN

uut: lifo PORT MAP (


ECED Page53

clk => clk,

pop => pop,

push => push,

stack_full => stack_full,

stack_empty => stack_empty,

data_in => data_in,

data_out => data_out

);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin


data_in<=x"f123",x"E234" after 10 ns,x"D465" after 20ns,x"C398" after 30ns,

x"B638" after 40 ns,x"A629" after 50 ns,x"C192" after 60ns,

x"E340" after 70ns;

push<= '1','0' after 90 ns;

pop<= '0','1' after 90 ns;

wait;

end process;

END;


Fig:RTL Schematic


ECED Page54




Result:

LIFO is designed and same is verified using behavioral model.


ECED Page55

6. FIFO:

Aim: To simulate memory FIFO using VHDL in process model.

Theory of Operation:Stand for "First In, First Out." LIFO is a method of processing data in

which the First items or data entered are the first to be removed. This is the opposite of LIFO.To

better understand LIFO, imagine stacking a deck of cards by placing one card on topof the other,

starting from the bottom. Once the deck has been fully stacked, you begin to remove the cards,

starting from the bottom. This process is an example of the FIFO method, because thefirst cards

to be placed on the deck are the first ones to be removed.

VHDL CODE

library IEEE;


use IEEE.STD_LOGIC_Arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL;

entity fifo is

Port ( data_in: in std_logic_vector(15 downto 0);

Clk: in STD_LOGIC;

push,pop: in STD_LOGIC;

data_out : out STD_LOGIC_vector(15 downto 0);

stack_full,stack_empty: out STD_LOGIC );

end fifo ;

architecture Behavioral of lifo is

type stack is array(7 downto 0) of std_logic_vector(15 downto 0);

signal temp:stack;

begin

a1:process(data_in,clk,push,pop)

variable a: integer :=0;

begin



if a<16 then

temp(a)<= data_in ;

a:=a+1;

stack_full<='0';

else

stack_full<='1';

end if;

end if;

end if;

end process a1;

b1:process(data_in,clk,push,pop)

variable b :integer :=0;

begin




ECED Page56

if b<16 then

data_out<=temp(b);

b:=b+1;

else

stack_empty<='1';

end if;

end if;

end if;

end process b1;

end Behavioral;

TEST BENCH

LIBRARY ieee;



ENTITY tb_fifo IS

END tb_fifo;

ARCHITECTURE behavior OF tb_fifo IS

COMPONENT fifo

PORT(data_in : IN std_logic_vector(15 downto 0);

clk : IN std_logic;

push : IN std_logic;

pop : IN std_logic;

data_out : OUT std_logic_vector(15 downto 0);

stack_full : OUT std_logic;

stack_empty : OUT std_logic);

END COMPONENT;

--Inputs

signal data_in : std_logic_vector(15 downto 0) ;


signal push : std_logic := '1';

signal pop : std_logic := '0';

--Outputs

signal data_out : std_logic_vector(15 downto 0);

signal stack_full : std_logic;

signal stack_empty : std_logic;



BEGIN

uut: fifo PORT MAP

( data_in => data_in,

clk => clk,

push => push,

pop => pop,

data_out => data_out,


ECED Page57

stack_full => stack_full,

stack_empty => stack_empty);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

data_in<=x"fe00",x"ef01" after 10 ns,x"ff11" after 20 ns,x"aa10" after30ns,

x"ab01" after 40 ns,x"bc11" after 50 ns,x"cc11" after 60ns,x"cb10"

after 70 ns,x"fc11" after 80 ns,x"ff01" after 90 ns;

pop<='0','1' after 100 ns;

push<='1','0' after 100 ns;

wait;

end process;

END;


Fig:RTL Schematic


ECED Page58




Result:

FIFO is designed and same is verified using behavioral model.


ECED Page59

MODULEIII: Design the following in Structural model.

1. FULL ADDER:

Aim: To implement a full adder using VHDL in structural model.


Theory of operation: This program can add input Boolean variables A ,B and Cin.

According to that it can generates the Sum and the Carry output. It uses two XOR-gates to

generate Sum and one AND-gate, one OR-gate and one XOR-gate to generate carry.

TRUTH TABLE:

.

VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity fa_struc is

Port ( x : in STD_LOGIC;

y : in STD_LOGIC;

z : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end fa_struc;

A B CIN Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Sum=A xor B xor Cin Carry =(A and B) or (B and Cin) or (Cin and A)


ECED Page60

architecture Behavioral of fa_struc is

component halfadd_beh is


b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end component;

signal l,m,n:std_logic;

begin

ha1:halfadd_beh port map(x,y,l,m);

ha2:halfadd_beh port map(l,z,sum,n);

carry<= m or n;

end Behavioral;

Component Code

Code for half adder

library IEEE;


entity halfadd_beh is


b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end halfadd_beh;

architecture Behavioral of halfadd_beh is

begin

process(a,b)

begin

if(a='0' and b='0') then s<='0';c<='0';

elsif(a='0' and b='1') then s<='1';c<='0';



end if;

end process;

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_fa_struc IS


ECED Page61

END tb_fa_struc;

ARCHITECTURE behavior OF tb_fa_struc IS


COMPONENT fa_struc

PORT(

x : IN std_logic;

y : IN std_logic;

z : IN std_logic;

sum : OUT std_logic;

carry : OUT std_logic

);

END COMPONENT;

--Inputs

signal x : std_logic := '0';

signal y : std_logic := '0';

signal z : std_logic := '0';

--Outputs

signal sum : std_logic;

signal carry : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN


uut: fa_struc PORT MAP (

x => x,

y => y,

z => z,

sum => sum,

carry => carry

);


-- Stimulus process

stim_proc: process

begin

x<='0';y<='0';z<='0';wait for 100 ns;

x<='0';y<='0';z<='1';wait for 100 ns;

x<='0';y<='1';z<='0';wait for 100 ns;

x<='0';y<='1';z<='1';wait for 100 ns;

x<='1';y<='0';z<='0';wait for 100 ns;

x<='1';y<='0';z<='1';wait for 100 ns;

x<='1';y<='1';z<='0';wait for 100 ns;

x<='1';y<='1';z<='1';wait for 100 ns;

end process;


ECED Page62

END;


Fig:RTL Schematic


ECED Page63




Result:

The full adder is designed and same is verified using structural model.


ECED Page64

2. 4 BIT BINARY ADDER:

Aim: To implement a 4 bit binary adder using VHDL in structural model.


Theory of operation: A full adder is capable of adding two 1-bit binary numbers and a

carry-in. Whentwo N-bit binary numbers are to be added, the number of full adder required will

be equal to thenumber of bits N in each number. So the 4-bit binary adder required 4 full adders.

In which thecarry out of each full adder is the carry in of next higher order full adder. A parallel

adder is usedto add two numbers in parallel form and to produce the sum bits as parallel outputs.

VHDL Code

library IEEE;


entity binadd_stru is

port(x:in std_logic_vector (3 downto 0);

y:in std_logic_vector (3 downto 0);

zin:in std_logic;

rst1:in std_logic;

s1:out std_logic_vector (3 downto 0);

c1:out std_logic

);

end binadd_stru;

architecture Behavioral of binadd_stru is

component fulladd_beh is

port(a,b,cin,rst : in std_logic;

sum,carry : out std_logic);

end component;

signal temp:std_logic_vector(2 downto 0);

begin

fa1:fulladd_beh port map(x(0),y(0),zin,rst1,s1(0),temp(0));

fa2:fulladd_beh port map(x(1),y(1),temp(0),rst1,s1(1),temp(1));

fa3:fulladd_beh port map(x(2),y(2),temp(1),rst1,s1(2),temp(2));

fa4:fulladd_beh port map(x(3),y(3),temp(2),rst1,s1(3),c1);

end Behavioral;


ECED Page65

Component Code

Code for Full adder

library IEEE;


entity fulladd_beh is

port(a,b,cin,rst : in std_logic;

sum,carry : out std_logic);

end fulladd_beh;

architecture Behavioral of fulladd_beh is

begin

process(a,b,cin,rst)

begin

if(a='0' and b='0' and cin='0') then sum<='0';carry<='0';

elsif(a='0' and b='0' and cin='1') then sum<='1';carry<='0';







end if;

end process;

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_binadd_stru IS

END tb_binadd_stru;

ARCHITECTURE behavior OF tb_binadd_stru IS


COMPONENT binadd_stru

PORT(

x : IN std_logic_vector(3 downto 0);

y : IN std_logic_vector(3 downto 0);

zin : IN std_logic;


ECED Page66

rst1 : IN std_logic;

s1 : OUT std_logic_vector(3 downto 0);

c1 : OUT std_logic

);

END COMPONENT;

--Inputs

signal x : std_logic_vector(3 downto 0) := (others => '0');

signal y : std_logic_vector(3 downto 0) := (others => '0');

signal zin : std_logic := '0';

signal rst1 : std_logic := '0';

--Outputs

signal s1 : std_logic_vector(3 downto 0);

signal c1 : std_logic;

BEGIN


uut: binadd_stru PORT MAP (

x => x,

y => y,

zin => zin,

rst1 => rst1,

s1 => s1,

c1 => c1

);

-- Stimulus process

stim_proc: process

begin

rst1<='1';wait for 100 ns;rst1<='0';

x<="0001";y<="0001";wait for 100 ns;

x<="0011";y<="0001";wait for 100 ns;

x<="0101";y<="0001";wait for 100 ns;

x<="0001";y<="0111";wait for 100 ns;

x<="0001";y<="0001";wait for 100 ns;

x<="1001";y<="0001";wait for 100 ns;

x<="1101";y<="0001";wait for 100 ns;

x<="1101";y<="0001";wait for 100 ns;

x<="1101";y<="0001";wait for 100 ns;

x<="1111";y<="0001";wait ;

end process;

END;



ECED Page67

Fig:RTL Schematic



ECED Page68



Result:

The 4 bit binary adder is designed and same is verified using structural model.


ECED Page69

3. 4 BIT COUNTER:

Aim: To implement a 4 bit counter using VHDL in structural model.


Theory of operation: A binary counter is a machine (like a computer) which counts in

binary. A counter is a device which stores (and sometimes displays) the number of times

aparticular event or processhas occurred, often in relationship to a clock signal. A digital circuit

which has a clock input anda number of count outputs which give the number of clock cycles.

The output may change eitheron rising or falling clock edges. The circuit may also have a reset

input which sets all outputs tozero when asserted.

TRUTH TABLE:

VHDL Code

library IEEE;


entity SUN_DOWN_COU is

Port ( J,K,PRE,RT,CLK : in STD_LOGIC;

Q,Qbar : inout STD_LOGIC_VECTOR (3 downto 0));

end SUN_DOWN_COU;

architecture Behavioral of SUN_DOWN_COU is

signal s1,s2,s3: STD_LOGIC;


ECED Page70

component JK_FF

Port ( J,K,PRE,RT,CLK : in STD_LOGIC;

Q,Qbar : inout STD_LOGIC);

end component;

component And_gate_2_input

port (a,b: in std_logic;

Z: out std_logic);

end component;

begin

s1<=Qbar(0);

TS5: And_gate_2_input port map(Q(1),Q(0),s2);

TS6: And_gate_2_input port map(s2,Q(2),s3);

TS1: JK_FF port map('1','1',PRE,RT,CLK,Q(0),Qbar(0));

TS2: JK_FF port map(s1,s1,PRE,RT,CLK,Q(1),Qbar(1));



end Behavioral;

Component Code

Code for JK Flip Flop

library IEEE;


entity JK_FF is

Port ( J,K,preset,rst,clk : in STD_LOGIC;

Q,Qbar : out STD_LOGIC);

end JK_FF;

architecture Behavioral of JK_FF is

signal w: std_logic:='0';

begin

JK_FF: process(preset,rst,clk,J,K)

begin

if preset='0' and rst='1' then

w<= '0';

elsif preset='1' and rst='0' then

w<= '1';


w<= 'X';

elsif clk='1' and clk'event then


if J='0' and K='0' then

w<=w;


ECED Page71

elsif J='0' and K='1' then

w<='0';


w<='1';


w<= not w;

end if;

end if;

end if;

end process;

Q<=w;

Qbar<= not w;

end Behavioral;

Code for AND gate

library IEEE;


entity And_gate_2_input is

Port ( A,B : in STD_LOGIC;

Z : out STD_LOGIC);

end And_gate_2_input;

architecture Behavioral of And_gate_2_input is

begin

Z<= A and B;

end Behavioral;

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;ENTITY tb_SUN_DOWN_COU IS

END tb_SUN_DOWN_COU;

ARCHITECTURE behavior OF tb_SUN_DOWN_COU IS


COMPONENT SUN_DOWN_COU

PORT(

J : IN std_logic;

K : IN std_logic;

PRE : IN std_logic;

RT : IN std_logic;

CLK : IN std_logic;

Q : INOUT std_logic_vector(3 downto 0);

Qbar : INOUT std_logic_vector(3 downto 0)

);


ECED Page72

END COMPONENT;

--Inputs

signal J : std_logic := '0';

signal K : std_logic := '0';

signal PRE : std_logic := '0';

signal RT : std_logic := '0';

signal CLK : std_logic := '0';

--BiDirs

signal Q : std_logic_vector(3 downto 0);

signal Qbar : std_logic_vector(3 downto 0);


constant CLK_period : time := 10 ns;

BEGIN


uut: SUN_DOWN_COU PORT MAP (

J => J,

K => K,

PRE => PRE,

RT => RT,

CLK => CLK,

Q => Q,

Qbar => Qbar

);


CLK_process :process

begin

CLK <= '0';

wait for CLK_period/2;

CLK <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

RT<='1','0' after 50 ns;

PRE<= '0','0' after 50 ns;

wait;

end process;

END;



ECED Page73

Fig:RTL Schematic



ECED Page74



Result:

The 4 bit counter is designed and same is verified using structural model.


ECED Page75

4. 4 BIT COUNTERS(Generate):

Aim: To implement a 4 bit counter using VHDL in structural model.


Theory of operation: A binary counter is a machine (like a computer) which counts in

binary. A counter is a device which stores (and sometimes displays) the number of times a

particular event or processhas occurred, often in relationship to a clock signal. A digital circuit

which has a clock input anda number of count outputs which give the number of clock cycles.

The output may change eitheron rising or falling clock edges. The circuit may also have a reset

input which sets all outputs tozero when asserted.

TRUTH TABLE:

.


ECED Page76

VHDL Code

library IEEE;


entity counter_gen is

Port ( clk : in STD_LOGIC;

dout : out STD_LOGIC_VECTOR (3 downto 0) ;

dbarout : out STD_LOGIC_VECTOR (3 downto 0)) ;

end counter_gen;

architecture Behavioral of counter_gen is

component JK_FF is

Port ( J,K: in STD_LOGIC;

preset,rst: in STD_LOGIC :='0';

clk : in STD_LOGIC;


end component;

signal s :std_logic;

signal clk1:std_logic_vector(4 downto 0);

begin

s<='1';

dout<=clk1(4 downto 1);

clk1(0)<=clk;

G1: for i in 0 to 3 generate

F1: JK_FF port map(J=>s,K=>s,clk=>clk1(i),Q=>clk1(i+1),Qbar=>dbarout(i));

end generate G1;

end Behavioral;

Component Code

Code for JK Flip Flop

library IEEE;


entity JK_FF is

Port ( J,K,preset,rst,clk : in STD_LOGIC;


end JK_FF;

architecture Behavioral of JK_FF is

signal w: std_logic:='0';

begin

JK_FF: process(preset,rst,clk,J,K)

begin


w<= '0';



ECED Page77

w<= '1';


w<= 'X';



if J='0' and K='0' then

w<=w;


w<='0';


w<='1';


w<= not w;

end if;

end if;

end if;

end process;

Q<=w;

Qbar<= not w;

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_count_gen IS

END tb_count_gen;

ARCHITECTURE behavior OF tb_count_gen IS


COMPONENT counter_gen

PORT(

clk : IN std_logic;

dout : OUT std_logic_vector(3 downto 0);

dbarout : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs


--Outputs


signal dbarout : std_logic_vector(3 downto 0);



BEGIN


uut: counter_gen PORT MAP (

clk => clk,


ECED Page78

dout => dout,

dbarout => dbarout

);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

clk <= '0';


clk <= '1';


end process;

END;


Fig:RTL Schematic


ECED Page79




Result:

The 4 bit counter using generate is designed and same is verified using structural model.


ECED Page80

5. 4 BIT SHIFT REGISTER:

Aim: To implement a 4 bit shift register using VHDL in structural model.


Theory of operation: Shift registers are a type of sequential logic circuit, mainly for storage

ofdigital data. They are a group of flip-flops connected in a chain so that the output from oneflip-

flop becomes the input of the next flip-flop. Most of the registers possess nocharacteristic

internal sequence of states. All flip flops are driven by a common clock, and all are set or reset

simultaneously.

VHDL Code

library IEEE;


entity SHIFT_REGISTER is

Port ( D,CLK,RT,PRE : in STD_LOGIC;

SHIFT : inout STD_LOGIC);

end SHIFT_REGISTER;

architecture Behavioral of SHIFT_REGISTER is

Component D_FF

Port ( CLK : in STD_LOGIC;

RESET : in STD_LOGIC;

PRESET: in STD_LOGIC;

DATA : in STD_LOGIC;


end component;

signal S:STD_LOGIC_VECTOR(7 downto 0);

begin

TS1: D_FF port map (CLK,RT,PRE,D,S(0),S(4));

TS2: D_FF port map (CLK,RT,PRE,S(0),S(1),S(5));

TS3: D_FF port map (CLK,RT,PRE,S(1),S(2),S(6));

TS4: D_FF port map (CLK,RT,PRE,S(2),SHIFT,S(7));

end Behavioral;


ECED Page81

Counter Component Code

D- Flip Flop Code

library IEEE;


entity D_FF is






end D_FF;

architecture Behavioral of D_FF is

begin

process( CLK,RESET)

begin

if PRESET='1' and RESET='0' then

Q<='1';

elsif PRESET='0' and RESET='1' then

Q<='0';


Q<='X';


if CLK='1' and CLK'event then

Q<=DATA; else

Q<=Q;

end if;

end if;

end process;

Qbar<= not Q;

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_SHIFT_REGISTER IS

END tb_SHIFT_REGISTER;

ARCHITECTURE behavior OF tb_SHIFT_REGISTER IS

COMPONENT SHIFT_REGISTER


ECED Page82

PORT( D : IN std_logic;

CLK : IN std_logic;

RT : IN std_logic;

PRE : IN std_logic;

SHIFT: inOUT std_logic);

END COMPONENT;

--Inputs

signal D : std_logic := '0';




--BiDirs

signal SHIFT: std_logic;



BEGIN

uut: SHIFT_REGISTER PORT MAP

( D => D,

CLK => CLK,

RT => RT,

PRE => PRE,

SHIFT => SHIFT );



begin

CLK <= '0';


CLK <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

RT<='1','0' after 10 ns;

PRE<='0','1' after 10 ns,'0' after 20 ns;

D<='0' after 20 ns,'1' after 110 ns,'0' after 120 ns;

wait;

end process;


ECED Page83


Fig:RTL Schematic



ECED Page84



Result:

The 4 bit shift register is designed and same is verified using structural model.


ECED Page85

6. 4 BIT RING COUNTER:

Aim: To implement a 4 bit ring counter using VHDL in structural model.


Theory of operation: A ring counter is a Shift Register (a cascade connection of flip-flops)

with the output of the last flip flop connected to the input of the first. It is initialized such that

only one of the flip flop output is 1 while remain is 0. The 1 bit is circulated so the state repeats

every n clock cycles if n flip-flops are used. The "MOD" or "MODULUS" of a counter is the

number of unique states. The MOD of the n flip flop ring counter is n.

It can be implemented using D-type flip.

TRUTH TABLE:


ECED Page86

VHDL Code

library IEEE;


entity RING_COUNTER_4_BIT is

Port ( D,CLK,RT,PRE : in STD_LOGIC;

Q,Qbar : inout STD_LOGIC_VECTOR (3 downto 0));

end RING_COUNTER_4_BIT;

architecture Behavioral of RING_COUNTER_4_BIT is

component D_FF






end component;

begin

TS1: D_FF port map (CLK,RT,PRE,Q(3),Q(0),Qbar(0));

TS2: D_FF port map (CLK,RT,'0',Q(0),Q(1),Qbar(1));



end Behavioral;

Ring Counter Component Code

D- Flip Flop Code

library IEEE;


entity D_FF is






end D_FF;

architecture Behavioral of D_FF is

begin

process( CLK,RESET)

begin


Q<='1';


Q<='0';


Q<='X';



Q<=DATA;


ECED Page87

else

Q<=Q;

end if;

end if;

end process;

Qbar<= not Q;

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_RING_COUNTER_4_BIT IS

END tb_RING_COUNTER_4_BIT;

ARCHITECTURE behavior OF tb_RING_COUNTER_4_BIT IS


COMPONENT RING_COUNTER_4_BIT

PORT(D : IN std_logic;

CLK : IN std_logic;

RT : IN std_logic;

PRE : IN std_logic;


Qbar : INOUT std_logic_vector(3 downto 0) );

END COMPONENT;

--Inputs





--BiDirs





BEGIN

uut: RING_COUNTER_4_BIT PORT MAP

(D => D,

CLK => CLK,

RT => RT,

PRE => PRE,

Q => Q,

Qbar => Qbar );



begin

CLK <= '0';


CLK <= '1';


end process;


ECED Page88

-- Stimulus process

stim_proc: process

begin

PRE<='1' after 10 ns,'0' after 20 ns;

RT<='1', '0' after 10 ns;

wait;

end process;

END;


Fig:RTL Schematic


ECED Page89




Result:

The 4 bit Ring counter is designed and same is verified using structural model.


ECED Page90

7. 4 BIT TWISTED COUNTER:

Aim: To implement a 4 bit twisted counter using VHDL in structural model.


Theory of operation: A Johnson counter is a modified ring counter, where the inverted

output from the last flip flop is connected to the input to the first. The register cycles through a

sequence of bitpatterns.The MOD of the Johnson counter is 2n if n flip-flops are used. The main

advantage ofthe Johnson counter is that it only needs half the number of flip-flops compared to

the standardring counter for the same MOD.

It can be implemented using D-type flip-flops.


ECED Page91

TRUTH TABLE:

VHDL Code

library IEEE;


entity JOHN_COUNTER is

Port ( D,CLK,PRE,RT : in STD_LOGIC;

Q,Qbar : inout STD_LOGIC_VECTOR (3 downto 0)); end JOHN_COUNTER;

architecture Behavioral of JOHN_COUNTER is

component D_FF






end component;

end component;

begin

TS1: D_FF port map (CLK,RT,'0',Qbar(3),Q(0),Qbar(0));




end Behavioral;

Johson Counter Component Code

Code for D-Flip Flop

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity D_FF is




ECED Page92




end D_FF;

end D_FF;

architecture Behavioral of D_FF is begin

process( CLK,RESET) begin


Q<='1';


Q<='0';


Q<='X';



Q<=DATA;

else

Q<=Q;

end if; end if; end process;

Qbar<= not Q;

end Behavioral;

Test Bench

LIBRARY ieee;


ENTITY tb_JOHN_COUNTER IS

END tb_JOHN_COUNTER;

ARCHITECTURE behavior OF tb_JOHN_COUNTER IS


COMPONENT JOHN_COUNTER

PORT(D : IN std_logic;

CLK : IN std_logic;

PRE : IN std_logic;

RT : IN std_logic;


Qbar : INOUT std_logic_vector(3 downto 0) );

END COMPONENT;

--Inputs





--BiDirs




ECED Page93



BEGIN


uut: JOHN_COUNTER PORT MAP

( D => D,

CLK => CLK,

PRE => PRE,

RT => RT,

Q => Q,

Qbar => Qbar);



begin

CLK <= '0';


CLK <= '1';


end process;

-- Stimulus process stim_proc: process

begin

RT<='1','0' AFTER 10 ns;

wait;

end process;

END;


Fig:RTL Schematic


ECED Page94




Result:

The John Son(twisted ring counter) is designed and same is verified using structural model.


ECED Page95

MODULE IV: RAMMemory

Aim: To simulate memory 16x4 using VHDL in process model.

Theory of Operation:Stand Random-access memory (RAM) is a form of computer data

storage. A random-access device allows stored data to be accessed directly in any random order.

Randomaccess memory, or RAM, allows us to store even larger amounts of data.

The basic capabilities of a memory:

– It should be able to store a value.

– We should be able to read the value that was saved.

– We should be able to change the stored value.

A RAM is similar, except that it can store many values.

– An address will specify which memory value we’re interested in.

– Each value can be a multiple-bit word.

A RAM should be able to:

- Store many words, one per address.

-Read the word that was saved at a particular address.

- Change the word that’s saved at a particular address.

– A Chip Select, CS, enables or disables the RAM.

– Address specifies the address or location to read from or write to.

– WR and RD selects between reading from or writing to the memory.

To write from memory, WR should be set to 1 and RD should be set to 0.

To read from memory, WR should be set to 0 and RD should be set to 1.

VHDL CODE library IEEE;


use IEEE.STD_LOGIC_Arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity RAM is

Port ( INP_DATA : in STD_LOGIC_VECTOR (3 downto 0);

ADDRESS : in STD_LOGIC_VECTOR (3 downto 0);

CLK,RT,CE,WR,RD : in STD_LOGIC;

OPT_DATA : out STD_LOGIC_VECTOR (3 downto 0));

end RAM;


ECED Page96

architecture Behavioral of RAM is

signal POSITION : integer range 0 to 15;

type RAM_ARRAY is array (0 to 15) of STD_LOGIC_VECTOR(3 downto 0);

signal temp: RAM_ARRAY;

begin

POSITION<= (CONV_integer(ADDRESS));

process (CLK,RT,WR,RD,CE)

begin

if (CE='0' and RT='0') then

OPT_DATA<="ZZZZ";

elsif (CE='0' and RT='1') then

OPT_DATA<="ZZZZ";



if WR='1' and RD='0' then

temp(position)<=INP_DATA;

elsif WR='0' and RD='1' then

OPT_DATA<=temp(position);

end if;

else

temp(position)<=temp(position);

end if;

end if;

end process;

end Behavioral;

TEST BENCH

LIBRARY ieee;



ENTITY tb_RAM IS

END tb_RAM;

ARCHITECTURE behavior OF tb_RAM IS

COMPONENT RAM

PORT(INP_DATA : IN std_logic_vector(3 downto 0);

ADDRESS : IN std_logic_vector(3 downto 0);

CLK : IN std_logic;

RT : IN std_logic;

CE : IN std_logic; WR : IN std_logic;

RD : IN std_logic;

OPT_DATA : OUT std_logic_vector(3 downto 0) );

END COMPONENT;

--Inputs

signal INP_DATA : std_logic_vector(3 downto 0):=(others => '0');

signal ADDRESS : std_logic_vector(3 downto 0):=(others => '0');



ECED Page97


signal CE : std_logic := '0';

signal WR : std_logic := '0';

signal RD : std_logic := '0';

--Outputs

signal OPT_DATA : std_logic_vector(3 downto 0);



BEGIN

uut: RAM PORT MAP

( INP_DATA => INP_DATA,

ADDRESS => ADDRESS,

CLK => CLK,

RT => RT,

CE => CE,

WR => WR,

RD => RD,

OPT_DATA => OPT_DATA);



begin

CLK <= '0';


CLK <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

RT<='1','0' after 10 ns;

CE<='0' after 5 ns,'1' after 10 ns;

WR<='1' after 20 ns,'0' after 100 ns;

RD<='1' after 100 ns;

ADDRESS<=X"0",X"1" after 20 ns,X"A" after 30 ns,X"5" after 40ns,X"4" after 50

ns,X"3" after 60 ns,X"8" after 70 ns,X"6" after 80 ns,X"7" after 90 ns,X"9"

after 100 ns,X"0" after 110 ns,X"6" after 120 ns,X"1" after 130 ns,X"7" after

140 ns,X"A" after 150 ns;

INP_DATA<=X"0",X"A" after 20 ns,X"F" after 30 ns,X"C" after 40 ns,X"E" after

50 ns,X"2" after 60 ns,X"A" after 70 ns,X"B" after 80 ns,X"6" after 90

ns,X"5" after 100 ns,X"8" after 110 ns,X"4" after 120 ns,X"D" after 130

ns,X"1" after 140 ns,X"9" after 150 ns;

wait;

end process;

END;


ECED Page98


Fig:RTL Schematic



Result:

16x4 memory is designed and same is verified using behavioral model.


ECED Page99

MODULEV: 64 X 8 Memory

Aim: To simulate memory 64x8 using VHDL in process model.

Theory of Operation:The 64 X 8 memory can be making by using 16 X 4 RAM. In which

the 2-bit MSB of address line are uses as the chip enable signal to enable the RAM out of eight

16 X 8 RAM

VHDL CODE library IEEE;


use IEEE.STD_LOGIC_Arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

library work;

entity MEMORY_64X8 is

Port ( IP_DATA : in STD_LOGIC_VECTOR (7 downto 0);

CLK,WT,RD,CE,RT : in STD_LOGIC;

OUT_DATA : out STD_LOGIC_VECTOR (7 downto 0);

ADDRESS : in STD_LOGIC_VECTOR (5 downto 0));

end MEMORY_64X8;

architecture Behavioral of MEMORY_64X8 is

signal P: STD_LOGIC_VECTOR(3 downto 0);

component RAM





end component;

for all: RAM use entity WORK.RAM(Behavioral);

begin

TS:for I in 0 to 3 generate

with I select

P(I) <= ((NOT ADDRESS(5)) and (NOT ADDRESS(4)))and CE when 0,(NOT ADDRESS(5)

and ADDRESS(4)) and CE when 1,(ADDRESS(5) and (NOT ADDRESS(4))) and CE when

2,( ADDRESS(5) and ADDRESS(4)) and CE when others;

TS1: RAM port map (IP_DATA(3 downto 0),ADDRESS(3 downto0),CLK,RT,P(I),WT,RD,

OUT_DATA(3 downto 0));

TS2: RAM port map (IP_DATA(7 downto 4),ADDRESS(3 downto 0),CLK,RT,P(I),WT,RD,

OUT_DATA(7 downto 4));

end generate TS;


ECED Page100

end Behavioral;

Component Code

Code for RAM: library IEEE;


use IEEE.std_logic_unsigned.all;

entity RAM is





end RAM;

architecture Behavioral of RAM is

signal POSITION : integer range 0 to 15;

type RAM_ARRAY is array (0 to 15) of STD_LOGIC_VECTOR(3 downto 0);

signal temp: RAM_ARRAY;

begin

POSITION<= (CONV_integer(ADDRESS));

process (CLK,RT,WR,RD,CE)

begin

if (CE='0' and RT='0') then

OPT_DATA<="ZZZZ";


OPT_DATA<="ZZZZ";



if WR='1' and RD='0' then

temp(position)<=INP_DATA;

elsif WR='0' and RD='1' then

OPT_DATA<=temp(position);

end if;

else

temp(position)<=temp(position);

end if;

end if;

end process;

end Behavioral;

TEST BENCH

LIBRARY ieee;



ENTITY tb_MEMORY_64X8 IS


ECED Page101

END tb_MEMORY_64X8;

ARCHITECTURE behavior OF tb_MEMORY_64X8 IS

COMPONENT MEMORY_64X8

PORT(IP_DATA : IN std_logic_vector(7 downto 0);

CLK : IN std_logic;

WT : IN std_logic;

RD : IN std_logic;

CE : IN std_logic;

RT : IN std_logic;

OUT_DATA : OUT std_logic_vector(7 downto 0);

ADDRESS : IN std_logic_vector(5 downto 0) );

END COMPONENT;

--Inputs

signal IP_DATA : std_logic_vector(7 downto 0):= (others => '0');


signal WT : std_logic := '0';

signal RD : std_logic := '0';

signal CE : std_logic := '0';


signal ADDRESS : std_logic_vector(5 downto 0):= (others => '0');

--Outputs

signal OUT_DATA : std_logic_vector(7 downto 0);



BEGIN

uut: MEMORY_64X8 PORT MAP

( IP_DATA => IP_DATA,

CLK => CLK,

WT => WT,

RD => RD,

CE => CE,

RT => RT,

OUT_DATA => OUT_DATA,

ADDRESS => ADDRESS);



begin

CLK <= '0';


CLK <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

IP_DATA<=X"10" after 10 ns,X"15" after 20 ns,X"A0" after 30ns,

X"1B" after 40 ns,X"1F" after 50 ns,X"16" after 60 ns,

X"F0" after 70 ns,X"1C" after 80 ns,X"AC" after 90 ns,

X"10" after 100 ns,X"B0" after 110 ns,X"AF" after 120 ns,


ECED Page102

X"BD" after 130 ns,X"1F" after 140 ns,X"0C" after 150ns;

WT<='1' after 10 ns,'0' after 130 ns;

RD<='1' after 130 ns;

CE<='0','1' after 10 ns;

RT<='1','0' after 10 ns;

ADDRESS<="001010","001011" after 20 ns,"000111" after 30 ns,"011000" after 40

ns,"011111" after 50 ns,"011001"after 60 ns,"100011" after 70 ns,"100001"

after 80 ns,"101011" after 90 ns,"101101" after 100 ns,"110111" after 110

ns,"110101" after 120 ns,"111001" after 130ns,"001011" after 140ns,"011111"

after 150 ns,"100011"after 160 ns,"110111" after 170 ns;wait;

end process;

END;


Fig:RTL Schematic



Result:

64x8 memory is designed and same is verified using behavioral model.


ECED Page103

MODULE VI: Use a FF as a component the design of which is placed in another

library. Bind it using a configuration, and design a 16 bit counter.

VI.16 BIT COUNTER USING CONFIGURATION

Aim: To design a 16 bit counter and bind it using a configuration.


VHDL Code

library IEEE;


library ff_lib;

entity counter16bit is

generic (n:natural:=16);

port(rst:in std_logic;

clk:in std_logic;

set:in std_logic;

dout:out std_logic_vector((n-1) downto 0)

);

end counter16bit;

architecture Behavioral of counter16bit is

component tff is


set : in STD_LOGIC;


clk : in STD_LOGIC;

q : out STD_LOGIC;


end component;

signal a:std_logic_vector((n-1) downto 0);

signal b:std_logic_vector((n-1) downto 0);

for all:tff use entity ff_lib.tff(Behavioral);

begin

generate_x:for i in 0 to (n-1) generate

tff_1:if i=0 generate

U1 : tff port map('1',set,rst,clk,a(i),b(i));

end generate tff_1;

tff_n:if i>0 generate

U2 : tff port map('1',set,rst,b(i-1),a(i),b(i));

end generate tff_n;

end generate generate_x;

dout<=a;

end Behavioral;


ECED Page104

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;ENTITY tb_counter16bit IS

END tb_counter16bit;

ARCHITECTURE behavior OF tb_counter16bit IS


COMPONENT counter16bit

PORT(

rst : IN std_logic;

clk : IN std_logic;

set : IN std_logic;

dout : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

--Inputs

signal rst : std_logic := '0';


signal set : std_logic := '0';

--Outputs




BEGIN


uut: counter16bit PORT MAP (

rst => rst,

clk => clk,

set => set,

dout => dout

);



begin

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

set<='0'; rst<='1'; wait for 10 ns;

set<='1'; rst<='0'; wait for 10 ns;

wait;

end process;


ECED Page105

END;

Component Code

Code for tff which is residing inside ff_lib library(user

defined)

library IEEE;


entity tff is


set : in STD_LOGIC;


clk : in STD_LOGIC;

q : out STD_LOGIC;


end tff;

architecture Behavioral of tff is

signal temp:std_logic;

begin

process(clk)

begin

if clk='1' and clk'event then

if set='1' then

temp<='1';

elsif reset='1' then

temp<='0';

else

temp<=temp xor t;

end if;

end if;

end process;

q<=temp;

qbar<=not temp;

end Behavioral;


Fig:RTL Schematic


ECED Page106




Result:

The 16 bit counter is designed using TFF and bound by configuration and same is verified using

ISim.


ECED Page107

MODULE VII: Write a number of functions and store in a package .Use these

functions from a different design library (find applications to use the functions)

The functions are

a) Conversion from bit vector to integer and vice versa.

b) Counting the number of zeros (and number of ones) in a 16 bit word.

c) Finding the biggest of 10 integers

A.CONVERSION FROM BIT VECTOR TO INTEGER AND VICE VERSA

Aim: To convert bit vector to integer and vice versa


Package my_pack Code

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

USE IEEE.STD_LOGIC_UNSIGNED.all;

package my_pack1 is

function int_bit(a:in integer) return std_logic_vector;

function bit_int(a:in std_logic_vector(7 downto 0)) return integer;

function no_1(a:in integer) return integer;

function no_0(a:in integer) return integer;

type integer_Array is array(9 downto 0) of integer;

function Find_Largest(signal input : integer_Array ) return integer;

end my_pack1;

package body my_pack1 is

function int_bit(a:in integer) return std_logic_vector is

variable bit_value:std_logic_vector(7 downto 0);

variable temp:integer:=0;

begin

temp:=a;

for i in 0 to 7 loop

if(temp mod 2=0) then

bit_value(i):='0';

else

bit_value(i):='1';

end if;


ECED Page108

temp:=temp/2;

end loop;

return bit_value;

end int_bit;

function bit_int(a:in std_logic_vector(7 downto 0)) return integer is

variable result:integer:=0;

begin


if(a(i)='1')then

result:=result+(2**i);

end if;

end loop;

return result;

end bit_int;

function no_1(a:in integer) return integer is

variable count:integer:=0;

variable temp:integer;

begin

temp:=a;



count:=count+1;

else

count:=count;

end if;

temp:=temp/2;

end loop;

return count;

end no_1;

function no_0(a:in integer) return integer is

variable count:integer:=0;

variable temp:integer;

begin

temp:=a;



count:=count+1;

else

count:=count;

end if;

temp:=temp/2;

end loop;

return count;

end no_0;

function Find_Largest(signal input : integer_Array )

return integer is

variable RESULT: integer ;

begin

RESULT:= input(0);



ECED Page109

if input(i) > RESULT then

RESULT := input(i);

end if;

end loop;

return RESULT;

end Find_Largest;

end my_pack1;

VHDL Code

LIBRARY ieee;




library my_lib1;

use my_lib1.my_pack1.all; entity package1 is

port (

int_in: in integer;

int_out: out integer;

bit_in:in std_logic_vector(7 downto 0);

bit_out:out std_logic_vector(7 downto 0);

no1_in: in integer;

no1_out:out integer;

no0_in: in integer;

no0_out:out integer;

inputs: in integer_Array;

output: out integer

);

end package1;

architecture Behavioral of package1 is

begin

int_out<=bit_int(bit_in);

bit_out<=int_bit(int_in);

no1_out<=no_1(no1_in);

no0_out<=no_0(no0_in);

output<=Find_Largest(inputs);

end Behavioral;

Test Bench

LIBRARY ieee;




library my_lib1;

use my_lib1.my_pack1.all;


ECED Page110

ENTITY tb_package1 IS

END tb_package1;

ARCHITECTURE behavior OF tb_package1 IS


COMPONENT package1

PORT(

int_in : IN integer;

int_out : OUT integer;

bit_in : IN std_logic_vector(7 downto 0);

bit_out : OUT std_logic_vector(7 downto 0);

no1_in : IN integer;

no1_out : OUT integer;

no0_in : IN integer;

no0_out : OUT integer;

inputs : IN integer_Array;

output : OUT integer

);

END COMPONENT;

--Inputs

signal int_in : integer ;

signal bit_in : std_logic_vector(7 downto 0) := (others => '0');

signal no1_in :integer ;

signal no0_in : integer ;

signal inputs : integer_Array;

--Outputs

signal int_out : integer;

signal bit_out : std_logic_vector(7 downto 0);

signal no1_out : integer;

signal no0_out : integer;

signal output : integer;



-- constant <clock>_period : time := 10 ns;

BEGIN


uut: package1 PORT MAP (

int_in => int_in,

int_out => int_out,

bit_in => bit_in,

bit_out => bit_out,

no1_in => no1_in,

no1_out => no1_out,

no0_in => no0_in,

no0_out => no0_out,

inputs => inputs,

output => output

);


ECED Page111


-- Stimulus process

stim_proc: process

begin


bit_in<="10001001";

int_in<=45;

no1_in<=21;

no0_in<=22;

inputs(0) <=10 ; inputs(1) <=8 ;inputs(2) <=21 ;inputs(3) <=24 ;

inputs(5) <=35 ;inputs(9) <=99 ;inputs(4) <=88 ;inputs(8) <=75 ;

inputs(7) <=71 ;inputs(6) <=35 ;

wait for 100ns;

wait;

end process;

END;




ECED Page112



Result:

The given functions are designed and same are verified using ISim.


ECED Page113

MODULE VIII: Design the following as state machines

a) Up/down counter counting from 0 to 5.

b) A clock serial adder for four bits

c) A sequence detector to detect the sequence 1001.

A) UP/DOWN COUNTER COUNTING FROM 0 TO 5.

Aim: To design Up/down counter counting from 0 to 5.


VHDL Code

library IEEE;




entity updownfsm is


rst : in STD_LOGIC;

ud : in STD_LOGIC;

count : out STD_LOGIC_Vector(2 downto 0));

end updownfsm;

architecture Behavioral of updownfsm is

type state_type is (s0,s1,s2,s3,s4,s5);

signal state:state_type:=s0;

begin

process(clk,rst,ud)

begin

if rst='1' then state<=s0;count<="000";


case state is

when s0=> if ud='1' then state<=s1;count<="001";

else state<=s5;count<="101";

end if;



end if;



end if;



end if;



end if;



ECED Page114


end if;

when others => null;

end case;

end if;

end process;

end Behavioral;

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_updown2 IS

END tb_updown2;

ARCHITECTURE behavior OF tb_updown2 IS


COMPONENT updownfsm

PORT(

clk : IN std_logic;

rst : IN std_logic;

ud : IN std_logic;

count : OUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs



signal ud : std_logic := '0';

--Outputs

signal count : std_logic_vector(2 downto 0);



BEGIN


uut: updownfsm PORT MAP (

clk => clk,

rst => rst,

ud => ud,

count => count

);



begin


ECED Page115

clk <= '0';


clk <= '1';


end process;

-- Stimulus process

stim_proc: process

begin

rst<='1';wait for 10 ns;

rst<='0';

ud<='1'; wait for 70 ns;

ud<='0'; wait for 70 ns;

end process;

END;


Fig:RTL Schematic


ECED Page116




Result:

The Up/down counter counting from 0 to 5 is designed and same is verified using ISim.


ECED Page117

B.CLOCK SERIAL ADDER FOR FOUR BITS.

Aim: To design a clock serial adder for four bits.


VHDL Code

library IEEE;



USE IEEE.STD_LOGIC_UNSIGNED.all;entity ADDER is

Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);

control,CLK,RT: in STD_LOGIC;

SUM : out STD_LOGIC_VECTOR (4 downto 0));

end ADDER;

architecture Behavioral of ADDER is

type state is (S0,S1,S2,S3);

signal PState: state;

signal Cin:STD_LOGIC_VECTOR (4 downto 0):="00000";

begin

P2: process (control,PState,CLK,RT)

begin

if RT='1' then

PState<=S0;

SUM<="00000";

elsif rising_edge(CLK) then

case PState is

when S0=> if CONTROL='0' then

PState<=S0;

SUM<="00000";

else

PState<=S1;

SUM(0)<= (A(0) xor B(0)) XOR Cin(0);

Cin(1)<= ((A(0) and B(0))or(B(0) and

Cin(0)))or(A(0) and Cin(0));

end if;

when S1=> PState<=S2;

SUM(1)<=(A(1) xor B(1)) XOR Cin(1);

Cin(2)<=((A(1) and B(1))or(B(1) and Cin(1)))or(A(1) and Cin(1));

when S2=>

PState<=S3;


Cin(3)<=((A(2) and B(2))or(B(2) and Cin(2)))or(A(2) and Cin(2));

when S3=>

PState<=S0;


SUM(4)<=((A(3) and B(3))or(B(3) and Cin(3)))or(A(3) and Cin(3));

end case;

end if;

end process P2 ;

end Behavioral;


ECED Page118

Test Bench

LIBRARY ieee;


ENTITY tb_ADDER IS

END tb_ADDER;

ARCHITECTURE behavior OF tb_ADDER IS

--Component Declaration for the Unit Under Test (UUT)

COMPONENT ADDER

PORT(

A : IN std_logic_vector(3 downto 0);

B : IN std_logic_vector(3 downto 0);

control : IN std_logic;

CLK : IN std_logic;

RT : IN std_logic;

SUM : OUT std_logic_vector(4 downto 0)

);

END COMPONENT;

--Inputs

signal A : std_logic_vector(3 downto 0) := (others => '0');

signal B : std_logic_vector(3 downto 0) := (others => '0');

signal control : std_logic := '0';



--Outputs

signal SUM : std_logic_vector(4 downto 0);



BEGIN


uut: ADDER PORT MAP (

A => A,

B => B,

control => control,

CLK => CLK,

RT => RT,

SUM => SUM

);



begin

CLK <= '0';


CLK <= '1';


end process;

-- Stimulus process


ECED Page119

stim_proc: process

begin

RT<='1','0' after 10 ns;

control <= '1' after 10 ns;

A<="0100","0101" after 400 ns,"1100" after 1200 ns;

B<="0100","0100" after 400 ns,"0010" after 1200 ns;

wait;

end process;

END;


Fig:RTL Schematic



Result:

A clock serial adder for four bits is designed and same is verified using ISim.


ECED Page120

C) A SEQUENCE DETECTOR TO DETECT THE SEQUENCE 1001.

Aim: To design a sequence detector to detect the sequence 1001.


VHDL Code

library IEEE;




entity sequencedetect is


rst : in STD_LOGIC;

sequence : in STD_LOGIC;

y : out STD_LOGIC);

end sequencedetect;

architecture Behavioral of sequencedetect is

type state_type is (s0,s1,s2,s3);

signal state:state_type:=s0;

begin

process(clk,rst,sequence)

begin

if rst='1' then

state<=s0;y<='0';


case state is

when s0=> if sequence='1' then state<=s1;y<='0';

else state<=s0;y<='0';

end if;



end if;



end if;



end if;


end case;

end if;

end process;

end Behavioral;


ECED Page121

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_sequencedetect IS

END tb_sequencedetect;

ARCHITECTURE behavior OF tb_sequencedetect IS


COMPONENT sequencedetect

PORT(

clk : IN std_logic;

rst : IN std_logic;

sequence : IN std_logic;

y : OUT std_logic

);

END COMPONENT;

--Inputs



signal sequence : std_logic := '0';

--Outputs

signal y : std_logic;



BEGIN


uut: sequencedetect PORT MAP (

clk => clk,

rst => rst,

sequence => sequence,

y => y

);



begin

clk <= '1';


clk <= '0';


end process;

-- Stimulus process

stim_proc: process

begin

rst<='1';wait for 10 ns;

rst<='0';

sequence<='1';wait for 10 ns;



ECED Page122











wait;

end process;

END;


Fig:RTL Schematic



ECED Page123



Result:

A sequence detector to detect the sequence 1001 is designed and same is verified using ISim.


ECED Page124

MODULE IX: Write a testbench for a 4x1 Multiplexer (DUT). All the input

combinations are stored in a file “input.txt”. Testbench should read the inputs from

the file and apply it to the DUT and store the result in another file named

“output.txt”. Use the relevant packages for file handling.

Aim: To write a code for reading inputs from file and and writing outputs to the file.


VHDL Code

library IEEE;


entity mux4X1 is

port (I: in std_logic_vector(3 downto 0);

S: in std_logic_vector(1 downto 0);

Y : out std_logic);

end mux4X1;

architecture Behavioral of mux4X1 is

begin

Y<= I(0) when S = "00" else

I(1) when S = "01" else



'Z';

end Behavioral;

Test Bench

LIBRARY ieee;


USE ieee.std_logic_textio.ALL;

use std.textio.all;

ENTITY tb_mux4X1 IS

END tb_mux4X1;

ARCHITECTURE behavior OF tb_mux4X1 IS


COMPONENT mux4X1

PORT(

I : IN std_logic_vector(3 downto 0);

S : IN std_logic_vector(1 downto 0);


ECED Page125

Y : OUT std_logic

);

END COMPONENT;

--Inputs

signal I : std_logic_vector(3 downto 0) := (others => '0');

signal S : std_logic_vector(1 downto 0) := (others => '0');

--Outputs

signal Y : std_logic;



file input_file : TEXT

open READ_MODE is "F:\DSD\files\input.txt";

file output_file : TEXT

open WRITE_MODE is "F:\DSD\files\output.txt";

BEGIN


uut: mux4X1 PORT MAP (

I => I,

S => S,

Y => Y

);

-- Stimulus process

file_ReadWrite: process

variable BUF_IN,BUF_OUT : line;

variable input_string : std_logic_vector(5 downto 0);

variable output_string : std_logic;

begin

while not endfile(input_file) loop

readline(input_file,BUF_IN);

assert (BUF_IN'length = 6)

report "Vector does not have valid 6 inputs in which 4 are input

data and two are selection lines"

severity ERROR;

read(BUF_IN,input_string);

I <= input_string(5 downto 2);

S <= input_string(1 downto 0);

wait for 7 ns;

write(BUF_OUT,STRING'(" Input Data-->"));

write(BUF_OUT, I);

write(BUF_OUT,STRING'(" Select lines S1S0-->"));

write(BUF_OUT, S);

write(BUF_OUT,STRING'(" Multiplexer output--->"));

output_string := Y;

write(BUF_OUT, output_string);

writeline(output_file,BUF_OUT);

end loop;

report "Reached end of the file";

wait;

end process;

END;


ECED Page126


Fig:RTL Schematic



ECED Page127


Fig:Simulation Output

Result:

A code for reading inputs from file and and writing outputs to the file is designed and same is

verified.


ECED Page128

MODULE X: Hardware Implementation (Use Spartan 3E FPGA kit and show the

result on the hardware). Design the following considering them as state machines

A) 8 bit shift register

B) Up/down decade counter

C) 8 x8 shift and add multiplier

A) 8 BIT SHIFT REGISTER.

Aim: To design a 8 bit shift register.

Software:Xilinx ISE Design Suite 13.2 with ISim (VHDL/Verilog) simulator and FPGA

SPARTAN 3E Kit

VHDL Code

library IEEE;




entity shiftreg_fsm is

port(clk_down,rst,shiftin : in std_logic;

shiftout : out std_logic);

end shiftreg_fsm;

architecture Behavioral of shiftreg_fsm is

signal temp: std_logic_vector(7 downto 0):= (others => '0');

signal count : std_logic_vector(25 downto 0) := (others => '0');


type states is (S0, S1);

signal state:states := S0;

begin

process(clk_down,rst)

begin

if(rst = '1') then

count <= (others => '0');

elsif(clk_down = '1' and clk_down'event) then

count <= count + 1;

end if;

clk<=count(25);

end process;

process(clk, shiftin,rst)

begin

if (rst = '1')then

state <= S0;

temp <= (others => '0');

elsif(clk = '1' and clk'event) then

case state is

when S0 => state <= S1;

temp <= shiftin & temp(7 downto 1);


ECED Page129

when S1 => state <= S1;

temp <= shiftin & temp(7 downto 1);


end case;

end if;

shiftout <= temp(0);

end process;

end Behavioral;

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL;

ENTITY tb_shiftreg_fsm IS

END tb_shiftreg_fsm;

ARCHITECTURE behavior OF tb_shiftreg_fsm IS


COMPONENT shiftreg_fsm

PORT(

clk_down : IN std_logic;

rst : IN std_logic;

shiftin : IN std_logic;

shiftout : OUT std_logic

);

END COMPONENT;

--Inputs

signal clk_down : std_logic := '0';


signal shiftin : std_logic := '0';

--Outputs

signal shiftout : std_logic;


constant clk_down_period : time := 10 ns;

BEGIN


uut: shiftreg_fsm PORT MAP (

clk_down => clk_down,

rst => rst,

shiftin => shiftin,

shiftout => shiftout

);



ECED Page130

clk_down_process :process

begin

clk_down <= '0';

wait for clk_down_period/2;

clk_down <= '1';

wait for clk_down_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

rst <= '1' ;

wait for clk_down_period;

rst <= '0';


shiftin <= '1';

wait for clk_down_period * 10;

rst <= '1' ;


wait;

end process;

END;

CONSTARINT FILE(.ucf)

NET "clk_down" LOC = "C9";

NET "rst" LOC = "L13";

NET "shiftin" LOC = "L14";

NET "shiftout" LOC = "F12";


Fig:RTL Schematic


ECED Page131




Result:

A shift regiater using FSM is designed and same is verified using ISim and FPGA SPARTAN

3E Kit


ECED Page132

B) DECADE UP/DOWN COUNTER.

Aim: To design decade up/down counter.


VHDL Code

library IEEE;




entity COUNTER is

Port ( A,CLK,RT : in STD_LOGIC;

Yout : out STD_LOGIC_VECTOR (3 downto 0));

end COUNTER;

architecture Behavioral of COUNTER is

signal Pstate,Nstate: STD_LOGIC_VECTOR(3 downto 0):="0000";

signal CLK_out:STD_LOGIC:='0';

begin

CLK_1: process(CLK)

variable temp: integer:=0;

begin


if temp=500000 then

temp:= 0;

CLK_out<= not CLK_out;

else

temp:=temp+1;

end if;

end if;

end process CLK_1;

STATE_1:process(CLK_out,RT)

begin

if RT='1' then

PState<="0000";

else

if (CLK_OUT='1' and CLK_OUT'event) then

Pstate<=Nstate;

else

Pstate<= Pstate;

end if;

end if;

end process STATE_1;

Yout<= Pstate;

STATE_2:process(A,Pstate)

begin

case Pstate is

when "0000" =>if A='1' then

Nstate<="0001";


ECED Page133

else

Nstate<="1001";

end if;


Nstate<="0010";

else

Nstate<="0000";

end if;


Nstate<="0011";

else

Nstate<="0001";

end if;


Nstate<="0100";

else

Nstate<="0010";

end if;


Nstate<="0101";

else

Nstate<="0011";

end if;


Nstate<="0110";

else

Nstate<="0100";

end if;


Nstate<="0111";

else

Nstate<="0101";

end if;


Nstate<="1000";

else

Nstate<="0110";

end if;


Nstate<="1001";

else

Nstate<="0111";

end if;


Nstate<="0000";

else

Nstate<="1000";

end if;

when others=>null;

end case;

end process STATE_2;

end behavioral;


ECED Page134

CONSTARINT FILE(.ucf)

NET "CLK" LOC = C9;

NET "RT" LOC = L13;

NET "A" LOC = L14;

NET "Yout[0]" LOC = D11;

NET "Yout[1]" LOC = C11;

NET "Yout[2]" LOC = F11; NET "Yout[3]" LOC = E11;

Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY tb_COUNTER IS

END tb_COUNTER;

ARCHITECTURE behavior OF tb_COUNTER IS

COMPONENT COUNTER

PORT(A : IN std_logic;

CLK : IN std_logic;

RT : IN std_logic;

Yout : OUT std_logic_vector(3 downto 0) );

END COMPONENT;

--Inputs

signal A : std_logic := '0';



--Outputs

signal Yout : std_logic_vector(3 downto 0);



BEGIN

uut: COUNTER PORT MAP

( A => A,

CLK => CLK,

RT => RT,

Yout => Yout);



begin

CLK <= '0';


CLK <= '1';


end process;

-- Stimulus process

stim_proc: process

begin


ECED Page135

RT<='1', '0' after 10 ns;

A<='1' after 10 ns,'0' after 200 ns;

wait;

end process;

END;





Result:

Decade up/down is designed and same is verified using ISim and FPGA SPARTAN 3E Kit

Date post:	19-Mar-2017
Category:	Education
Upload:	ramesh-naik-bhukya
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Digital System Design Lab Report - VHDL ECE

Education