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George Mason UniversityECE 448 – FPGA and ASIC Design with VHDL George Mason University
ECE 448
Lab 1
Developing Effective
Testbenches
2
Part 1: Introduction & General Lab Rules
Part 2: Refresher on VHDL
Part 3: Refresher on Simple Testbenches
Part 4: Introduction to Lab 1
Part 5: Hands-on Session: Isim & Templates
Agenda for today
3ECE 448 – FPGA and ASIC Design with VHDL
Part 1
Introduction & General Lab Rules
4
Lab Access Rules and Behavior Code
Please refer to
Computer Engineering Lab website
and in particular to
Access rules & behavior code
5
See the Rules posted at the Course Web Page.
Follow this link.
Tentative Grading Scheme for the Labs(the exact point amounts may still change)
Lab 1: Developing Effective Testbenches (Parts a & b) – 4 points
Lab 2: Implementing Combinational Logic in VHDL – 5 points
Lab 3: Implementing Sequential Logic in VHDL – 5 points
Lab 4: State machines – 6 points
Lab 5: VGA display – 6 points
Lab 6: DSP & FPGA Embedded Resources – 6 points
Lab 7: PicoBlaze & Serial Communication – 6 points
Lab 7a: Logic Analyzer – 2 points
Penalties and Bonus Points
Penalties:
one-week delay: 1/3 of points
i.e., you can earn max. 4 out of 6 points
No submissions or demos will be accepted more than one week
after the assignment is due!
Bonus points:
Majority of labs will have opportunities for earning
bonus points by doing additional tasks
Flexibility in the Second Part of the Semester
Lab 5: VGA display (2 weeks) – 6 points
Lab 6: DSP & FPGA Embedded Resources (2 weeks) – 6 points
Lab 7: PicoBlaze & Serial Communication (2 weeks) – 6 points
Lab 7a: Logic Analyzer (in class) – 2 points
Lab 5: VGA display (3 weeks) – 6 points
Lab 6: DSP & FPGA Embedded Resources (3 weeks) – 6 points
Lab 7a: Logic Analyzer (in class) – 2 points
Schedule A:
Schedule B:
Total: 20 points
Total: 14 points
Flexibility in the Second Part of the Semester
• Intended for students who do exceptionally well in the first part
of the semester ( ≥ 90% of points for Labs 1-4)
• An open-ended project proposed by students, the TA, or the
instructor
• Can be done individually or in groups of two students
• Schedule: Detailed Specification (1 week)
Milestone 1 (2 weeks)
Milestone 2 (2 weeks)
Final Report & Deliverable (1 week)
Schedule A+:
Total: 25 points
10ECE 448 – FPGA and ASIC Design with VHDL
Part 2
Refresher on VHDL
11ECE 448 – FPGA and ASIC Design with VHDL
Naming and Labeling (1)
• VHDL is case insensitiveExample:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent
12ECE 448 – FPGA and ASIC Design with VHDL
Naming and Labeling (2)
General rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture must be unique
13ECE 448 – FPGA and ASIC Design with VHDL
Valid or invalid?
7segment_display
A87372477424
Adder/Subtractor
/reset
And_or_gate
AND__OR__NOT
Kogge-Stone-Adder
Ripple&Carry_Adder
My adder
14ECE 448 – FPGA and ASIC Design with VHDL
Extended Identifiers
Allowed only in VHDL-93 and higher:
1. Enclosed in backslashes2. May contain spaces and consecutive underscores3. May contain punctuation and reserved characters within
a name (!, ?, ., &, +, -, etc.)4. VHDL keywords allowed5. Case sensitive
Examples: /rdy/ /My design/ /!a/ /RDY/ /my design/ /-a/
15ECE 448 – FPGA and ASIC Design with VHDL
Free Format
• VHDL is a “free format” language
No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:
if (a=b) then
orif (a=b) then
orif (a =
b) then
are all equivalent
16ECE 448 – FPGA and ASIC Design with VHDL
Readability standards & coding style
Adopt readability standards based on one of the the two main textbooks:
Chu or Brown/Vranesic
Use coding style recommended in
OpenCores Coding Guidelines
linked from the course web page
Strictly enforced by the primary instructor and the TA.
Penalty points may be enforced for not following
these recommendations!!!
17ECE 448 – FPGA and ASIC Design with VHDL
Comments
• Comments in VHDL are indicated with a “double dash”, i.e., “--”
Comment indicator can be placed anywhere in the line
Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over
a couple of linesExamples:-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFO
18ECE 448 – FPGA and ASIC Design with VHDL
Comments
• Explain Function of Module to Other Designers
• Explanatory, Not Just Restatement of Code
• Locate Close to Code Described• Put near executable code, not just in a header
19ECE 448 – FPGA and ASIC Design with VHDL
Design Entity
20ECE 448 – FPGA and ASIC Design with VHDL
Example: NAND Gate
a b z
0 0 1
0 1 1
1 0 1
1 1 0
a
bz
21ECE 448 – FPGA and ASIC Design with VHDL
Example VHDL Code• 3 sections to a piece of VHDL code• File extension for a VHDL file is .vhd• Name of the file should be the same as the entity name
(nand_gate.vhd) [OpenCores Coding Guidelines]
LIBRARY DECLARATION
ENTITY DECLARATION
ARCHITECTURE BODY
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY nand_gate ISPORT( a : IN STD_LOGIC;
b : IN STD_LOGIC; z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate ISBEGIN
z <= a NAND b;END model;
22ECE 448 – FPGA and ASIC Design with VHDL
Design Entity - most basic building block of a design.
One entity can have many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity
Design Entity
23ECE 448 – FPGA and ASIC Design with VHDL
ENTITY nand_gate ISPORT( a : IN STD_LOGIC;
b : IN STD_LOGIC; z : OUT STD_LOGIC
);END nand_gate;
Reserved words
Entity name Port names Port typeSemicolon
No Semicolon after last port
Port modes (data flow directions)
Entity Declaration
• Entity Declaration describes an interface of the component, i.e. input and output ports.
24ECE 448 – FPGA and ASIC Design with VHDL
ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type);
END entity_name;
Entity declaration – simplified syntax
25ECE 448 – FPGA and ASIC Design with VHDL
a
EntityPort signal
Driver resides
outside the entity
Port Mode IN
26ECE 448 – FPGA and ASIC Design with VHDL
Entity
Port signal
Driver resides
inside the entity
Output cannot be read within the entity
z
c <= z
c
Port Mode OUT
27ECE 448 – FPGA and ASIC Design with VHDL
Port signal
Entity
Driver resides
inside the entity
Signal x can beread inside the entity
x
c
z
z <= x
c <= x
Port Mode OUT (with extra signal)
28ECE 448 – FPGA and ASIC Design with VHDL
Signal can beread inside the entity
EntityPort signal
Driver may reside
both inside and outside
of the entity
a
Port Mode INOUT
29
Port Modes - Summary
The Port Mode of the interface describes the direction in which data travels with respect to the component
• In: Data comes into this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.
• Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.
• Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.
30ECE 448 – FPGA and ASIC Design with VHDL
Architecture (Architecture body)
• Describes an implementation of a design entity
• Architecture example:
ARCHITECTURE dataflow OF nand_gate ISBEGIN
z <= a NAND b;END dataflow;
31ECE 448 – FPGA and ASIC Design with VHDL
Architecture – simplified syntax
ARCHITECTURE architecture_name OF entity_name IS
[ declarations ]
BEGIN
code
END architecture_name;
32ECE 448 – FPGA and ASIC Design with VHDL
Entity Declaration & Architecture
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY nand_gate ISPORT( a : IN STD_LOGIC;
b : IN STD_LOGIC; z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE dataflow OF nand_gate ISBEGIN
z <= a NAND b;END dataflow;
nand_gate.vhd
33ECE 448 – FPGA and ASIC Design with VHDL
Tips & Hints
Place each entity in a different file.
The name of each file should be exactly the sameas the name of an entity it contains.
These rules are not enforced by all tools
but are worth following in order to increase
readability and portability of your designs
34ECE 448 – FPGA and ASIC Design with VHDL
Tips & Hints
Place the declaration of each port, signal, constant, and variable
in a separate line
These rules are not enforced by all tools
but are worth following in order to increase
readability and portability of your designs
35ECE 448 – FPGA and ASIC Design with VHDL
Libraries
36ECE 448 – FPGA and ASIC Design with VHDL
Library Declarations
Use all definitions from the package
std_logic_1164
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY nand_gate ISPORT( a : IN STD_LOGIC;
b : IN STD_LOGIC; z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE dataflow OF nand_gate ISBEGIN
z <= a NAND b;END dataflow;
Library declaration
37ECE 448 – FPGA and ASIC Design with VHDL
Library declarations - syntax
LIBRARY library_name;
USE library_name.package_name.package_parts;
38ECE 448 – FPGA and ASIC Design with VHDL
Fundamental parts of a library
LIBRARY
PACKAGE 1 PACKAGE 2
TYPES
CONSTANTS
FUNCTIONS
PROCEDURES
COMPONENTS
TYPES
CONSTANTS
FUNCTIONS
PROCEDURES
COMPONENTS
39ECE 448 – FPGA and ASIC Design with VHDL
Libraries
• ieee
• std
• work
Need to be explicitly
declared
Visible by default
Specifies multi-level logic system,
including STD_LOGIC, and
STD_LOGIC_VECTOR data types
Specifies pre-defined data types
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion
functions, basic text i/o functions, etc.
Holds current designs after compilation
40ECE 448 – FPGA and ASIC Design with VHDL
Modeling Wires and Buses
41ECE 448 – FPGA and ASIC Design with VHDL
Signals
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);
wire
a
bus
b
1
8
42ECE 448 – FPGA and ASIC Design with VHDL
Standard Logic Vectors
SIGNAL a: STD_LOGIC;SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0); ……….a <= ‘1’;b <= ”0000”; -- Binary base assumed by defaultc <= B”0000”; -- Binary base explicitly specifiedd <= X”AF67”; -- Hexadecimal basee <= O”723”; -- Octal base
43ECE 448 – FPGA and ASIC Design with VHDL
Merging wires and buses
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL c: STD_LOGIC;SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d <= a & b & c;
4
5
10
a
b
c
d
44ECE 448 – FPGA and ASIC Design with VHDL
Vectors and Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111”
d <= ‘0’ & ”0001111”; -- d <= ”00001111”
e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ”00001111”
45ECE 448 – FPGA and ASIC Design with VHDL
Splitting buses
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL c: STD_LOGIC;SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);b <= d(5 downto 1);c <= d(0);
4
5
10
a
b
c
d
46ECE 448 – FPGA and ASIC Design with VHDL
Part 3
Refresher on VHDL Testbenches
47ECE 448 – FPGA and ASIC Design with VHDL
Testbench Defined
• Testbench = VHDL entity that applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs.
• The results can be viewed in a waveform window or written to a file.
• Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability).
• The same Testbench can be easily adapted to test different implementations (i.e. different architectures) of the same design.
48ECE 448 – FPGA and ASIC Design with VHDL
Simple Testbench
Processes
Generating
Stimuli
Design Under Test (DUT)
Observed Outputs
49ECE 448 – FPGA and ASIC Design with VHDL
Representative
Inputs
VHDL Design
Manual Calculations
or
Reference Software
Implementation(C, Java, Matlab )
expected results
Testbench
actual results= ?
Possible sources of expected results used for comparison
50ECE 448 – FPGA and ASIC Design with VHDL
Test vectors
Set of pairs: {Input i, Expected Output i}
Input 1, Expected Output 1
Input 2, Expected Output 2
……………………………
Input N, Expected Output N
Test vectors can cover either:
- all combinations of inputs (for very simple circuits only)
- selected representative combinations of inputs
(most realistic circuits)
51ECE 448 – FPGA and ASIC Design with VHDL
Testbench
testbench
design entity
Architecture 1 Architecture 2 Architecture N. . . .
The same testbench can be used to test multiple implementations of the same circuit
(multiple architectures)
52ECE 448 – FPGA and ASIC Design with VHDL
Testbench Anatomy
ENTITY my_entity_tb IS --TB entity has no ports
END my_entity_tb;
ARCHITECTURE behavioral OF tb IS
--Local signals and constants-----------------------------------------------------BEGIN DUT:entity work.TestComp PORT MAP( -- Instantiations of DUTs ); testSequence: PROCESS -- Input stimuli END PROCESS;
END behavioral;
53ECE 448 – FPGA and ASIC Design with VHDL
Testbench for XOR3 (1)
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY xor3_tb ISEND xor3_tb;
ARCHITECTURE behavioral OF xor3_tb IS
-- Stimulus signals - signals mapped to the input and inout ports of tested entitySIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL test_result : STD_LOGIC;
54ECE 448 – FPGA and ASIC Design with VHDL
Testbench for XOR3 (2)
BEGINUUT : entity work.xor3
PORT MAP (A => test_vector(2),B => test_vector(1),C => test_vector(0),Result => test_result);
); Testing: PROCESS BEGIN test_vector <= "000";
WAIT FOR 10 ns; test_vector <= "001"; WAIT FOR 10 ns; test_vector <= "010"; WAIT FOR 10 ns;
test_vector <= "011"; WAIT FOR 10 ns; test_vector <= "100"; WAIT FOR 10 ns; test_vector <= "101"; WAIT FOR 10 ns; test_vector <= "110"; WAIT FOR 10 ns; test_vector <= "111";
WAIT FOR 10 ns; END PROCESS;END behavioral;
55ECE 448 – FPGA and ASIC Design with VHDL
VHDL Design Styles
Components andinterconnects
structural
VHDL Design Styles
dataflow
Concurrent statements
behavioral
• Testbenches
Sequential statements
56ECE 448 – FPGA and ASIC Design with VHDL
Process without Sensitivity List
and its use in Testbenches
57ECE 448 – FPGA and ASIC Design with VHDL
• A process can be given a unique name using an optional LABEL
• This is followed by the keyword PROCESS
• The keyword BEGIN is used to indicate the start of the process
• All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important.
• A process must end with the keywords END PROCESS.
Testing: PROCESS BEGIN
test_vector<=“00”;WAIT FOR 10 ns;
test_vector<=“01”;WAIT FOR 10 ns;
test_vector<=“10”;WAIT FOR 10 ns;
test_vector<=“11”;WAIT FOR 10 ns;
END PROCESS;
• A process is a sequence of instructions referred to as sequential statements.
What is a PROCESS?
The keyword PROCESS
58ECE 448 – FPGA and ASIC Design with VHDL
Execution of statements in a PROCESS
• The execution of statements continues sequentially till the last statement in the process.
• After execution of the last statement, the control is again passed to the beginning of the process.
Testing: PROCESS BEGIN
test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;
END PROCESS;O
rde
r o
f exe
cutio
n
Program control is passed to the first statement after BEGIN
59ECE 448 – FPGA and ASIC Design with VHDL
PROCESS with a WAIT Statement
• The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns.
• This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed.
• This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.
Testing: PROCESSBEGIN
test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT;
END PROCESS;
Program execution stops here
Ord
er
of e
xecu
tion
60ECE 448 – FPGA and ASIC Design with VHDL
WAIT FOR vs. WAIT
WAIT FOR: waveform will keep repeating itself forever
WAIT : waveform will keep its state after the last wait instruction.
0 1 2 3
…
0 1 2 3 …
61ECE 448 – FPGA and ASIC Design with VHDL
Specifying time in VHDL
62ECE 448 – FPGA and ASIC Design with VHDL
Time values (physical literals) - Examples
7 ns
1 min
min
10.65 us
10.65 fs
Unit of time Space
(required)
Numeric value
unit of time
most commonly
used in simulation
63ECE 448 – FPGA and ASIC Design with VHDL
Units of time
Unit Definition
Base Unit
fs femtoseconds (10-15 seconds)
Derived Units
ps picoseconds (10-12 seconds)
ns nanoseconds (10-9 seconds)
us microseconds (10-6 seconds)
ms miliseconds (10-3 seconds)
sec seconds
min minutes (60 seconds)
hr hours (3600 seconds)
64ECE 448 – FPGA and ASIC Design with VHDL
Simple Testbenches
65ECE 448 – FPGA and ASIC Design with VHDL
Generating selected values of one input
SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);
BEGIN
.......testing: PROCESS
BEGIN
test_vector <= "000";
WAIT FOR 10 ns;
test_vector <= "001";
WAIT FOR 10 ns;
test_vector <= "010";
WAIT FOR 10 ns;
test_vector <= "011";
WAIT FOR 10 ns;
test_vector <= "100";
WAIT FOR 10 ns;
END PROCESS;
........
END behavioral;
66ECE 448 – FPGA and ASIC Design with VHDL
Generating all values of one input
USE ieee.std_logic_unsigned.all;
.......
SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000";
BEGIN
.......
testing: PROCESS
BEGIN
WAIT FOR 10 ns;
test_vector <= test_vector + 1;
end process TESTING;
........
END behavioral;
67ECE 448 – FPGA and ASIC Design with VHDL
Arithmetic Operators in VHDL (1)
To use basic arithmetic operations involving std_logic_vectors you need to include thefollowing library packages:
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;orUSE ieee.std_logic_signed.all;orUSE ieee.std_logic_arith.all;
68ECE 448 – FPGA and ASIC Design with VHDL
Arithmetic Operators in VHDL (2)
You can use standard +, - operatorsto perform addition and subtraction:
signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0);
…… C <= A + B;
69ECE 448 – FPGA and ASIC Design with VHDL
Different ways of performing the same operation
signal count: std_logic_vector(7 downto 0);
You can use:
count <= count + “00000001”;
or
count <= count + 1;
or
count <= count + ‘1’;
70ECE 448 – FPGA and ASIC Design with VHDL
Different declarations for the same operator
Declarations in the package ieee.std_logic_unsigned:
function “+” ( L: std_logic_vector; R: std_logic_vector)
return std_logic_vector;
function “+” ( L: std_logic_vector; R: integer)
return std_logic_vector;
function “+” ( L: std_logic_vector; R: std_logic)
return std_logic_vector;
71ECE 448 – FPGA and ASIC Design with VHDL
Operator overloading
• Operator overloading allows different argument types for a given operation (function)
• The VHDL tools resolve which of these functions to select based on the types of the inputs
• This selection is transparent to the user as long as the function has been defined for the given argument types.
72
Library inclusion
• When dealing with unsigned arithmetic use:LIBRARY IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;
• When dealing with signed arithmetic use:LIBRARY IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_signed.all;
• When dealing with both unsigned and signed arithmetic use:LIBRARY IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
Then do all type conversions explicitly
73
std_logic_unsigned vs. std_logic_arith
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0) );
end adder;
architecture adder_arch of adder is
begin
c <= std_logic_vector(unsigned(a) + unsigned(b));
end adder_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0) );
end adder;
architecture adder_arch of adder is
begin
c <= a + b;
end adder_arch;
UNSIGNED ADDER WITH NO CARRYOUT
Tells compiler totreat std_logic_vectorlike unsigned type
74
std_logic_signed vs. std_logic_arith
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0) );
end adder;
architecture adder_arch of adder is
begin
c <= std_logic_vector(signed(a) + signed(b));
end adder_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_signed.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0) );
end adder;
architecture adder_arch of adder is
begin
c <= a + b;
end adder_arch;
SIGNED ADDER
Tells compiler totreat std_logic_vectorlike signed type
75ECE 448 – FPGA and ASIC Design with VHDL
USE ieee.std_logic_unsigned.all;
...........
SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0);BEGIN
.......double_loop: PROCESSBEGIN
test_ab <="00";test_sel <="00";for I in 0 to 3 loop for J in 0 to 3 loop
wait for 10 ns;test_ab <= test_ab + 1;
end loop; test_sel <= test_sel + 1;end loop;
END PROCESS;
........
END behavioral;
Generating all possible values of two inputs
76ECE 448 – FPGA and ASIC Design with VHDL
Generating periodical signals, such as clocks
CONSTANT clk1_period : TIME := 20 ns;
CONSTANT clk2_period : TIME := 200 ns;
SIGNAL clk1 : STD_LOGIC;
SIGNAL clk2 : STD_LOGIC := ‘0’;
BEGIN
.......
clk1_generator: PROCESS
clk1 <= ‘0’;
WAIT FOR clk1_period/2;
clk1 <= ‘1’;
WAIT FOR clk1_period/2;
END PROCESS;
clk2 <= not clk2 after clk2_period/2;
.......
END behavioral;
77ECE 448 – FPGA and ASIC Design with VHDL
Generating one-time signals, such as resets
CONSTANT reset1_width : TIME := 100 ns;
CONSTANT reset2_width : TIME := 150 ns;
SIGNAL reset1 : STD_LOGIC;
SIGNAL reset2 : STD_LOGIC := ‘1’;
BEGIN
.......
reset1_generator: PROCESS
reset1 <= ‘1’;
WAIT FOR reset1_width;
reset1 <= ‘0’;
WAIT;
END PROCESS;
reset2_generator: PROCESS
WAIT FOR reset2_width;
reset2 <= ‘0’;
WAIT;
END PROCESS;
.......
END behavioral;
78ECE 448 – FPGA and ASIC Design with VHDL
Typical error
SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL reset : STD_LOGIC;
BEGIN
.......
generator1: PROCESS
reset <= ‘1’;
WAIT FOR 100 ns
reset <= ‘0’;
test_vector <="000";
WAIT;
END PROCESS;
generator2: PROCESS
WAIT FOR 200 ns
test_vector <="001";
WAIT FOR 600 ns
test_vector <="011";
END PROCESS;
.......
END behavioral;
79
Example of Design Under Test
B
A
NEG_A
NEG_B
IN0
IN1
IN2
IN3
OUTPUT
SEL1SEL0
MUX_4_1
L0L1
NEG_Y
Y
Y1
A1
B1
MUX_0
MUX_1
MUX_2
MUX_3
0
1
0
1
0
1
80ECE 448 – FPGA and ASIC Design with VHDL
Part 4
Introduction to Lab 1:
Developing Effective Testbenches
81
Interface
ECE 448 – FPGA and ASIC Design with VHDL
82
Ports
ECE 448 – FPGA and ASIC Design with VHDL
83ECE 448 – FPGA and ASIC Design with VHDL
Part 5
Hands-on Session:
Simulation using ISim
Use of VHDL Templates