1

Digital Wave Simulation of Quasi-Static PartialElement Equivalent Circuit Method

Luigi Lombardi, Piero Belforte, Member, IEEE , Giulio Antonini, Senior Member, IEEE

Abstract—PEEC modeling is a well established technique forobtaining a circuit equivalent for an electromagnetic problem.The time domain solution of such models is usually performedusing nodal voltages and branch currents, or sometimes chargeand currents. The present paper describes a possible alternativeapproach which can be obtained expressing and solving theproblem in the waves domain. The digital wave theory is usedto find an equivalent representation of the PEEC circuit in thewave domain. Through a pertinent continuous to discrete timetransformation, the constitutive relations for partial inductances,capacitances and resistances are translated in an explicit form.The combination of such equations with Kirchhoff laws allowsto achieve a semi-explicit resolution scheme. Three differentphysical configurations are analyzed and their extracted DigitalWave PEEC models are simulated at growing sizes using thegeneral-purpose Digital Wave Simulator (DWS). The results arecompared to those obtained by using standard SPICE simulatorsin both linear and nonlinear cases. When the size of the modelis manageable by SPICE, an excellent accuracy and a speed-upfactor of up to three orders of magnitude are observed with muchlower memory requirements. PEEC model size manageable byDWS are also an order of magnitude larger than SPICE.

A comparative analysis of results including the effect ofparameters like the simulation time step choice is also presented.

Index Terms—Delay free loop (DFL), digital wave approach,digital wave simulator (DWS), free oscillations (FO), wave digitalnetwork (WDN), partial element equivalent circuit (PEEC),transient analysis.

I. INTRODUCTION

Virtual prototyping at the industrial level has become a veryeffective approach which prevents the realization of physicalprototypes, saving money and time-to-market. Engineers canquickly explore the performance of thousands of design al-ternatives without investing the time and money required tobuild physical prototypes. In the design of electronic/electricalsystems and devices, circuit simulation is nowadays consideredas a powerful environment to perform virtual prototyping,provided equivalent circuits for the systems of interest. Withthe increase of frequency, the modeling cannot neglect therole of interconnections and parasitics anymore. Physical in-terconnects therefore constitute a dominant factor affecting theoverall system performance. Hence, in order to compensatetheir effects in earlier stages of design, it is important to

Manuscript received July 23, 2016.Luigi Lombardi and Giulio Antonini are with the UAq EMC Laboratory,

Dipartimento di Ingegneria Industriale e dell’Informazione e di Economia,Universita degli Studi dell’Aquila, Via G. Gronchi 18, 67100, L’Aquila, Italy,e-mail: giulio.antonini@univaq.it.

Piero Belforte is an independent researcher at Via G. C. Cavalli 28 bis,10138 Turin, Italy, e-mail: piero.belforte@gmail.com, Research Gate account:https://www.researchgate.net/profile/Piero Belforte.

correctly characterize the interconnects and incorporate theirmodels in the same circuit environment where the design isperformed. A very popular environment for circuit simulationis represented by SPICE [1] and all the SPICE-like transientsimulators which have been developed over the years.

Interconnect modeling and parasitic extraction has beenoften performed using 3-D electromagnetic solvers which thenpose the problem of being integrated in a circuit environment.Among them, a well-known approach which naturally gener-ates accurate circuit models for 3-D electromagnetic structuresis the partial element equivalent circuit (PEEC) approach [2].The PEEC method is based on the mixed potential integralequation (MPIE) and the continuity equation. It provides acircuit interpretation of the electric field integral equation(EFIE) and continuity equation [3] in terms of partial ele-ments, namely resistances, partial inductances and coefficientsof potential. Hence, the resulting equivalent circuit can bedirectly embedded in a circuit environment allowing an easyintegration with other circuit models and the entire problembe described by means of the circuit theory and solved inboth the time and frequency domain. Time domain solutionsare especially advantageous and the unique possibility, ifthere are nonlinearities in the circuit environment. Over theyears, several improvements of the PEEC method have beenperformed allowing to handle complex problems involvingboth circuits and electromagnetic fields [2], [4]–[14]. Thedrawback of this approach is related to the extremely largesize of the PEEC circuits which results in slow time-domainsimulations.

When the propagation delay is neglected and, thus, magneticand electric field interactions are assumed to be instantaneous,the application of the PEEC method returns an equivalentRLC circuit. Enforcing Kirchoff’s laws in the time domainleads to a set of differential algebraic equations (DAEs) whichcan be solved by resorting to standard solution schemes [15]involving, e.g., backward (BD1) and forward Euler schemes,the Gear (BD2) integration method, the trapezoidal scheme[16]. Implicit methods have much better stability over theirexplicit counterparts.

In the early 1970s, Alfred Fettweis formulated the wavedigital filter (WDF) framework as a technique for designingdigital filter structures that mimic the properties of analogreference circuits, which had well-studied behavior and well-established design principles [17], [18]. The WDF conceptprovides an elegant framework for creating digital models ofanalog reference circuits (or any lumped reference system).Wave digital structures (WDS) establish models in the discretetime domain; they can be used to describe both linear and

nonlinear systems. Due to their numerical properties, WDSare well suited for hardware implementation.

Also in the early ’70s, at the CSELT Labs of Turin, the digi-tal wave approach was conveniently applied for the first time tomodel and simulate the interconnects among high-speed digitaldevices of advanced Telecom systems [19]. Fettweis conceptswere extended to distributed ideal transmission line (TL)elements while z-transform principles were utilized to developdigital wave models of active components (drivers, receivers)extracted from TDR measurements. To clearly differentiateFettweis WDF from these TL computer simulation-orienteddevelopments, the term Digital Wave (DW) was always usedinstead of Wave Digital (WD). Up to mid ’80s severalspecialized programs were developed to model and simulatelossy interconnects, crosstalks and nonlinear drivers [20], [21].Based on this experience, a general topology program, withemphasis to wideband signal integrity (SI), power integrity(PI) and electromagnetic compatibility (EMC) applications,was developed by the company HDT founded by the inventors.This simulator, called SPRINT, solved the well known DFL(Delay Free Loop) issue affecting digital wave structures,included time-variant, nonlinear elements and S-parametersbehavioral blocks described in time domain [22]. An early DWapplication to PEEC is described in [23]. The input networkdescription was a SPICE-like netlist. The latest version of thistool is DWS 8.5 [24]. A complete overview of the applicationsfields of the digital wave simulator DWS is reported in [25]along with a specific application to lossy transmission lines inthe multi-gigabit speed range.

Recently, the digital wave approach has been also appliedto the microwave filter field to model microstrip structureswith discontinuities, short-circuited and open stubs [26], [27]assuming the model of uniform transmission lines.

The aim of this paper is to present in a systematic waya digital wave formulation of quasi-static PEEC models. Apreliminary work describing the digital wave formulation ofthe PEEC method has been presented in [28] where theformulation has been shortened for lack of space. All thedetails are provided in this work along with extensive extensivetests and related numerical results. Since magnetic and electricfield couplings are described by full matrices, a critical pointis to translate them in the wave domain in an efficient way.

The paper is organized as follows. Section II briefly summa-rizes the PEEC method. The WDF framework is introduced inSection III while Section IV presents the concept of adaptors.A possible representation in the wave domain of the couplingsis presented in Section V. The solution algorithm used withinDWS is outlined in Section VI. The numerical results alongwith the comparisons between DWS and SPICE are presentedin Section VII. The conclusions are drawn in Section IX.

II. BASIC PEEC FORMULATION FOR CONDUCTIVEMATERIALS

The PEEC method is based on an integral equation for-mulation of the geometry that is interpreted in terms ofcircuit elements [2]. The main difference between PEEC andother integral equation based methods is that it provides a

circuit interpretation of the electric field integral equation interms of partial elements (e.g., partial inductances and partialcapacitances) [29]. The resulting circuit can be analyzed usingSPICE-like circuit solvers in both time and frequency domain.In the following, a short summary is presented for conductorsonly for the sake of simplicity.

The PEEC model is developed starting from the electricfield integral equations and the continuity equation. The vol-umes of the geometry under analysis is discretized usingparallelepipeds or, more in general, hexahedra, while thesurfaces are tesselated using rectangles or quadrilaterals. Theelectrical unknowns, typically current densities and chargedensity are expanded using pulse basis functions, meaningthey are assumed uniform within each elementary volumethe former, elementary surface the latter. Then, the standardGalerkin’s testing approach is used to discretize the equationsleading to topological entities like nodes and branches whichare the typical of lumped circuits and are related by a con-nectivity matrix A. Magnetic field coupling is modeled bypartial inductances Lp and electric field coupling is modeledby coefficients of potentials P. Partial resistances are alsointroduced to represent power dissipation. The definition forcoefficient of potential implies that the charges reside only onthe surface of the conductors. Short-circuit capacitances Cs

are obtained directly from the coefficients of potential P [29].The enforcement of Kirchoff Voltage and Current Laws (KVLand KCL, respectively) to the equivalent circuit leads to thefollowing sets of equations

ATφ (t) + Ri (t) + Lpd

dti(t) = −vs (t) (1a)

P−1 d

dtφ (t) + Gleφ(t)−Ai (t) = is (t) (1b)

where the relation φ (t) = Pq (t) between charge and poten-tials has been used and where Gle denotes the memory-lesslumped elements matrix. Vector vs (t) denotes the voltagesources due to incident fields [30], vector is (t) representslumped current sources.

Equations (1) represent a set of Nn + N` equations inNn + N` unknowns (Nn and N` being the number of nodesand edges, respectively, of the equivalent circuit), that can bewritten in a matrix form as follows

[R + Lp

ddt AT

−A Csddt + Gle

]·[

iφ

]=

[−vs

is

](2)

By assuming matrices P and Lp frequency independent, thesystem (2) can be re-written in time-domain as follows

Cdx(t)

dt= −Gx(t) + Bu(t) (3)

Re(s)

Im(s)

|z| = 1

Re(z)

Im(z)

Fig. 1. Spectral mapping resulting from trapezoidal rule or, equivalently, frombilinear trasform.

where

C =

[Lp 00 Cs

](4a)

G =

[R AT

−A Gle

](4b)

B =

[I 00 I

](4c)

x(t) = [i(t) φ(t)]T (4d)

u(t) =

[−vs(t)is(t)

]. (4e)

The previous equations are only slightly modified if dielectricsare included. The interested reader can refer to [12], [29], [31].

III. DIGITAL WAVE ELEMENTS AND CONNECTIONS

Digital wave circuits are the result of a conversion per-formed on an analog circuit using a particular discretizationscheme.

A. The bilinear transform

The discretization is carried out using the trapezoidal rule inthe time domain or, equivalently, the bilinear transform in thefrequency domain. Such discretization can be regarded as themapping between the continuous frequency s and the discretefrequency ψ [32]. The new discrete frequency and the analogfrequency are related by

ψ ,2

T

1− e−sT

1 + e−sT. (5)

From standard digital filtering theory e−sT = z−1 can beinterpreted as the unit delay of duration T, hence

ψ ,2

T

1− z−1

1 + z−1. (6)

If we look at the real part of ψ, we have

Re(ψ) =2

T

1− e−2Re(s)T

|1 + e−sT |2=

2

T

1− |z|2

|1 + z−1|2. (7)

Equation (7) shows that, when the real part of the analogfrequency s is positive (negative), the real part of the discretefrequency ψ is positive (negative) as well and |z| > 1(|z| < 1). Hence, as it can be seen from Fig. 1, a stable andcausal transfer function in the continuous domain will staysuch also in the discrete domain.

B. Wave variables

For a port with voltage v and a current i, incident andreflected voltage waves are defined by

a = v + iR0 (8a)b = v − iR0 (8b)

It is straightforward to extend wave digital filtering principlesto the vector case (this has been outlined by Nitsche [33] andappeared in the context of DWNs [34]). For a q-componentvector one port element voltage v = [v1, v2, · · · , vq]T , andcurrent i = [i1, i2, · · · , iq]T , it is possible to define wavevariables a and b by

a = v + iR0 (9a)b = v − iR0 (9b)

C. Digital wave elements

We will now present the digital wave equivalents of thecircuit elements mentioned in the previous Section II, namelyinductances, capacitance, resistances, current sources and volt-age sources.

Under the bilinear transform (5), or (6), the steady stateequation for an inductor becomes

v =2L

T

(1− z−1

1 + z−1

)i (10)

or, in the discrete-time domain

v (n) + v (n− 1) =2L

T(i (n)− i (n− 1)) (11)

If we apply the definition of wave variables (8), we get, in thediscrete time domain

a(n) + b(n) + a(n− 1) + b(n− 1) =

=2L

RLT(a(n)− b(n)− a(n− 1) + b(n− 1) (12)

where RL is the reference resistance for the inductance L.If we set

R0 = RL =2L

T(13)

then (12) simplifies to

b (n) = −a(n− 1) (14)

Hence, the input wave a undergo a time-step delay T and signinversion before it is output as b.

The construction of the digital wave one-ports correspond-ing to the resistor and capacitor is similar. For the capacitance,assuming

R0 = RC =T

2C(15)

It leads tob (n) = a(n− 1) (16)

assuming a reference resistance RC = T/2C and

b (n) = 0 (17)

for the resistance, assuming a reference resistance RR = R.

TABLE IDIGITAL WAVE CONSTITUTIVE RELATIONS FOR R,L,C UNDER THE

BILINEAR TRANSFORM.

Lumped element Value Port impedance Wave relation

Resistor R R b(n) = 0

Capacitor C T2C

b(n) = a(n− 1)

Inductor L 2LT

b(n) = −a(n− 1)

The digital wave constitutive relations for R,L,C under thebilinear transform are summarized in Table I.

It is worth noting that the use of an implicit integrationmethod, like the trapezoid rule, to discretize the time derivativeof the inductance and capacitance constitutive laws usuallyentails decisive numerical advantages but at the cost of thelost of the local computability, meaning that it leads to thesolution of a linear system. When the electrical quantities areexpressed by wave quantities, it leads to an explicit scheme,provided a proper choice of the reference resistance is done.

It is to be remarked that the DWF is applicable also tocircuits which do not admit an impedance or admittancerepresentation, like ideal transformers which are often usedin the design.

IV. ADAPTORS

In a circuit environment, we can connect the basic lumpedelements by means of series and parallel connections. Whenwe move to digital wave domain, the same function is per-formed by adaptors. While the mathematical description ofa connection is given by a set of equation (usually voltage-current relation for the considered elements), for the adaptorsthe description is represented by scattering parameters, whichare completely defined by the port impedances of the adaptor.

A. Series Adaptors

A

B

B

A

Fig. 2. Series connection in a circuit environment and the equivalent seriesadaptor.

It follows that a series connection will be represented in thewave domain by means of a series adaptor. Figure 2 showsthe representations of a two element series. The 3-port seriesadaptor obtained will be described by the scattering matrix

SSA =

1− γ1 −γ1 −γ1−γ2 1− γ2 −γ2−γ3 −γ3 1− γ3

(18)

where

γ1 =2 ·Rport1

Rport1 +Rport2 +Rport3

, (19a)

γ2 =2 ·Rport2

Rport1 +Rport2 +Rport3

, (19b)

γ3 =2 ·Rport3

Rport1 +Rport2 +Rport3

. (19c)

Rporti , i = 1, 2, 3 is the impedance port for the i-th port.

B. Parallel Adaptors

A

B

B

A

Fig. 3. Parallel connection in a circuit environment and the equivalent paralleladaptor.

The same applies to the parallel connection. Figure 3 showsthe case of a two elements parallel connection. The 3-portparallel adaptor obtained is described by the scattering matrix

SPA =

δ1 − 1 δ2 δ3δ1 δ2 − 1 δ3δ1 δ2 δ3 − 1

(20)

where

δ1 =2 ·Gport1

Gport1 +Gport2 +Gport3

, (21a)

δ2 =2 ·Gport2

Gport1 +Gport2 +Gport3

, (21b)

δ3 =2 ·Gport3

Gport1 +Gport2 +Gport3

. (21c)

Gporti , i = 1, 2, 3 is the admittance port for the i-th port.

C. Reflection-Free PortIf we better analyze the scattering matrix for both series and

parallel adaptors, we easily realize that, with a proper choiceof the n-th impedance, we can stamp out the reflection on thesame port. As a consequence, we can obtain that the reflectedwave at the n-th port does not depend instantaneously on theincident wave at that port (snn = 0) . For example if weconsider the case of a 3-port series adaptor we will have:

SSA =

1− γ1 −γ1 −γ1γ1 − 1 γ1 γ1 − 1−1 −1 0

(22)

if we choose the reference port 3 impedance such that

Rport3 = Rport1 +Rport2 . (23)

Similarly for a 3-port parallel adaptor,

SPA =

δ1 − 1 1− δ1 1δ1 −δ1 1δ1 1− δ1 0

(24)

if we choose the reference port 3 admittance such that

Gport3 = Gport1 +Gport2 . (25)

It can be noticed that the impedances of the Reflection FreePort (RFP) is exactly the equivalent impedances seen from theA and B terminals if we consider the hybrid representationin Fig. 4, or the circuit representation in Figs. 2 and 3.The enforcement of the RFP criterion allows to decouple thecomputation between the waves propagating from the leavesto the root and the ones propagating in the inverse direction inthe chain of adaptors. This could lead to an explicit scheme,as we will see in the first example of the section VI, or to asemi-explicit scheme as we will see in the second example ofthe section VI. It must be noticed that the effectiveness of thisapproach depends on the way the elements are connected toeach other, more the network graph has triconnected elementsmore the solution becomes implicit because of the presenceof Delay Free Loop (DFL) needed to represent complexinstantaneous connections.

B

A

B

A

Fig. 4. Hybrid representation for series and parallel adaptors.

V. COUPLING REPRESENTATION

In this section we will see some possible way for managingthe coupling as DWS does in order to obtain a performanceimprovement.

A. The ”Marx” Π Model

k

L1 L2

D

C

A

B

L11

L12

L22

D

C

A

B

Fig. 5. Coupled inductors and their ”Marx” Π representation.

As seen in the previous section, in the conversion processfrom analog to digital network, a one-by-one replacementcan be performed for resistors, capacitors and inductors.Unfortunately, we can not do the same for inductive couplingcoefficients, hence we need to find some kind of equivalentrepresentation admitting a simple substitution in the digitalnetwork. We can represent the inductive behavior using theMarx, or Π, equivalent for the inductive couplings as shown inFig. 5 [24], in this way we replace the coupling coefficients inthe models with inductors. Hence, starting from inductors and

coupling factors we can compute a pure inductive equivalentrepresentation which admits an immediate representation inthe digital wave domain. For the case shown in Fig. 5, if wename the two inductors L1 and L2 and M = k

√L1L2, we

can compute the value of the Π equivalent by

L11 =L1L2 −M2

L2 −M(26)

L22 =L1L2 −M2

L1 −M(27)

L12 =L1L2 −M2

M(28)

In case of three or more coupled inductors, this represen-tation requires the inversion of the partial inductance matrix.The partial inductance matrix Lp may easily become quitelarge for PEEC models with a number of branches exceedinghundred thousands. Anyway, several techniques are availableto accelerate the inversion (e.g., see [35]).

N1

T-1

AS12

T-1

N2

T-1

A B C D

Fig. 6. Stub model for circuit in Fig. 5.

B. Link Model for Inductors

N1

T-1

A B C D

N2

T-1

T

T

Fig. 7. Link model for circuit in Fig. 5.

Once the Π model for coupled inductors is computed,we can quite easily obtain two possible equivalent networksbased on the ”stub” and ”link” models of inductors, shownin Fig. 6 and Fig. 7, respectively. The most accurate oneis the ”stub” representation [36], in which (see Fig. 6) wereplace the inductance by means of a stub having characteristicimpedance:

ZC =2 · L

TSTEP. (29)

Unfortunately, the resulting equivalent digital network leadsto a more implicit scheme, because we need to preserve theseries adaptors between the two parallel adaptors. In order toimprove the computation performances we can use the ”link”

model (see Fig. 7) for the mutual inductances that makesthe computation explicit within each inductive branch of thePEEC model and, at the same time, retains the stub modelfor the self-inductances. The link model of inductor is therepresentation of an inductor by means of a transmission line[24], [36], [37] having characteristic impedance:

ZC =L

TSTEP. (30)

It can be proved that the error, assuming the same time step, isfour times larger than the one obtained from the stub model.Due to the relation between errors [36] and time step, both linkand stub models are characterized by the same error simplyusing a time step for the link model equal to half the timestep for the stub model. Moreover, since the error can beregarded as a shunted capacitor, for both representation, theglobal model is still passive.

C. Electric Coupling

In the PEEC context, the electric field coupling can berepresented by either coefficients of potential or capacitors.Thus it is possible to represent the electric coupling in thedigital wave domain exploiting the capacitors representation.

VI. SIMPLE EXAMPLES AND DISCUSSION

In this section two simple examples are presented in orderto give more insight on DWS operation and some observationsare given to better explain the features of the proposedapproach.

A. RLC Series Circuit

e

R1 L3

R5C2 C4

Fig. 8. Simple RLC circuit.

The first example is the RLC circuit shown in Fig. 8. Usingthe transformations described in the previous sections and theequivalent wave representation for the real voltage source, itis easy to obtain the equivalent DWN, Fig. 9,including thescattering parameters for each adaptor. At this stage we canstart the computation going back and forth from the borders tothe middle of the circuit and viceversa. In this way we define

N1 SA1 N2

e

Ts Ts−1 Ts

0

Fig. 9. Equivalent wave digital network for the circuit in Fig. 8.

a)SA1

N1 N2

b)

ROOT

SARLi

SANLi

SACi

Fig. 10. Solution tree for the wave digital network in Fig.9 (a) and Fig. 12(b) .

R1 L1

R2 L2

RloadRS

C′1

C′4

∑αj4v(C

′j)

∑αj3v(C

′j)

C′3

C′2

∑αj2v(C

′j)

∑αj1v(C

′j)

IS

1 2

34

Fig. 11. Analog two cell PEEC.

the solution tree in Fig. 10. For this circuit the solution schemeis fully explicit and thanks to the computational schedulingadopted within DWS we have a very fast solving algorithm.If the circuit becomes larger the solution tree becomes deeperand/or wider and the scheme stays explicit, as long as we donot have free delay loop in the wave digital network [38].

B. PEEC 2 cell

The second example consists of a simple PEEC model thatallows us to take all the significant elements into accountthat are also found in larger problems. For the sake ofexplanation, we will use the representation in Fig. 11 and wewill use delayed controlled sources for the VCVS. Every otherrepresentation is fine as well although the WDN may resultto be different and even more complex. For the consideredrepresentation, the equivalent digital network is described inFig. 12. As in the previous example we can solve the networkfrom the border to the middle but at a certain stage weencounter the delay free loop in Fig. 13, hence we need tosolve it implicitly. The exposed procedure define the solutiontree in Fig. 10 (b) where ROOT is the DFL that is to besolved in some way. A possible approach for the solution of thesolution of the ”root” is given by the definition of an equivalentcircuit composed by resistors and controlled sources. Thedefinition of such network is completely specular respect to thecomputation of the equivalent digital network determination.

SAS

iS · RS

SAL

0

N4

SAc4

T

∑αj4v(C

′j)

SA2

0

SARL2

N3

SAc3

T

∑αj3v(C

′j)

NL2

-1

T

-1

TNL1

SARL1

T T

N2

SAc2

T

∑αj2v(C

′j)

SA1

0

N1

SAc1

T

∑αj1v(C

′j)

Fig. 12. Equivalent digital network for the 2 cell PEEC.

SAS

iS · RS

SAL

0

N4 SA2 N3

N2SA1N1

Fig. 13. ”Root” of the equivalent digital network for the 2 cell PEEC.

+

−iSRS

RS

R2

1GL2

+−

aL2

RL

R1

1GL1

+ −

aL1

+

−aN1

RN1

+

−aN4

RN4

+

−aN3

RN3

+

−aN2

RN2

Fig. 14. Circuital representation for the root problem.

In the case of this example the circuit representation of the”root” is shown in Fig. 14 and can be solved by nodal analysis.

VII. NUMERICAL RESULTS

The proposed digital wave formulation has been experi-mented using the tool DWS [24] while the traditional NodalAnalysis has been performed using both Ngspice [39] andPspice [40]. Ngspice has been used to compare the simulationtimes and RAM size requirements in a free oscillations config-uration. Pspice has been used to compare the numerical resultsin specific termination conditions specified in the examples.

The digital wave simulator DWS is completely circuit-oriented and, thus, can be considered as an alternative tostandard SPICE-like solvers. All the simulations have beenperformed on an Intel Quad-Core i7-2630QM 2.00 GHz CPUmachine.

Three different physical structures have been chosen tocompare DWS to SPICE results. The effect of growing sizeof the PEEC model is evaluated using different pitches ofspatial discretization. The PEEC model has been generatedby using an in-house tool, then a SPICE-like netlist has beensynthesized and analyzed using both Ngspice [39] and Pspice[40]. The same RLC and coupled inductor PEEC netlist can besimulated by all the tools simply modifying the .TRAN controlstatement according to DWS and SPICE syntax respectively.The tests have been carried out using a stimulus and termina-tion configuration suitable to pinpoint results differences witha bandwidth resolution much higher than the bandwidth of thePEEC model itself. An ideal fast ramp voltage (10 ps total risetime) source is connected to the input port while the outputport(s) are left open. This configuration is able to generatefree oscillations of the circuit under test. Observing the outputwaveforms for a suitable number of free oscillations it is easyto point out issues like late-time numerical instabilities, delaydifferences and spurious losses due to the simulation methodused.

Using DWS, the most important control parameter is thesimulation time step (TSTEP). This choice directly conditions

the parameters of the generated DWN, the integration error andthe equivalent bandwidth of the simulation. Using the defaultsemi-explicit method for PEEC couplings, the TSTEP valueis also directly related to the stability of the simulated model.Typically picosecond or sub-picosecond TSTEP values arerequired with a 10 ps input stimulus to get good stability forthe chosen test circuits. SPICE typically works at variable timestep and in order to get results with an accuracy/ bandwidthcomparable to DWS the maximum allowed value of time step(TMAX) was chosen as main control parameter, leaving theother options to their default value.

A. Interconnect

In the first example, a five conductor interconnect is con-sidered. The length, width and thickness of the conductorsare 5 cm, l50 µm and 100 µm, respectively. The edge-to-edge spacing is l50 µm. The geometry of the interconnect isshown in Fig. 15. In the first test, the first two conductors areterminated on 1 pΩ resistance and driven by a voltage stepwith 10 ps rise-time. All the other ports are left open. Figure16 shows the output port voltage on the two driven conductors.Figures 17-18 shows the input and output port voltages on thelast two open-ended conductors.

0

0.02

x [m]

0.040

0

×10-3

y [m]

1

0.5

×10-4

z [

m]

0.0611.5

2

Fig. 15. Five conductor interconnect.

In the second test, the first port is driven by a fast voltageramp (10 ps rise time and 1 V of amplitude) while all the otherports are left open. The comparative performances of Ngspiceand DWS solvers are reported in Table II.

B. Power divider

In the second example, a three-port microstrip power-dividercircuit has been modeled. The structure is shown in Fig. 19(P1, P2 and P3 denote the ports). The dimensions of the circuitare [20, 20, 0.5] mm in the [x, y, z] directions and the width ofthe microstrips is set as 0.8 mm. Furthermore the dimensionslX1, lY 1, and lY 3 are 9, 7.2 and 7.2 mm, respectively. Therelative dielectric constant is εr = 2.2. In the first test, port 1is excited by a 2 V finite ramp with a rise-time 10 ps. All the

0 0.2 0.4 0.6 0.8 1

Time [s] 10-8

-0.5

0

0.5

1

1.5

2

2.5

V2 [

V]

Pspice

DWS

Fig. 16. Interconnect port 2 voltage.

0 0.2 0.4 0.6 0.8 1

Time [s] 10-8

-0.14

-0.12

-0.1

-0.08

-0.06

-0.04

-0.02

0

V5 [

V]

Pspice

DWS

Fig. 17. Interconnect port 5 voltage.

0 0.2 0.4 0.6 0.8 1

Time [s] 10-8

-0.2

-0.15

-0.1

-0.05

0

0.05

V6 [

V]

Pspice

DWS

Fig. 18. Interconnect port 6 voltage.

ports are terminated on 50 Ω resistances. In the second test,the first port is driven by a fast voltage ramp (10 ps rise timeand 1 V of amplitude) while all the other ports are left open.

TABLE IIPERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE 5 CONDUCTOR MTL CASE.

Netlist lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice [s] DWS [s] Speed-up11k 180 100 10 10 1096 1.6 68511k 180 100 10 0.1 4200 65 64.630k 300 160 10 10 5400 6.8 794.130k 300 160 10 0.1 11700 468 25114k 620 300 0.5 0.5 NA 708 NA114k 620 300 0.5 0.1 NA 3111 NA

wP1

P3P2

lX,1

lY,1 lY,3

lY

lX

Fig. 19. The three-port microstrip power-divider circuit.

0 1 2 3 4 5

Time [s] 10-9

0

0.2

0.4

0.6

0.8

1

1.2

V1 [

V]

Pspice

DWS

Fig. 20. Power divider port 1 voltage.

0 1 2 3 4 5

Time [s] 10-9

-0.2

0

0.2

0.4

0.6

0.8

V2 [

V]

Pspice

DWS

Fig. 21. Power divider port 2 voltage.

0 1 2 3 4 5

Time [s] 10-9

-0.2

0

0.2

0.4

0.6

0.8

1

V3 [

V]

Pspice

DWS

Fig. 22. Power divider port 3 voltage.

The comparative performances of Ngspice and DWS solversare reported in Table III.

C. Coplanar striplines

In the third example, two coplanar striplines are embeddedin a dielectric, as shown in Fig. 23 and backed by two metallicplanes. The conductivity of striplines and planes is σ = 5.7 ·107 S/m. The relative permittivity of the dielectric is εr = 4.The blue lines represent the ports. Following are the geometricparameters shown in Fig. 23 : `1 = 40 mm, `2 = 14 mm, s1 =5 mm, s2 = 2 mm, wc = 1 mm, vs = 10 mm, hd = 20.95mm and tc = 50 µm. A voltage ramp of amplitude 2 V isapplied to port 1. Port 1 has a 50 Ω resistance while port 2 isleft open. The transient voltages are observed at ports 1 and2. In the second test, the first port is driven by a fast voltageramp (10 ps rise time and 1 V of amplitude) while all the otherports are left open. The comparative performances of Ngspiceand DWS solvers are reported in Table IV. Then, in a thirdtest, the coplanar striplines have been terminated on a diode(CJO=1 pF, Tt=100 ps) with in parallel a 100 fF capacitor.The input port of the striplines is driven by a voltage rampwith 10 ps rise time and 0.5 V amplitude. Figure 26 presentsthe voltage across the diode as evaluated by the digital wavesimulator (DWS) and Ngpice. The performances are reportedin Table V.

TABLE IIIPERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE POWER DIVIDER CASE.

Netlist lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice DWS [s] Speed-up35k 436 86 0.5 0.5 480 min 55 523100k 720 149 0.5 0.5 67 h 360 670100k 720 149 0.5 0.2 NA 660 NA200k 1008 212 0.2 0.2 NA 1260 NA

TABLE IVPERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE COPLANAR STRIPLINE CASE

(*ESTIMATED SIMULATION TIME WITH TMAX = 1 ps).

Netlist Lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice DWS [s] Speed-up18k 300 72 0.2 0.2 5760 50 11518k 300 72 0.2 0.1 NA 88 NA18k 700 144 0.2 0.2 34h * 574 21396k 700 144 0.2 0.1 34h * 1050 116255k 1150 264 0.05 0.05 NA 5800 NA

TABLE VPERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS FOR THE COPLANAR STRIPLINE CASE TERMINATED ON A DIODE

(*ESTIMATED SIMULATION TIME WITH TMAX = 0.2 ps).

Netlist Lines Edges Nodes DWS MAX TSTEP [ps] DWS TSTEP [ps] Ngspice DWS [s] Speed-up18k 300 72 0.2 0.2 366 min 41 54996k 700 144 0.2 0.2 253 h* 574 1500225k 1150 264 0.05 0.05 NA 5800 NA494k 1500 288 0.2 0.2 NA 6450 NA

`2

`1

hd

tc

tc

s1vs

vs

tc

wc s2 wc

vs

vs

tc

s1

1

2

Fig. 23. Structure of the coplanar striplines circuit.

0 0.2 0.4 0.6 0.8 1

Time [s] ×10-8

0

0.5

1

1.5

2

2.5

V1 [

V]

Pspice

DWS

Fig. 24. Coplanar striplines port 1 voltage.

0 0.2 0.4 0.6 0.8 1

Time [s] ×10-8

-0.5

0

0.5

1

1.5

2

2.5

3

V2 [

V]

Pspice

DWS

Fig. 25. Coplanar striplines port 2 voltage.

VIII. ANALYSIS OF RESULTS

A. DWS simulations

It has been observed from the tests that the default DWSmodel of magnetic couplings leads to a semi-explicit wavemodel that imposes some constraints of the maximum allowedsimulation time step (MAX TSTEP). To insure late-timestability of the simulation a sufficiently small TSTEP hasto be chosen. The value of the maximum allowed tstep hasbeen determined experimentally and depends on the specificmodel and on the size of the circuit. Larger circuit size usuallyrequires smaller time steps. The multiconductor transmissionline of Fig. 15 allows a time step up to 10 ps for thesmaller model sizes (11K and 30K netlist lines), while 500

0 0.2 0.4 0.6 0.8 1

Time [s] ×10-8

-0.2

0

0.2

0.4

0.6

0.8V

olta

ge

[V

]

DWS

Ngpice

Fig. 26. Voltage across the diode (example of coplanar striplines).

fs is required for the 114K netlist lines model. The three-port splitter of Fig. 19 and the coplanar stripline of Fig. 23show MAX TSTEP values ranging from 500 fs down to 50 fsdepending of the netlist size. The calculation speed is linearlydependent on time step while the bandwidth resolution isinversely proportional. Using sub-picosecond time steps thesimulation bandwidth exceeds the requirement imposed by the10 ps transition time of the stimulus and by the extractedPEEC model itself. RAM size requirements are not dependenton time step and depends only on circuit size. 22.5 MB arerequired for a 18K lines coplanar stripline model, while 263MB are required to run the largest models (400K lines). Therequired RAM is constant during the simulation run. Theanalysis of free oscillations has also pointed out that no energylosses are due to the simulator even for relatively long times(tens of nanoseconds). This lossless behavior is expected dueto the use of wave models equivalent to the trapezoidal ruleof integration for capacitors and inductors and for the linktransmission line model of the magnetic coupling.

B. SPICE simulations

Three SPICE versions has been used during the tests:Ngspice, Pspice and Ltspice. While Ngspice and Pspice givepractically the same results, LTspice is affected by a strongdamping of high-frequency components if default settingsof inductor parameters are used. To avoid this effect, theadditional default resistances must be set to zero [41]. Ngspiceand Pspice simulation time is strongly affected by circuit sizeand this dependence is not linear, so that PEEC models withsize in the order of tens of thousands netlist lines are verydifficult to be managed because of prohibitive run times (hoursto tens of hours). RAM requirement grows during run time andis in the order of 462 MB for a 18K lines model (Coplanarline with diode clamp).

C. DWS vs SPICE

The comparison of DWS and SPICE (Ngspice, Pspice,LTspice) simulations shows a very good matching between

numerical results even in the wideband configuration used forthe tests. A slight phase shift of persistent free oscillationscan be observed especially after a consistent number ofoscillations. This phase shift grows linearly with time andis due to the one-step delay of the link model of magneticcoupling used in DWS. For this reason it is more significantwhen using larger time steps. In practical configurations whereresistive sources and loads are used, this effect is negligible.

The most evident difference is on the speed-up achievedby DWS with respect to SPICE. The observed speed-up isranging from 65X for the simplest MTL model to 1500X(extrapolated) for the medium size Coplanar stripline witha nonlinear termination. The speedup is 4 times larger fora nonlinear situation with respect the linear one. DWS canmanage PEEC models up to a 500K lines netlist complexitywith a simulation time in the order of a couple of hours whileSPICE is practically limited to about 20K lines. With largersize circuits DWS is affected by a significant amount of timespent for building up the DWN from the netlist. In the case ofCoplanar line largest model, this setup time is about the 60%of the total elapsed time.

Despite its speed, DWS also requires a smaller amountof RAM with respect to SPICE. A typical 20X RAM sizereduction has been observed in the tests. A main reason of theslow simulation speed of SPICE is the variable simulationtime step. This requires a matrix inversion at each stepin a situation where the matrix is dense. The situation isexacerbated when the circuit is nonlinear, because at each stepa number of Newton-Raphson iterations is required. In DWSthese iterations are confined only to the nonlinear elements orare not required in case of piecewise linear elements [24], sothat the time required for a non linear circuit can be aboutthe same of the linear situation. The same applies for time-variant terminations [42]. Several additional technical reportsregarding DWS-PEEC trials are reported in [43].

IX. CONCLUSIONS

In this paper a Digital Wave formulation of quasi-staticPEEC method (PEEC-DWS) has been presented. This for-mulation is used within the general purpose simulator DWS.Despite DWS has been conceived mainly to deal with prop-agation and delay effects typical of wideband SI, PI andEMC problems, it has been demonstrated that it can be alsoconveniently utilized for highly interconnected RLC lumpedelectrical networks typical of PEEC models. Using a Marxequivalent of coupled inductors, DWS builds up a semi-explicit wave domain equivalent of the PEEC model startingfrom its Spice-like netlist. Stable simulations of the PEECmodel connected to a linear, time-variant or even nonlinearnetwork, can be achieved if a sufficiently small simulationtime step is used. Comparative tests with Ngspice or Pspicesimulations, carried out using very fast ramp stimulus andopen terminations, have shown an excellent agreement witha speed-up factor of up to 3 orders of magnitude and a muchlower requirement of memory. The larger the PEEC model,the larger is the achievable speed-up and the speed gain ishigher in nonlinear situations. While SPICE is practically

limited to deal with PEEC models showing a netlist sizein the order of ten thousand lines, DWS can be used tosimulate models up to 50-100 times this size. Being theDWN used by DWS essentially composed by unit-delay TLand adaptors (series and parallel) no additional loss is addedwithin the wave model. This lossless behavior can be easilyverified by observing the free oscillations generated by thetest configurations: they are persistent if the no resistive part isincluded within the PEEC model. Another major advantage ofusing the PEEC-DWS modeling is the ability to mix traditionalPEEC models with lossless/lossy distributed-parameters TLMor behavioral time models that are very fast and accurate.A further step toward higher performance can be achievedusing alternative modeling techniques of basic elements likecapacitors and inductors in order to get stable responses evenusing larger time-steps. Another interesting development is theutilization of different alternatives by modeling the couplingsby means of delayed controlled sources well supported byDWS and/or including behavioral frequency dependent losseswithin the PEEC-DWS cells.

These alternative solutions will be the object of futureresearch work.

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Luigi Lombardi was born in Larino (CB), Italy.He received the Laurea degree (cum laude) in elec-tronic engineering in 2015 University of L’Aquila,L’Aquila, Italy, where he is currently working towardthe Ph.D. degree.

Piero Belforte Born in Turin in 1947, he re-ceived his Laurea degree in Electronics Engineeringsumma cum laude in 1970 from the Politecnico ofTurin. From 1970 to 2000 he worked in CSELT,the Research Center of Telecom Italia as Head ofSwitching Techniques Department and then as Headof Hardware Qualification Department. In 1975 hestarted the development of several generations ofhigh-speed modeling and simulation tools using in-novative DSP algorithms for fast computer simula-tion of high-speed electronic systems. In 1988 he

founded and directed the company HDT (High Design Technology) for thedevelopment of state-of.-the art CAE tools for SI/PI/EMC prediction basedon digital wave simulation. From 2001 to present he continues his researchactivity as Independent Researcher He is author of several publications andinternational patents in the field of digital electronics with reference todigital switching systems and techniques for telecom networks, high-speedelectronics, signal and power integrity, circuital modeling and simulation,electromagnetic compatibility and test equipment for high performance digitalsystems

Giulio Antonini (M94 - SM05) received the Laureadegree (cum laude) in electrical engineering fromUniversity of L’Aquila, L’Aquila, Italy, in 1994and the Ph.D. degree in electrical engineering fromUniversity of Rome “La Sapienza” in 1998. Since1998, he has been with the UAq EMC Laboratory,University of L’Aquila, where he is currently aProfessor. His scientific interests are in the field ofcomputational electromagnetics.