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Partial Element Equivalent Circuit (PEEC) E8-202 Class 12 Dipanjan Gope
Partial Element Equivalent Circuit (PEEC)
E8-202 Class 12
Dipanjan Gope
2
Grading Scheme
Time Frame Assignment Grading
Sep 6 HW 1 15
Sep 24 HW2
Oct 8 HW 3
Oct 11 Midterm 1 15
Nov 5 HW 4 5
Nov 20 Midterm 2 15
Dec 5 Final Exam 30
Dec 10 Final Project 20
3
• 2D vs 2.5D vs. 3D Formulations
• Electrostatic Formulation: Capacitance matrix extraction
• Magnetostatic Formulation: Inductance matrix extraction
• Electric Field Integral Equation (EFIE): S-parameter extraction
• Partial Element Equivalent Circuit (PEEC) Method
• Magnetic Field Integral Equation (MFIE) and Combined Field Integral Equation (CFIE)
• PMCHWT Formulation: Dielectric modeling
• Parallelization techniques
Module 2: Method of Moments
4
• A. E. Ruehli, “Equivalent circuit models for three-dimensional multiconductor systems” IEEE Trans. Microwave Theory and Techniques, vol. MTT22 (3), pp. 216-221, March 1974.
References
5
What does PEEC do?
Lumped Circuit Elements e.g. R; L; C; V; I
Distributed Circuit Elements e.g. Transmission Line
~r dt t
KVL; KCL Maxwell’s Equations
Elem
en
ts
Def
init
ion
Eq
uat
ion
s So
luti
on
SPICE Port Model + SPICE PEEC
r dt t
6
SPICE Review
• Sparse Tableau Analysis (STA) - IBM ASTAP simulator
• Modified Nodal Analysis (MNA) - SPICE simulators
7
Stamps Revisited
Resistor
Current Source
Voltage Source
Some excerpts from UW class notes by Prof. Richard Shi and Guoyong Shi
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Stamps Revisited
Capacitor
N+
N-
N+ N- RHS
N+ C/h -C/h (C/h)V(t-h)
N- -C/h C/h -(C/h)V(t-h)
Inductor
N+
N-
N+ N- I-branch RHS
N+ 1
N- -1
Branch 1 -1 -L/h -(L/h)I(t-h)
9
Stamps Revisited
VCVS
CCCS
Some excerpts from UW class notes by Prof. Richard Shi and Guoyong Shi
N+ N- NC+ NC- ik
N+ 1
N- -1
NC+
NC-
ij 1 -1 E -E
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' '
' ' ' '( )( , ) ( , ) ( ) ( , ) ( )i
v v
J rE r j G r r J r dv G r r q r dv
j
Circuit Model Element Identification
• KVL: Voltage = R I + sLp I + Q/sC
• RHS Term 1: Resistance
• RHS Term 2: Partial Inductance
• RHS Term 3: Coefficients of Partial Potential
PEEC: Equation
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Basis Function
Current
Charge
12
Partial vs Loop Inductance
Loop Partial
122211 2LLLL
13
Vc2
CCVS
Vc1
Unit Cell
' '
' ' ' '( )( , ) ( , ) ( ) ( , ) ( )i
v v
J rE r j G r r J r dv G r r q r dv
j
dldarfa
dvrfa
a lv
)(1
)(1
Testing Function
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Vc2 CCVS
Vc1
Resistance Term
dldaJ
adv
J
aa lv
11
dldaa
I
adv
J
aa lv
11
a
lIdv
J
av
1
15
Vc2 CCVS
Vc1
Inductance Term
v va a
dvdvGaa
jGJdvdvja
'1
'1
''
'
v v
vvp dvdvGaa
L '1
''
'
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Vc2 CCVS
Vc1
Capacitor Terms
2121111 QpQp
211
1211
11
1Q
p
pQ
p
dt
dQ
p
p
dt
dQ
dt
d
p
2
11
1211
11
1
211
121
1
11
1cc i
p
pi
dt
d
p
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Ge
om
etry
C
on
du
cto
r
4km
k m k m
k mp k m
k m k ma a l l
dl dlL da da
a a r r
+ - + -
R1 N1 N2 1.202mOhms
L1 N2 N3 5.887nH
C1 N1 0 1.702pF
K12 L1 L2 1.282nH 0.054ns
F12 N4 0 V1 0.124 0.032ns
PEEC Stick Example
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Vc2 CCVS
Vc1
Basic Dielectric Modeling
Vc2 CCVS
Vc1
vv
i dvrqrrGj
dvrJrrGjj
JrE ')'()',(')'()',(
)1(),(
'0
l
AC 0)1(
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Integral Equation Solution to Maxwell’s Equations
Special Meshing for PEEC Cells
Transformation to PEEC Circuit Elements
SPICE Circuit Elements Other SPICE Type Models
SPICE Like Circuit Description
MNA Delay Diff. Eq. (DDE) Circuit Solver
Voltages, Currents, Electric and Magnetic Fields
PEEC Flow
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• Orthogonal, No-retardation
• …
• Orthogonal, with-retardation
• …
• Orthogonal, with-dielectric and retardation
• Non-orthogonal, with dielectric, retardation
• ….
PEEC History
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Volumetric formulation ideal for on-chip cases
• No thickness discretization necessary
DC to daylight solution
• Charge and current decoupled at DC
“Stamps” provide interface between techniques Multi-purpose solver (.tran / .ac / .cap / .ind)
PEEC: Advantages
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Dense Matrix: Expensive LU (Gaussian Elimination)
• Can we use EM properties to expedite solution? Volume formulation unsuitable for “thick” structures
• Can we get similar stamps for surface-based/hybrid form?
PEEC: Drawbacks
Addressed in later research
