Discrete Gate SizingCENG 5270 – Tutorial 9WILLIAM CHOW

Discrete Gate Sizing Given design D that contains:

◦ Set of standard cells C◦ Set of pins P on these cells◦ Set of Nets N

DN1

N2

N3

N4 N5

N6

N7

N8

PI

PO

C1 C2 C3

C4 C5

Sc1

Power = 2uW

Power = 4uW

Power = 8uW

Discrete Gate Sizing For each standard cell , contains:

◦ Set of cell types Sc

For each of cell type , ◦ Power(s) denotes the leakage power of cell type s

DN1

N2

N3

N4 N5

N6

N7

N8

PI

PO

C1 C2 C3

C4 C5

Sc1

Power = 2uW

Power = 4uW

Power = 8uW

Discrete Gate Sizing For each pin ,

◦ Slack(p) denotes timing slack at pin p

DN1

N2

N3

N4 N5

N6

N7

N8

PI

PO

C1 C2 C3

C4 C5

Sc1

Power = 2uW

Power = 4uW

Power = 8uW

Slack Signal at primary input (PI) must arrive primary output (PO) within target delay

Slack = actual arrival time (AAT) – required arrival time (RAT)

10

89

9

4

9

6

0

0

10

8

28

23

37

29

19

10

89

9

4

9

6

-7

-5

3

3

21

24

30

30

12

Actual arrival time

Required arrival time

Slack

10

89

9

4

9

6

0

0

10

8

28

23

37

29

19

10

89

9

4

9

6

-7

-5

3

3

21

24

30

30

12

Actual arrival time

Required arrival time

10

89

9

4

9

6

-7

-5

-7

-5

-7

+1

-7

+1

-7

Slack

Total Negative Slack (TNS) denote the absolute value of the total negative slack of all PO

TNS = 7

Delay Tables (DT)Slew Tables (ST)

◦ Cell delays and slews are defined using delay tables and slew tables.◦ The timing arcs are defined from input pins of the cell to the output pin

(rising and falling).◦ Timing arc delay = DT[in_slew, out_load]◦ Timing arc slew = ST[in_slew, out_load]

out_load=50fF

in_slew=80ps

0 20 40 80 160

10 12.5 15.7 18.9 22.0 25.2

20 24.1 30.5 36.7 41.5 50.0

40 30.8 52.4 70.1 82.3 98.2

60 44.7 63.0 99.7 101.5 123.4

80 89.5 91.5 110.5 168.8 210.7

0 20 40 80 160

10 12.5 15.7 18.9 22.0 25.2

20 24.1 30.5 36.7 41.5 50.0

40 30.8 52.4 70.1 82.3 98.2

60 44.7 63.0 99.7 101.5 123.4

80 89.5 91.5 110.5 168.8 210.7

0 20 40 80 160

10 12.5 15.7 18.9 22.0 25.2

20 24.1 30.5 36.7 41.5 50.0

40 30.8 52.4 70.1 82.3 98.2

60 44.7 63.0 99.7 101.5 123.4

80 89.5 91.5 110.5 168.8 210.7

0 20 40 80 160

10 12.5 15.7 18.9 22.0 25.2

20 24.1 30.5 36.7 41.5 50.0

40 30.8 52.4 70.1 82.3 98.2

60 44.7 63.0 99.7 101.5 123.4

80 89.5 91.5 110.5 168.8 210.7

DTfall

STfall

DTrise

STrise

Difficulties Changing cell size affect neighboring gates’ delay

10

89

6

4

6

6

0

0

10

8

25

23

31

29

19

13

108

5

4

6

6

0

0

13

10

26

25

32

31

21

Capacitance increase

Slewdecrease

Difficulties Other constraints:

◦ Capacitance constraint◦ Slew constraint◦ Wire delay◦ Area constraint

◦ We don’t consider these in this tutorial

Problem Formulation Given a design D with timing constraints, determine the cell type for each cell such that the following objective function is minimized:

Problem Formulation Objective function:

We define the dummy variables as negative margin to replace the max function

𝑎𝑢𝑑𝑢→𝑣 𝑎𝑣

Problem Formulation Minimize:

Constraints:

Constraints are extremely difficult to model!

Lagrangian Relaxation We integrate the constraints to the original objective function and obtain the Lagrangian-Relaxed Subproblem (LRS):

If we set :

Lagrangian Relaxation Based on Kuhn-Tucker conditions, the sum of multipliers on incoming arcs of a node must be equal to the sum of multipliers on its outgoing arcs.

𝑎𝑠1

𝑎𝑠 2

𝑎𝑣𝑎𝑢

𝑎𝑡1

𝑎𝑡 2

𝜇𝑢→𝑣

𝜇𝑠1→ 𝑡1

𝜇𝑠2→ 𝑡2

Lagrangian Relaxation We want to use the slack values computed by signoff timer directly.

We define:

Graph Model Use a graph model that captures the Lagrangian relaxed subproblem

Select cell size with the graph model

Graph Model What is the minimal cost selection?

2

5 1

4

1

23

61

8

Graph Model What is the minimal cost selection?

2

5 1

4

1

23

61

8 11

Graph Model What is the minimal cost selection?

2

5 1

4

1

23

61

8

12

86

23

7

9

42

53

3

3

5

4

Graph Model What is the minimal cost selection?

2

5 1

4

1

23

61

8

12

86

23

7

9

42

53

3

3

5

4

25

Graph Model◦ Begin with an arbitrary size selection◦ Define reference cell types as the current selected cell types◦ For node weight, we consider:

◦ Leakage power of cell type◦ Gate delay change without changing downstream cell types

◦ For edge weight, we consider:◦ Gate delay change due to change of downstream cell types

Graph Model Reference delay of timing arc k of cell i with type j:

Approximate delay under change of fanout cells:

Weight of a subnode :

Weight of an edge from to :

Graph Model

The Algorithm Produce an initial arbitrary solution

Run static timing analysis

While objective function is not converge◦ Update Lagrange multipliers◦ Choose size with dynamic programming using the graph model◦ Run static timing analysis◦ Update objective function

Refrences [1] M. M. Ozdal, S. Burns, J. Hu, "Gate Sizing and Device Technology Selection Algorithms for High-Performance Industrial Designs", ICCAD 2010