DLDA - M_09

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S.E. Sem. III [CMPN]

Digital Logic Design and Applications May '09 : Mumbai University − Examination Paper Solution

Time : 3hrs] [Marks : 100

N.B. : (1) Question No. 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

1. (a) Converter (670.17)8 into decimal, binary and hex. [6]

Soln.: (670.17)8

Octal to Decimal :

Step 1 : Get the octal no. 6 7 1 . 1 7

Step 2 : Write corresponding weights 82 81 80 . 8−1

8−2

Step 3 : Multiple columnwise 384 56 0 . 1/8 7/56

Step 4 : Add the contents of row 3 = 384 + 56 + 0 + 1 7

8 64+

= (440.23)10

Octal to Binary :

Step 1 : Get the octal no. 6 7 1 . 1 7

Step 2 : Convert each digits into binary 110 111 000 . 001 111

∴ (670.17)8 = (110 111 000 . 001 111)2

Octal to Hexadecimal :

Step 1 : Convert into binary (110 111 000 . 001 111)

Step 2 : Convert binary to hexadecimal (1 1011 1000 . 0011 11)2

Add three zeros on extreme left corner and

Add 2 zero on extreme right side.

Binary (0001 1011 1000 . 0011 1100) group of 4 bit,

Hexa number 1 B 8 . 3 C

(670.17)8 = (1B8.3C)16

1. (b) Design 16 : 1 MUX using 4 : 1 MUX. [6]

Soln.: Refer figure for implementation.

Description :

• The select inputs S1 and S0 of the multiplexers 1, 2, 3 and 4 are connected together.

• The select inputs S3 and S2 are applied to the select inputs S1 and S0 of MUX-5.

• The outputs Y1, Y2, Y3, Y4 are applied to the data inputs D0, D1, D2 and D3 of MUX-5 as

shown in figure.

(2) S.E. −−−− DLDA (CMPN)

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Fig.: 16 : 1 multiplexer using 4 : 1 multiplexers.

The operation can be summarized using table.

1. (c) Design a full subtractor using only NAND gates. [4]

Soln.: The full subtractor is a combinational circuit with three inputs A, B and Bin and two outputs D

and B.

Select Inputs Mux. Outputs Final output

S3 S2 S1 S0 Y1 Y2 Y3 Y4 Y

0 0 0 0 D0 D4 D8 D12 D0

0 0 0 1 D1 D3 D9 D13 D1

0 0 1 0 D2 D6 D10 D14 D2

0 0 1 1 D3 D7 D11 D15 D3

0 1 0 0 D0 D4 D8 D12 D4

0 1 0 1 D1 D3 D9 D13 D5

0 1 1 0 D2 D6 D10 D14 D6

0 1 1 1 D3 D7 D11 D15 D7

1 0 0 0 D0 D4 D8 D12 D8

1 0 0 1 D1 D3 D9 D13 D9

1 0 1 0 D2 D6 D10 D14 D10

1 0 1 1 D3 D7 D11 D15 D11

1 1 0 0 D0 D4 D8 D12 D12

1 1 0 1 D1 D3 D9 D13 D13

1 1 1 0 D2 D6 D10 D14 D14

1 1 1 1 D3 D7 D11 D15 D15

S3 S2 = 00

∴ MUX − 5

selects Y1

S3 S2 = 01

∴ MUX − 5

selects Y2

S3 S2 = 10

∴ MUX − 5

selects Y3

S3 S2 = 11

∴ MUX − 5

selects Y4

Examination Paper Solution (3)

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A is the minuend, B is subtrahend, Bin is the borrow produced by the previous stage, D is the

difference output and B0 is the borrow output.

Truth Table : The truth table for full subtractor is shown in table.

Table : Truth table for a full subtractor.

Input Output

A

(Minuend)

B

(Subtrahend)

Bin

Previous borrow (A −−−− B −−−− Bin) B0

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-maps and simplifications :

K-maps for D and B0 outputs are shown in fig.(a) and (b).

Simplification for difference output :

From fig. (a), D = in in in inABB ABB ABB ABB+ + +

= in in

EX-NOR EX OR

B (AB AB) B (AB AB)

−

+ + +��

∴ D = in inB (A B) B (A B)⊕ + ⊕

Let (A ⊕ B) = C ∴ D = in inB C B C+ = inB C⊕

∴ D = Bin ⊕ A ⊕ B

Simplification for borrow output :

From fig.(b), B0 = in inAB AB BB+ +

No further simplification is possible.

Logic diagram for full subtractor :

Logic diagram for the full subtractor is shown in figure.

For difference output

∴ D = in in in inABB ABB ABB ABB+ + +

BBin

A 00 01 11 10

0 0 1 0 1

1 1 0 1 0

(a) K-map for D

inABB inABB

inABB inABB

For borrow output

∴ B0 = in inAB AB BB+ +

BBin

A 00 01 11 10

0 1 1 1 1

1 0 0 1 0

(b) K-map for B0

Group 1 : inAB Group 2 : AB

Group 3 : BBin


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Fig.: Logic diagram for a full subtractor.

1. (d) Simplify the following using Boolean Laws : [4]

(i) A AB ABC ABCD+ + + (ii) A[B C(AB AC)]+ +

Soln.:

(i) A AB ABC ABCD+ + +

A + B + AB(C CD)+ (∵ A + AB = A + B)

A + B + AB(C D)+ (∵ A (B + C) = AB + AC)

A + B + ABC ABD+

A + ABC B BAD+ +

A + BC B AD+ +

A + AD B BC+ +

A + D + B + C

A + B + C + D

(ii) A[B C(AB AC)]+ +

= A [B + C (AB.AC)] (De-Morgan 2 law = A B AB+ = )

= A [B + C (A B) . (A C)]+ + (De-Morgan 1 law = A B A B+ = + )

= A [B + C (A.A A.B A.C B.C)]+ + +

= A [B + C (0 A.B A.C B.C)]+ + + (A.A 0)=

= A [B + C.0 + A.BC A.CC B.CC]+ + (A.0 = 0)

= A [B + 0 + A.BC 0 0]+ +

= AB + A.A.B.C

= AB + 0

= AB

2. (a) Simplify using K-map, obtain SOP equation and realize using only NAND gates. [10]

f (A, B, C, D) = π M (1, 2, 3, 8, 9, 10, 11, 14) + d (7, 15)

Soln.:

f (A, B, C, D) = π M (1, 2, 3, 8, 9, 10, 11, 14) + d (7, 15)

(1) The given Expression :

Y = M1 M2 M3 M8 M9 M10 M11 M14 + d (7, 15)


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(2) In K-map inter, 0's corresponding to these mixtures, inter X's for don't cars and inter 1's in the

remaining cells as shown in figure for the further simplification :

f (ABCD) = BC BD ACD AB+ + +

(3) Logic Diagram :

Step 1 :

Step 2 : AND – OR – NOT into NAND – NAND logic :

Replace every AND by NAND

every OR by a bubbled OR

every by a NAND invertors to get NAND-NAND logic

CD CD CD CD CD

AB 00 01 11 10

AB 00

1 0

0 1

0 3

0 2

AB 01

1 4

1 5

× 7

1 6

AB 11

1 12

1 13

× 15

0 14

AB 10

0 8

0 8

0 11

0 10

1 2

3

4

A B C D

f (A, B, C, D)

A B C D

f (A, B, C, D)


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Step 3 : Draw circuit using only NAND gate.

2. (b) Consider a chemical mixing tank for which there are 3 variables of interest : liquid level, pressure

and temperature. The alarm will be triggered under the following conditions : [10]

(i) Low level with high pressure (ii) High level with low pressure

(iii) High level with low temperature and high pressure

Design the system, implement using only NOR gates.

Soln.: (i)

Input

L P T Output

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

(ii) POS expression

0 = (L + P) (L P T)+ +

(iii) Logic Diagram NOR gates.

Step 1 : Implementing the given expression using AND-OR-NOT. The implementation

using AND-OR-NOT gates as shown in logic figure.

A B C D

PT PT PT PT PT L 00 01 11 10

L 0

0 0

0 1

1 3

1 2

L 1

1 4

1 5

0 7

1 6

T L P

O


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Step 2 : Replace OR by NOR

AND by bubbled AND

NOT by NOR inverter with the replacement, the current.

Step 3 : Implementing circuit using only NOR gates

3. (a) Design BCD to 7-segment code converter. [10]

Soln.:

BCD to 7 Segment Display Decoder

In most practical applications, seven segment displays are used to give a visual indication of the

output states of digital ICs such as decade counters, latches etc. These outputs are usually in four

bit BCD (binary coded decimal) form, and are thus not suitable for directly driving seven segment

displays. The special BCD to seven segment decoder / driver ICs are used to convert the BCD

signal into a form suitable for driving these displays. In this sections, we are going to study LED

and LCD decoders / drivers for seven segment displays. Let us tabulate the segments activated

during each digit display.

Digit Segments Activated Display

0 a, b, c, d, e, f

1 b, c

2 a, b, d, e, g

3 a, b, c, d, g

T L P

T L P

b c

a b c

d

f e g

a b

d

e g

a b c

d

g


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4 b, c, f, g

5 a, c, d, f, g

6 a, c, d, e, f, g

7 a, b, c

8 a, b, c, d, e, f, g

9 a, b, c, d, f, g

From the above table we can determine the truth table for BCD−to−7 segment decoder / driver.

This truth table also depends on the construction of 7-segment display. If 7-segment display is

common anode, the segment driver output must be active low to glow the segment. In case of

common cathode type 7-segment display, the segment driver output must be active high to glow

the segment. Following table shows the truth tables for both BCD-to 7 segment decoder / driver

with common anode display and with common cathode display.

Digit A B C D a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 1 0 1 1

Table : Truth table for BCD−−−−to−−−−common−−−−cathode 7-segment decoder/driver

a b c

d

f g

a

c

d

f g

a

c

d

f e g

a b c

a b c

d

f e g

a b c

d

f g


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K-map Simplification

Digit A B C D a b c d e f g

0 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 1 1 0 0 1 1 1 1

2 0 0 1 0 0 0 1 0 0 1 0

3 0 0 1 1 0 0 0 0 1 1 0

4 0 1 0 0 1 0 0 1 1 0 0

5 0 1 0 1 0 1 0 0 1 0 0

6 0 1 1 0 0 1 0 0 0 0 0

7 0 1 1 1 0 0 0 1 1 1 1

8 1 0 0 0 0 0 0 0 0 0 0

9 1 0 0 1 0 0 0 0 1 0 0

Table : Truth table for BCD−−−−to−−−−common−−−−anode 7-segment decoder/driver

Let us design the combinational circuit for common cathode 7-segment display / driver.

(10) S.E. −−−− DLDA (CMPN)

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Logic Diagram :

3. (b) Draw the 2-input TTL NAND gate and explain. List important characteristics of TTL family. [10]

Soln.:

Two Input TTL-NAND Gate (Totem Pole Output) : A two input TTL-NAND gate is shown in figure 1. A and B are the two inputs while Y is the

output terminal of this NAND gate.

Fig.1 : Two input TTL-NAND gate Fig.2 : Transistor Q1 is replaced by

its equivalent.

Operation : In order to understand the operation of this circuit, let us replace transistor Q1 by its equivalent

circuit as shown figure 2.


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1. A and B are the input terminals. The input voltages A and B can be either LOW (zero volts

ideally) or HIGH (+ VCC ideally).

2. A and B both LOW : If A and B both are connected to ground, then both the B-E junctions

of transistor Q1 are forward biased.

• Hence diodes D1 and D2 in figure will conduct to force the voltage at point C in figure 2 to 0.7 V.

• This voltage is insufficient to forward bias base-emitter junction of Q2. Hence Q2 will

remain OFF.

• Therefore its collector voltage VX rises to VCC.

• As transistor Q3 is operating in the emitter follower mode, output Y will be pulled up to

high voltage.

∴ Y = 1 (HIGH) … For A = B = 0 (LOW)

• The equivalent circuit for this input condition is shown in figure 3(a).

(a) Equivalent circuit for A = B = 0. (b) Equivalent circuit for A = 1, B = 0.

(c) Equivalent circuit for A = B = 1

Fig.3 3. Either A or B LOW : If any one input (A or B) s connected to ground with the other

terminal left open or connected to +VCC, then the corresponding diode (D1 and D2) will

conduct.

(12) S.E. −−−− DLDA (CMPN)

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• This will pull down the voltage at 'C' to 0.7 V.

• This voltage is insufficient to turn ON Q2. So it remains OFF.

• So collector voltage VX of Q2 will be equal to VCC. This voltage acts as base voltage for Q3.

• As Q3 acts as an emitter follower, output Y will be pulled to VCC.

∴ Y = 1 if A = 0 and B = 1

if A = 1and B = 0

• The equivalent circuit for this mode is shown in figure 3(b).

4. A and B both HIGH : If A and B both are connected to +VCC, then both the diodes D1 and

D2 will be reverse biased and do not conduct.

• Therefore diode D3 is forward biased and base current is supplied to transistor Q2 via R1 and D3.

• As Q3 conducts, the voltage at X will drop down and Q3 will be OFF, whereas voltage at

Z (across R3) will increase to turn ON Q4.

• As Q4 goes into saturation, the output voltage Y will be pulled down to a low voltage.

• The equivalent circuit for this mode of operation is shown in figure 3(c).

• This discussion reveals that the circuit operates as a NAND gate.

Standard TTL Characteristics : In 1964 Texas Instruments Corporation introduced the standard RRL ICs, 54/74 series. There are

several series / subfamilies in the TTL family of logic devices. We first examine the electrical

characteristics of the standard 74 series. Later we introduce the other TTL series and compare

their characteristics with those of the standard series.

Supply voltage and temperature range : Both the 74 series and 54 series operate on supply voltage of 5V. The 74 series works reliably

over the range 4.75V to 5.25V, while the 54 series can tolerate a supply variation of 4.5 to 5.5V.

he 74 series devices are guaranteed to work reliably over a temperature range of 0 to 70°C where

as 54 series devices can handle temperature variations from −55 to +125°C. From the above

values we can say that 54 series devices have greater tolerance of voltage and temperature

variations. Hence, these devices are used where it is necessary to maintain reliable operation over

an extreme range of conditions. For example, in military and space application. The only disadvantage of these devices is that they are expensive.

Voltage Levels and Noise Margin : Table shows the input and output logic voltage levels for the standard 74 series. The minimum

and maximum values shown in the table are for worst case conditions of power supply,

temperature and loading conditions.

Voltages Minimum Typical Maximum

VOL − 0.2 0.4

VOH 2.4 3.4 −

VIL − − 0.8

VIH 2.0 − −

Table : Voltage levels

Looking at the table we can say that, in the worst case, there is difference of 0.4V between the

driver output voltages and the required load input voltages. For instance, the worst-case low

values are

VOL(max) = 0.4V driver output

VIL(max) = 0.8V load input

Similarly, the worst-case high values are

VOH(min) = 2.4V driver output

VIH(min) = 2V load input

In either case, the difference is 0.4V. This difference is called noise margin. For TTL, Low state

noise margin, VNL and high state noise margin, VNH both are equal and 0.4V. This is illustrated in


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Figure. It provides built-in protection against noise. It ensures reliable operation of the device for

induced noise voltages less than 0.4V.

Power Dissipation and Propagation Delay : A standard TTL gate has an average power dissipation of about 10 mW. It may vary from this

value because of signal levels, tolerances, etc. We know that, the propagation delay time is the

time it takes for the output of a gate to change after the inputs have changed. The propagation

delay time of a TTL gate is approximately 10 nanoseconds.

Fan-Out : A standard TTL output can typically drive 10 standard TTL inputs. Therefore, standard TTL has

fanout 10.

Table summarizes the characteristics of standard TTL

Characteristics Values

Supply voltage For 74 series − (4.75 to 5.25) units

For 54 series − (4.5 to 5.5) units

Temperature range For 74 series − (0°C to 70°C)

For 54 series − (−55° to 125°C)

Voltage levels VOL(max) − 0.4V

VOH(max) − 2.4 V

VIL(max) − 0.8 V

VIH(min) − 2.0 V

Noise margin 0.4V

Power dissipation 10 mW per gate

Propagation delay Typically 10 ns

Fanout 10

Table : Standard TTL characteristics

4. (a) Design a BCD adder using 4-bit binary adders and explain. [10]

Soln.: • A BCD adder adds two BCD digits and produces a BCD digit A-BCD cannot be greater than 9.

• The two given BCD numbers are to be added using the rules of binary addition.

• If sum is less than or equal to 9 and carry - 0, then no correction is necessary. The sum is

correct and in the true BCD form.

• But if sum is invalid BCD or carry - 1, then the result is wrong and needs correction.

• The wrong result can be corrected by adding six (0110) to it.

Noise margin (VNH)

Noise margin (VNL)

VIH(min)

2V

VIL(max)

0.8V

0V 0V

0.4V

VOL(max)

2.4V

VOH(min)

5V 5V

Logic 1 Logic 1

Logic 0 Logic 0

VNH = VOH(MIN) – VIH(MIN)

= 2.4 − 2 = 0.4V

VNL = VIL(MAX) – VOL(MAX)

= 0.8 − 0.4 = 0.4V

Output voltage

ranges

Input voltage

ranges

Fig. TTL logic levels and noise margin

(14) S.E. −−−− DLDA (CMPN)

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Block diagram of BCD adder :

• From the points stated above, we understand,

that the 4-bit BCD adder .should consist of the

following blocks.

1. A 4-bit binary adder to add the given numbers A and B.

2. A combinational circuit to check if sum is

greater than 9 or carry = 1.

3. One more 4-bit binary adder to add six

(0110) to the incorrect sum if sum > 9 or

carry = 1.

• The block diagram of such a BCD adder is

shown in figure1.

• So we have to design the combinational circuit

that senses if sum is greater than 9 or Carry = 1.

Design of Combination Circuit :

• The output of combinational circuit should be 1 if the sum produced by adder 1 is greater

than 9 i.e. 1001. The truth table is as follows :

Table : Truth table for combinational circuit design.

Write K-map : The K-map for Y output of the combinational circuit is as shown figure 2.

Fig.1 : Block diagram of BCD adder.

Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Sub bits of

adder-1

Sum is valid BCD number.

∴ Y = 0

Sum is invalid BCD number.

∴ Y = 1

For Y output

S1S2

S3S2 00 01 11 10

00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

10 0 0 1 1

Fig.2 : K-map for Y output. Group 2 : S3S1

Group 1 : S3S2


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• The Boolean expression is,

Y = S3S2 + S3S1

The BCD adder is shown in figure 3.

• The output of the combinational circuit should be 1 if Cout of adder-1 is high. Therefore Y is

ORed with Cout of adder 1 as shown in figure 3. • The output of combinational circuit is connected to B1B2 inputs of adder-2 and B3 = B1 = 0 as

they are connected to ground permanently. This make B3 B2 B1 B0 = 0 1 1 0 if Y' = 1.

• The sum outputs of adder-1 are applied to A3A2A1A0 of adder-2. The output of

combinational circuit is to be used as final output carry and the carry output of adder-2 is to

be ignored.

Operation :

Case 1 : Sum ≤ 9 and carry = 0.

� The output of combinational circuit Y' = 0. Hence B3 B2 B1 B0 = 0000 for adder-2.

• Hence output of adder-2 is same as that of adder-1.

Fig.3 : 4-bit BCD adder.

Case II : Sum > 9 and carry = 0.

• If S3 S2 S1 S0 of adder-1 is greater than 9, then output Y' of combinational circuit becomes 1.

• ∴ B3 B2 B1 B0 = 0110 (of adder-2).

• Hence six (011) will be adder to the sum output of adder-1.

• We get the corrected BCD result at the output of adder-2.

Case III : Sum ≤ 9 but carry = 1.

• An carry output of adder-1 is high, Y' = 1.

• ∴ B3 B2 B1 B0 = 0 1 1 0 (of adder-2).

• ∴ 0 1 1 0 will be added to the sum output of adder-1.

• We get the corrected BCD result at the output of adder-2.

Thus the four bit BCD addition can be carried out using the binary adder.

(16) S.E. −−−− DLDA (CMPN)

16

4. (b) Design a MOD-6 synchronous up-counter and explain its operation. [10]

Soln.:

Flip-flops required : 2n ≥ N

N = 6

n = 3

i.e., three flip-flops required.

• The principle of operation of a 2-bit synchronous counter to a 3-bit counter shown in figure 1.

• FF-A acts as a toggle FF since JA = KA = 1.

• QA output of FF-A is applied to JB as well as KB. Hence if QA = 1 at the instant of triggering,

then FF-B will toggle but if QA = 0 then FF-B will not change its state.

• QA and QB are ANDed and the output of AND gate is applied to JC and KC.

• Hence when QA and QB both are simultaneously high, then JC = KC = 1 and FF-C will toggle.

Otherwise there is no change in the state of FF-3.

So in general we can say that each FF should have its J and K inputs connected such that

they are high only when the outputs of all lower order FFs are in the high state.

Fig.1 : A 3-bit synchronous binary counter.

Operation :

Initially all the FFs are in their rest state. ∴ QC QB QA = 0 0 0

1st clock pulse :

• FF-A toggles and QA changes to 1 from 0. But since QA = 0 at the instant o application of 1st

falling clock edge, JB = KB = 0 and QB does not change state. ∴ QB remains 0.

• Similarly QC also does not change state. ∴ QC = 0

∴ QC QB QA = 0 0 1 … after 1st clock pulse

2nd clock pulse :

• FF-A toggles and QA becomes 0.

• But at the instant of application of 2nd falling clock edge QA was equal to 1.

Hence JB = KB = 1. Hence FF-B will toggle and QB becomes 1.

• Output of AND gate is 0 at the instant of negative clock edge. So JC = KC = 0. Hence QC remains 0.

∴ QC QB QA = 0 1 0 … after the 2nd

clock pulse

3rd clock pulse :

• After the 3rd clock pulse, the outputs are QC QB QA = 0 1 1.

4th clock pulse :

• Note that QB = QA = 1. Hence output of AND gate = 1 and JC = KC = 1, at the instant of application of 4th negative edge of the clock.


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• Hence on application of this clock pulse, FF-C will toggle and QC changes from 0 to 1.

• FF-A toggles as usual and QA becomes 0.

• Since QA was equal to 1 earlier, FF-B will also toggle to make QB = 0.

∴ QC QB QA = 1 0 0 … after the 4th clock pulse

• Thus the counting progresses.

• After the 7th clock pulse the output is 111 and after the 8

th clock pulse, all the flip-flops toggle

and change their outputs to 0. Hence QC QB QA = 0 0 0 after the 8th pulse and the operation

repeats.

• Table summarizes operation of the three bit synchronous counter.

Table : Summary of operation of a 3-bit synchronous counter.

Clock QC QB QA

0 0 0 0

1st (↓) 0 0 1

2nd (↓) 0 1 0

3rd (↓) 0 1 1

4th (↓) 1 0 0

5th (↓) 1 0 1

6th (↓) 1 1 0

7th (↓) 1 1 1

Fig.2 : Timing diagram for a 3-bit synchronous counter.

Timing diagram : • Timing diagram for a 3-bit synchronous counter is shown in figure 2.

• Note that the waveforms of synchronous counter are exactly same as those of an

asynchronous counter.

5. (a) Simplify using K-map and realize using NOR gates. [10]

f (A, B, C, D) = π m (1, 3, 7, 11, 15) + d (0, 2, 5, 8, 14)

Soln.:

f (A, B, C, D) = π m (1, 3, 7, 11, 15) + d (0, 2, 5, 8, 14)

(1) The given expression

Let Y = M1 M3 M7 M11 M15 + d (0, 2, 5, 8, 14)

(2) In K-map, enter 0's corresponding to those mixtures

enter ×'s for don't corresponds and

enter 1's in the remaining cells

(18) S.E. −−−− DLDA (CMPN)

18

(3) Logic diagram

Step 1 :

Step 2 : AND-OR-NOT into NOR-NOR logic

Replace entry AND by bubbled AND entry OR by NOR

entry NOT by NOR

Step 3 : Implements circuit using only NOR gates

5. (b) Draw a 4-bit Johnson counter using shift register and prove that it is "Divide by 4" logic. [10]

Soln.:

• In the ring counter the outputs of FF-3 were connected directly to the inputs of FF-0 i.e., Q3

to J0, 3Q to K0.

• Instead if the outputs are cross coupled to the inputs i.e., if Q3 is connected to K0 and 3.5Q

connected to J0 then the circuit is called as twisted ring counter or Johnson's counter.

CD CD CD CD CD

AB 00 01 11 10

AB 00

× 0

0 1

0 3

× 2

AB 01

1 4

× 5

0 7

1 6

AB 11

1 12

1 13

0 15

× 14

AB 10

× 8

1 9

0 11

1 10

A B C D

y

A B C D

O

A B C D

y


19

• The Johnson's counter is shown in figure 1.

• All the flip-flops are negative edge triggered, and clock pulses are applied to all of them

simultaneously.

• The clear inputs of all the flip-flops are connected together and connected to an external clear

signal. Note that all these clear inputs are active low inputs.

Operation : • Initially a short negative going pulse is applied to the clear input of all the flip-flops. This

will reset all the flip-flops. Hence initially the outputs are,

Q3 Q2 Q1 Q0 = 0 0 0 0

• But 3Q = 1 and since it is coupled to J0 it is also equal to 1.

∴ J0 = 1 and K0 = 0 … Initially

On the first falling edge of clock pulse : • As soon as the first negative edge of clock arrives, FF-0 will be set. Hence Q0 will become 1.

• But there is no change in the status of any other flip-flop.

• Hence after the first negative going edge of the clock the flip-flop outputs are,

Q3 Q2 Q1 Q0 = 0 0 0 1

On the second negative going clock edge :

� Before the second negative going clock edge, Q3 = 0 and 3Q = 1. Hence J0 = 1 and K0 = 1.

Also Q0 = 1. Hence J1 = 1.

• Hence as soon as the second falling clock edge arrives, FF-0 continues to be in the set mode

and FF-1 will now set. Hence Q1 will become 1 and 1Q = 1.

• There is no change in the status of any other flip-flop. • Hence after the second clock edge the outputs are,

Q3 Q2 Q1 Q0 = 0 0 1 1

• Similarly after the third clock pulse, the outputs are

Q3 Q2 Q1 Q0 = 0 1 1 1

• And after the fourth clock pulse, the outputs are

Q3 Q2 Q1 Q0 = 1 1 1 1

Note that now 3Q = 0, i.e., J0 = 0 and K0 = 1.

• Hence as soon as the fifth negative going clock pulse strikes, FF-0 will reset. But the outputs

of the other flip-flops will remain unchanged. So after the fifth clock pulse, the outputs are,

Q3 Q2 Q1 Q0 = 1 1 1 0 … after the 5th clock pulse

• This operation will continue till we reach the all zero output state. (i.e., Q3 Q2 Q1 Q0 = 0 0 0 0)

• The operation of Johnson's counter is summarised in table.

Fig.1 : Twisted ring counter or Johnson counter.

(20) S.E. −−−− DLDA (CMPN)

20

CLEAR CLK Q3 Q2 Q1 Q0 State number Decimal

equivalent

Initially 0 0 0 0 1 0

1 ↓ 0 0 0 1 2 1

1 ↓ 0 0 1 1 3 3

1 ↓ 0 1 1 1 4 7

1 ↓ 1 1 1 1 5 15

1 ↓ 1 1 1 0 6 14

1 ↓ 1 1 0 0 7 12

1 ↓ 1 0 0 0 8 8

1 ↓ 0 0 0 0 1 0

� Note that there are 8 distinct states of output.

In general we can say that the number of states of a Johnson's counter is twice the number of

flip-flops used. Therefore, for 4 flip-flops, states will be 8, 5 flip-flops states will be 10 and

for 8 flip-flops states will 16.

Waveforms for Johnson's counter The waveforms for a 4-bit Johnsons counter are shown in figure.

Fig.2: Waveforms of Johnson counter.

6. (a) Simplify using Quine McClusky method. [10]

f (A, B, C, D) = π m (0, 2, 3, 6, 7, 8, 9, 12, 13)

Realize the equation using any universal gate.

Soln.:

f (A, B, C, D) = π m (0, 2, 3, 6, 7, 8, 9, 12, 13)

= ∑ M (1, 4, 5, 10, 11, 14, 15)

(1) Group the minterms according to number's of 1's.

Binary Representation Group Minterms

A B C D

1 1 0 0 0 1

4 0 1 0 0

2 5 0 1 0 1

10 1 0 1 0

3 11 1 0 1 1

14 1 1 1 0

4 15 1 1 1 1


21

(2) Group the minterms to form Point :

(3) Group the minterm to form ______ .

(4) Collect all the prime implicant

f (A, B, C, D) = ACD ABC AC+ +

(5) Prepare the PI table.

PI term Decimal

represent 1 4 5 10 11 14 15

A C D � 1, 5 ×

A B C � 4, 5 ×

A C � 10, 11, 14, 15

In the PI table find the column only 1 cross (×) and encircle these (×) points. Put (�) in front

of the corresponding PI's.

These (�) marked PI in above table on the essential prime implicants.

Hence simplified expression for y,

y (A, B, C D) = ACD ABC AC+ +

(6) Logic diagram :

Step 1 :

Step 2 : AND-OR-NOT into NAND-NAND logic

Replace entry AND by NAND

entry OR by bubbled OR

entry inverts by NAND invert to get NAND-NAND logic.

× × × ×

×

×


A B C D

1 1 − 5 0 − 0 1

4 − 5 0 1 0 −

2 10 − 11 1 0 1 −

10 − 14 1 − 1 0

3 11 − 15 1 − 1 1

11 − 15 1 1 1 −

ACD

ABC Prime implicant


A B C D

2 10−11−11−15 1 − 1 −

10−14−11−15 1 − 1 −

AC is prime

implicants

A B D

y (A, B, C, D)

C

(22) S.E. −−−− DLDA (CMPN)

22

Step 3 : Draw circuit using only NAND gates :

6. (b) Implement the following expression using 8 : 1 MUX. [10]

f (A, B, C, D) = ∑ m (0, 1, 5, 7, 9, 10, 15)

Soln.: Below figure shows the implementation of given Boolean function with 8 : 1 multiplexer.

7. Write short notes on : [20]

7. (a) De Morgan's Theorems

The two theorems suggested by De-Morgen and which are extremely useful in Boolean algebra

are as follows :

Theorem 1 : AB A B= + : NAND = Bubbled OR

• This theorem states that the complement of a product is equal to addition of the complements.

• This rule is illustrated fig.1. The left hand side (LHS) of this theorem represents a NAND

gate with inputs A and B whereas the right hand side (RHS) of the theorem represents an OR

gate with inverted inputs.

A B D

y (A, B, C, D)

C

A B D

y (A, B, C, D)

C

D0 D1 D2 D3 D4 D5 D6 D7

A 0 1 2 3 4 5 6 7

A 8 9 10 11 12 13 14 15

A 1 A 0 0 A 0 1

A 1 0

D0

D1

D2

D3

D4

D5

D6

D7

8 : 1

MUX y


23

• This OR gate is called as "Bubbled OR". Thus we can state De-Morgans first theorem as,

NAND = Bubbled OR

Fig.1 : Illustration of De-Morgan's first theorem.

This theorem can be verified by writing a truth table as shown in fig.2.

Theorem 2 : A B A.B+ = : NOR = Bubbled AND

• The LHS of this theorem represents a NOR gate with inputs A and B whereas the RHS

represents an AND gate with inverted inputs.

• This AND gate is called as "Bubbled AND". Thus we can state De-Morgan's second theorem as :

NOR = Bubbled AND

Fig.3 : Illustration of De-Morgan's second theorem.

• This theorem can be verified by writing a truth table for both the sides of the theorem

statement. This truth table is shown in fig.4, which shows that LHS = RHS.

EX-OR using NAND :

• The Boolean expression for EX-NOR is

Y = A � B = AB AB+ = X + Z

• Taking double inversion of RHS,

Y = X Z+ = X.Z … De Morgan's theorem

∴ Y = (A B) . (AB)

• This is the required expression for EX-NOR in

terms of only NAND gates. Figure shows the

realization.

Refer figure for implementation.

Fig.: EX-NOR using only NAND gates.

A B AB A B A B+

0 0 1 1 1 1

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 0 0 0

Fig.2 : Verification of the theorem AB A B= +

LHS RHS AB A B+ +

A B A B+ A B A.B

0 0 1 1 1 1

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 0

Fig.4 : Truth table to verify De-Morgan's theorem

LHS RHS A B A.B+ =

(24) S.E. −−−− DLDA (CMPN)

24

Description :

• The select inputs S1 and S0 of the multiplexers 1, 2, 3 and 4 are connected together.

• The select inputs S3 and S2 are applied to the select inputs S1 and S0 of MUX-5.

• The outputs Y1, Y2, Y3, Y4 are applied to the data inputs D0, D1, D2 and D3 of MUX-5 as

shown in figure.

The operation can be summarized using table.

7. (b) NOR as universal gate

Similar to NAND gate, the NOR gate is also a universal gate, since it can be used to generate the

NOT, AND, OR and NAND functions.

Select Inputs Mux. Outputs Final output

S3 S2 S1 S0 Y1 Y2 Y3 Y4 Y

0 0 0 0 D0 D4 D8 D12 D0

0 0 0 1 D1 D3 D9 D13 D1

0 0 1 0 D2 D6 D10 D14 D2

0 0 1 1 D3 D7 D11 D15 D3

0 1 0 0 D0 D4 D8 D12 D4

0 1 0 1 D1 D3 D9 D13 D5

0 1 1 0 D2 D6 D10 D14 D6

0 1 1 1 D3 D7 D11 D15 D7

1 0 0 0 D0 D4 D8 D12 D8

1 0 0 1 D1 D3 D9 D13 D9

1 0 1 0 D2 D6 D10 D14 D10

1 0 1 1 D3 D7 D11 D15 D11

1 1 0 0 D0 D4 D8 D12 D12

1 1 0 1 D1 D3 D9 D13 D13

1 1 1 0 D2 D6 D10 D14 D14

1 1 1 1 D3 D7 D11 D15 D15

S3 S2 = 00

∴ MUX − 5

selects Y1

S3 S2 = 01

∴ MUX − 5

selects Y2

S3 S2 = 10

∴ MUX − 5

selects Y3

S3 S2 = 11

∴ MUX − 5

selects Y4

Fig.: 16 : 1 multiplexer using 4 : 1 multiplexers


25

NOT Function :

An inverter can be made from a NOR gate by connecting all of the inputs together and creating,

in effect, a single common input, as shown in Fig. 1.

Fig. 1 : NOT function using NOR gate

OR Function :

An OR function can be generated using only NOR gates. It can be generated by simply inverting

output of NOR gate; i.e. A B + = A + B. Fig. 2 shows the two input OR gate using NOR gates.

A B A+B A B A B + A B +

0 0 0 0 0 1 0

0 1 1 ≡ 0 1 0 1

1 0 1 1 0 0 1

1 1 1 1 1 0 1

Table : Truth table

AND Function :

AND function is generated using only NOR gates as follows : We know that Boolean expression

for AND gate is

Y = A. B

= A . B Rule 9 : [ A A = ]

= A B + DeMorgan’s Theorem 2

The above equation is implemented using only NOR gates as shown in the Fig. 3.

Fig. 2 : OR function using NOR gates

Fig. 3 : AND function using NOR gates

(26) S.E. −−−− DLDA (CMPN)

26

Note : Bubble at the input of NOR gate indicates inverted input.

A B A+B A B A B + A B +

0 0 0 0 0 1 0

0 1 0 ≡ 0 1 1 0

1 0 0 1 0 1 0

1 1 1 1 1 0 1

Table : Truth table

NAND Function :

NAND function is generated using only NOR gates as follows : We know that Boolean

expression for NAND gate is

Y = A . B

= A B + DeMorgan’s Theorem 1

= A B + Rule 9 : [ A A = ]

The above equation is implemented using only NOR gates, as shown in the Fig. 8.

Fig. 8 : NAND function using only NOR gates

A B A+B A B A B + A B + A B+

0 0 1 0 0 1 0 1

0 1 1 ≡ 0 1 1 0 1

1 0 1 1 0 1 0 1

1 1 0 1 1 0 1 0

Table : Truth table

7. (c) ALU

Arithmetic Logic Unit (ALU) :

• ALU is a very widely used and popular combinational circuit.

• It is capable of performing the arithmetic as well as the logic operations.

• ALU is the heart of any microprocessor.

• Figure 1 shows the block diagram of ALU IC 74181, Table 1 gives the pin description and

Figure 2 gives its pin configuration.

• 74181 is a 24-pin IC dual in line (DTP) package.

• A (A0 − A3) and B (B0 − B3) are the two 4 bit variables.


27

Table 1: Pin description of 74181

Pin Name Description

A0 − A3 Operated inputs

B0 − B3 Operand inputs

S0 − S3 Function select inputs

M Mode control input

nC Carry input (active low)

F0 − F3 Function output

A = B Comparator output (equality output)

G Carry generate output

P Carry propagate otput

n 4C + Carry output (active low)

• It can perform a total of 16 arithmetic operations which includes addition, subtraction,

compare and double operations.

• It provides many logic operations such as AND, OR, NOR, NAND EX-OR, compare etc on

the two four bit variables.

• 74181 is a high speed 4 bit parallel ALU.

• It is controlled by four function select inputs S0 − S3. These lines can select 16 different

operations for one mode (arithmetic) and 16 another operations for the other mode (logic).

• M is the mode control input. It decides the mode of operation to be either arithmetic or logic.

M = 0 For arithmetic operations

M =1 For logic operations

• G and P outputs are used when a number of 74181 circuits are to be used in cascade

alongwith 74182, the look ahead carry generator circuit to make the arithmetic operations

faster.

• When mode control input is high (M = 1), then the logic operations are performed on the

individual bits and all the internal carries are enabled.

Fig. 1 : Block diagram of ALU IC 74181 Fig. 2 : Pin configuration of the ALU IC 74181

(28) S.E. −−−− DLDA (CMPN)

28

• When mode control input is low (M = 0), the arithmetic operations are performed on the two

4-bit words and all the internal carriers are enabled.

• IC 74181 incorporates full internal carry lookahead. This enhances its speed of operation to a

great extent.

• It provides a ripple carry between the devices using the Cn+4 output. (see cascading of two

74181s).

• Or for exploiting the option of carry lookahead between the packages, we have to use the P

(carry propagate) and G (carry generate) outputs. This option should be used only when the

speed requirements are stringent.

• If low speed of operation is acceptable, the ripple carry operation using Cn+4 and Cn should be

exercised.

A = B Output : 1. A = B output indicates the logical equality of the two operands. This output goes HIGH when

the unit is in the subtract mode and A = B.

2. This output also goes high when all the four “Function outputs” are HIGH.

3. It is possible to wire AND the A = B outputs when more than one 74181s are being used. The

wire ANDing becomes possible because A = B is an open collector output. This enables us to

compare words which are longer than 4-bits.

Function tables : (If the question is 10 marks, then mention the functional table in details)

• Table 2(a) shows the function table for IC 74181. It is valid for the active high operands and

active high outputs, and with nC = 1 i.e. no carry.

Table 2(a): Function table for IC 74181 with active high data and nC = 1 (no carry)

Function Select Inputs Active high data and nC = 1

S3 S2 S1 S0 Logic operations (M = 1) Arithmetic operations (M = 0)

0 0 0 0 F = A (Inversion) F = A

0 0 0 1 F = A B+ (NOR) F = A + B

0 0 1 0 F = A.B F = A + B

0 0 1 1 F = 0 F = minus 1 (2’s comp)

0 1 0 0 F = AB (NAND) F = A plus A B

0 1 0 1 F = B (Invert) F = (A + B)plus A B

0 1 1 0 F = A ⊕ B (EXOR) F = A minus B minus 1

0 1 1 1 F = A B F = A B minus 1

1 0 0 0 F = A + B F = A plus AB

1 0 0 1 F = A B⊕ (EXNOR) F = A plus B

1 0 1 0 F = B F = (A + B ) plus AB

1 0 1 1 F = AB (AND) F = AB minus 1

1 1 0 0 F = logic 1 F = A plus A*

1 1 0 1 F = A + B F = (A + B) plus A

1 1 1 0 F = A + B (OR) F = (A + B ) plus A

1 1 1 1 F = A F = A Minus 1

Each bit is shifted to the next more significant position.

• The arithmetic operations listed in function Table 2(a), correspond to no carry input. They

will get modified if the carry input is present as shown in Table 2(b).

• It is possible to use IC 74181 with either active high inputs or with active low inputs. With

active low inputs the device produces active low outputs and with active high inputs it

produces active high outputs.


29

• The function table for active low inputs and outputs has been given in Table 2(b).

Table 2(b) : Function table for IC 74181 with active low data and nC = 0 (with carry).

Function Select Inputs Active Low data and nC = 0

S3 S2 S1 S0 Logic operations M = 0 Arithmetic operations M = 1

0 0 0 0 F = A (inversion) F = A minus 1

0 0 0 1 F = AB (NAND) F = AB minus 1

0 0 1 0 F = A B+ F = A B minus 1

0 0 1 1 F = 1 F = minus 1

0 0 1 1 F = A B+ F = A plus (A + B )

0 1 0 1 F = B (inversion) F = AB plus (A + B )

7. (d) TTL vs COMS logic family :

High Speed CMOS

The high speed CMOS devices have silicon gates instead of metal gates. This improved version

of CMOS ICs has higher switching speeds and higher output current capacity. The high speed

CMOS devices are pin compatible and functionally equivalent to TTL ICs with the same device

numbers.

Comparison of CMOS and TTL Families

Parameter CMOS TTL

Silicon gate

CMOS

Metal gate

CMOS 74 74LS 74AS 74ALS

VIH (min) 3.5 3.5 2.0 2.0 2.0 2.0

VIL (max) 1.0 1.5 0.8 0.8 0.8 0.8

VOH (min) 4.9 4.95 2.4 2.7 2.7 2.7

VOL (max) 0.1 0.05 0.4 0.5 0.5 0.4

VNH 1.4 1.45 0.4 0.7 0.7 0.7

VNL 0.9 1.45 0.4 0.3 0.3 0.4

Propagation

Delay (ns) 8 105 10 10 1.5 4

Power per

gate (mW) 0.17 0.1 10 2 8.5 1

Speed power

product or figure or

merit

1.4 pJ 10.5 pJ 100 pJ 20 pJ 12.8 pJ 4 pJ

Input

connection

Input cannot be left open. It has

to be connected to 0, or to VDD

or to the another input.

Input can be left open. It is treated as logic

high input.

Power

dissipation

Very less, but increases with

increase in switching speed

More than CMOS. It is constant, does not

depend on switching speed.

Fan out Fan−out is more than TTL

typically 50 Fan−out for TTL is 10.

Noise More susceptible to noise Less susceptible to noise.

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