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IEEE T RANS ACT I ONS ON E L t CI KON D E V I C E S . VOI. 40 . N O 4. APKIL. 1 Y Y 3 74

Drain-Induced Barrier Lowering inBuried-Channel MOSFETs

M i c h a e l J . Van de r T o1 and Savvas G. Chamber la in , Fellow, IEEE

Abstract-The concept of drain -induc ed barrier lowering inburied-channel MOSF ET i s not well understood. In the litera-ture, it is unclear as to whether or not buried-channel MOS-FETs are less resistant to drain-induc ed barrier lowering thansurface-channel MOSFETs. In this paper we clarify this con-fusion and experimentally demonstrate the relationship be-tween the threshold voltage and channel length reduction fornormally-on (inverting) BC-MOSFET s. These results are com -pared with similar measurements on surface-channel MOS-FETs. It is shown that BC-MOSFETs a re more prone to drain-induced barrier lowering when compared with surface-chann elMOSFETs. We derive a simple analytic model for thesubthreshold current in small-geometry BC-MOSFETs. Ouranalytic model shows good agreement with experimental mea-surements and with subthreshold cur rents obtained using a two-dimensional num erical simulator.

I . INTR ODUC TIONRAIN-IND UCED barrier lowering in short-channelD urface-channel MOSFETs is well known [ 11-[3].In surface-channel MOSFETs, the barrier-lowering ef-fect is observed through a shift in the threshold voltage a sa function of the drain bias for short-channel devic es. Theeffect of decreasing the channel lengths causes the d eple-tion region surrounding the source and drain diffusions toapproach each other. Depending upon the drain bias, theelectric field about the drain can penetrate into the sourceregion of the device. The potential barrier to electrons atthe source is significantly reduced due to this field pene-tration. As a result, the device can conduct significantdrain current due to an increase in electrons injected fromthe source.This mechanism is responsible for the strong depen-denc e of the subthreshold curre nt on the drain bias. Mor e-over, this subthreshold current will alter the thresholdvoltage characteristics as the drain bias is variedIn contrast, the concept of drain-induced barrier low-

Manuscript received January 23, 1991; revised November 1 , 1992 . Thi \work was supported by an individual operating research grant awarded toS . G . Chamberlain by the Natural Sciences and Engineering ResearchCouncil o f Canada . M. J . Van der To1 was supported by the Natural Sci-ences and Engineering Council of Canada Post-Graduate Sch olarship pro-gram and by the Bell-Northern Research Scholarship program . The reviewof this paper was arranged by Associate E ditor K . Shena i .M. J . Van der To1 was with the Department of Electr ical Engineering.University of Water loo , Wate r loo , Ont . , Canada N2L 3 GI . He is now withM T S , Bell-Northern Research Ltd., P.O. Box 35 1 . Station C, Ottawa ,Ont. , Canada K I Y 4H7.

S . G . Chamberlain is with the Department of Electr ical Engineering,University of Waterloo, Waterloo, Ont. . Canada N 2L 3G1.IEEE Log Number 9206634.

ering in buried-channel MOSFETs is not well under-stood. In the literature, it is uncle: : s to w hether or notburied-channel MO SFE Ts are less resistant to drain-in-duced barrier lowering than surface-channel MO SFE Ts.This is reflected in the conflicting published results re-garding the threshold voltage shift in BC-MOSFETs withchannel length reduction.Nishiuchi et a l . [4] compared small-geometry BC-MOSFET and small-geometry surface-channel MOS-FETs. It was demonstrated that the BC-MOSFET wasless sensitive to a shift in the threshold voltage with areduction in the channel length. In complete agreementwith these findings, Sze [ 5 ] has stated that the buried-channel d evice is less affected by this short-channel effectthan the conventional surface-channel MOSF ET. In con-trast, Wordeman and Dennard [6] critical of the work ofNishiuchi et al . , comparc .I urface-channel enhancementMOSFETs with buried-channel depletion MOSFETs.They concluded that the buried-channel device was lessresistant to drain-induced barrier lowering. This conclu-sion was based on their findings which showed burid-channel M OSFE Ts were more prone to a threshold volt-age shift as channel lengths are reduced. Ballay et al . 171also compared the threshold voltage shift in buried-ch;n-ne1 and surface-channel MO SF ET s as a function o f chan-nel length reduction. Their findings were in completeagreement with the work of Wordeman and Dennard. Thisfinding was further verified by Hu et a l . [SI. The authorsfound that buried-channel MOSFETs were more sensi-tive to drain-induced barrier lowering when comparedwith conventional surface-chann el MO SFE Ts. These re-sults completely contradict the results presented by Szeand Nishiuchi et a l . , but are confirmed by both Worde-man and Ballay et al .It is clear that there is confusion in the literature as towhether or not buried-channel MO SFETs are more or lessprone to drain-induced barrier lowering when comparedwith surface-channel MOSFETs.To clarify this confusion, the main goal of this paper isto experimentally demonstrate the relationship betweenthe threshold voltage and channel length reduction fornormally-on BC-MO SFETs . Th ese resul ts are comparedwith similar measurements on surface-channel MOS-FETs. By analyzing the threshold voltage as a functionof channel length we are able to deduce whether BC-MOSFETs are more or less prone to drain-induce d bar-rier lowering when com pared with surface-channel MOS-

0018-9383193$03.000 993 IEEE


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FETs. In the process, we derive an analytic expressionfor the subthreshold current in small-geometry BC -MOS-FETs. Our expression is less complicated than thesubthreshold current expression for p-channel BC-MOS-FETs proposed by Skotnicki et al . [9]. This allows for asimple physical understanding. Our analytic model iscompared with experimental measurements and sub-threshold currents obtained using a two-dimensional nu-merical simulator.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. N O . 4 . APRIL 1993

11. EXPERIMENTALE ASURE ME NTF THETHRESHOLD OLTAGEIn this section we discuss the techniques used to exper-imentally determine the threshold voltage for normally-on n-channel buried-channel MOSFETs, By measuringthe threshold voltage for BC-MOSFETs with varyingchannel lengths we can get a clear indication of the drain-induced barrier lowering (DIBL) present.Normally-on n-channel BC-MOSFETs are generallycharacterized by a negative threshold voltage and are typ-ically used as depletion-type d evices. H owev er, an inter-esting class of normally-on BC-MOSFETs exist for

which a threshold voltage in the normal sense does notexist. In these devices, the channel cannot be pinched offdue to the presence of surface pinning. In these n-channelBC-MOSFETs, the surface of the device becomes in-verted before the threshold voltage is reached. It is thislayer of holes that precludes device turn-of . As a result,a threshold voltage in normal sense does not exist as aninversion layer of holes is formed before the device canbe turned off. (This effect of surface pinning is particu-larly prevalent in normally-on BC-MOSFETs with deepchannel implants.) In order to address the concept ofdrain-induced barrier lowering in what we will call nor-mally-on (inverting) BC-MO SFET s, we must be able todefine what is meant by threshold voltage. For buried-channel MOSF ETs this is straightforward; the thresholdvoltage can be defined as the gate voltage that must beapplied to pinch off the device. This idea of pinch-off canbe applied to normally-on (inverting) BC-MOSFETs.However, the mechanism by which we arrive at pinch-offis defined differently. One approach is to apply a bulkbias. For deep, heavily implanted channels, large bulkbiases are required to deplete the channel region of thedevice. The second approach to initiating pinch-off innormally-on (inverting) BC-MOSFETs is to simulta-neously bias the source and drain terminals of the dev ice.In both instances, the effect upon the device is the sam e.Increasing the bulk-drain and bulk-source junctio n volt-age further reverse biases the p-n junction which extendsthe n-side depletion layer toward the surface. And by in-creasing the source-to-gate and drain-to-gate bias, thesurface depletion region is further extended towards thechannel region and pre-empts surface inversion. Thus wehave the surface depletion region extended toward then-side space-charge layer which itself is extending tow ardthe surface of the device. As a result we can achieve

VTH 0)1.00

000

-1.00

-2.00

-3.00

4.00

-5.00

-6 00

-7.00

-8.00

-9.00

-10.00O W 1.00 2.00 3 0 3 4.00 5.00 6.00 7.00

Channel Length L (pm)Fig. 1. Measured threshold voltage versus channel length. For the surfacechannel MOSFETs, the threshold voltage was measured with the Vs s = 0V, VB B= 0 V , and VD D= 0. 1 V . For the buried-channel MOSFETs, thethreshold voltage w as measured with the V s s = 9 .9 V , Vs e = 0 V , and VDD= 10.0V . The threshold voltage is given by the gate voltage at which thedrain current becomes I O nA. The measured results are indicated by theU.

pinch-off. In our analysis we will have chosen to bias thesource and drain terminal, while holding th e bulk terminalat ground, to achieve pinch-off.We are now in position to formulate the concept ofthreshold voltage in normally-on (inverting) BC-MOS-FETs. The threshold voltage for normally-on (inverting)BC-MOSFETs may be defined as the bias that must beapplied to the gate to pinch off the device in the presenceof a source and drain bias. Clearly, the definition is onsome unstable ground; what is meant by source and drainbias and how does one determine what voltage to apply?A suitable source V,, and drain V,, bias is determined byapplying an increasing voltage to the source and drain ter-minal such that V,, is

(1)With the gate biasing the device into inversion, the draincurrent is monitored. The source voltage and the drainvoltage at which the drain current becomes less then 10nA is defined as V,,,, an d VDbH, espectively. It is thissource and drain bias that is then used to bias the devicefor threshold voltage m easurements.The threshold voltage measurements fo r the normally-on (inverting) BC-MOSFETs were performed by mea-suring the gate transconductance as a function of the gatebias VG Gwhile maintaining the relation VDb, - VSsT, =0.1 V . The gate transconductance is determined indirectlyby measuring the incremental change in the drain currentin response to an incremental change in the g ate voltage.The gate voltage at which the drain current becomes lessthan 10 nA is deemed the threshold voltage VTH.

v,, = v,, - v,, = 0.1 v .


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V A N DE R TOL A N D C H A M B E R L A I N : D R A I N - I ND U C E D BARRI E R L O W E R I N G

-4.00

&00 -

-8.00

143

000 1.00 2 0 0 3.00 4 0 0 50 0 hOO 7 u oChannel Length L (pm )

Fig. 2. M easured threshold voltage versus chan nel length for the BC-MOSFET. The threshold vol tage for the buried-channel MOSFET's wasmeasured for drain biases of V D o= 10 .0 , 10 .9 , 11 .9 , 12 .9 , 13 .9 , and 14 .9V . The source voltage was held at Vss = 9 .9 V and the bulk bias was heldat Vs e = 0.0 V . Th e O show the measured results for channel lengths ofL = 6 , 5, 4, and 3 pm .

000

-2 00

-14.00 1 I 1 I I I I000 I 0 0 2.00 3u 3 4 0 0 5(10 60 0 71x1

Channel Length L (pm)Fig. 3. Measured threshold voltage versus ch annel length for the SC -MOSFET. The threshold vol tage for the buried-channel MOSFET's wasmeasured for drain biases of VDD = 0 . 1 , I . O , 2 .0 . 3 .0 , 4 .0 , and 5. 0 V .The source voltage was held at V ss = 0 . 0 V and the bulk bias was held atVss = 0.0 V . The o show the measured results for channel lengths of L= 6 , 5 , 4, an d 3 p m .

In order to compare drain-induced barrier lowering inburied-channel MOSFET's with surface-channel MOS-FET's, threshold voltage measurements were performedon normally-on n-channel (inverting) BC-M OSFE T's and

SC-MOSFET's with varying channel lengths. These re-sults are plotted in Fig. 1.To determine the effect of the drain bias on the thresh-old voltage for the buried-channel devices, the thresholdvoltage was measured as a function of the drain bias.These results are plotted in Fig. 2 . Similar measurementswere performed on the surface-channel devices. Thesemeasurements are plotted in Fig. 3 .

111. DRAIN-INDUCEDARRIERL O W E R I N GELATIONSHIPSIn this section we address the relationship between thethreshold voltage and the drain-to-source voltage for theburied-channel MO SFE T. It has been shown by Grotjohnand Hoefflinger [lo] and more recently by Chamberlainand Ramanan [ 2 ] that the variation of the threshold volt-age with respect to the drain-to-sou rce voltage for a short-

channel SC-MOSFET can be addressed as(2)

A = C,,,/(COX + CD) B = ( f , J " X ) / ( % A ( 3 )

VTH = VTHO - ( B / A )VD Swhere

and VTHo is the threshold voltage at zero drain-to-sourcebias, L is the channel length, and the parameter 7 is ageometry-dependent parameter used to model the DIBLeffect. For a surface-channel MOSFE T, C , represents th edepletion capacitance and is given by(4)

where +A is the surface potential in the SC-MOSFET andNEFFs the channel doping below the semiconductor sur-face.The relationship in (2) between VTH an d VD s for sur-face-channel MOSFET's is verified by the experimentalmeasurements plotted in F ig . 4.From our measurementsof the threshold voltage in the BC-M OSF ET as a functionof the drain-to-source voltage (illustrated in Fig. 5 ) , wemust conclu de that a relationship similar to (2 ) must exist.However, in the case of the buried-channel device, thedependence upon the channel length is more pronounced.The subthreshold current in a BC-MOSFET is domi-nated by diffusion current [ 111 and it can be expressed inthe following form [ 5 ] :

( 5 )where W Ax is the cross-sectional area of current flowin the buried channel, V, is the thermal voltage, pbo s theelectron mobility, and n (0) an d n ( L ) re the electron con-centrations in the buried c hannel near the so urce and drain,respectively. Under pinch-off conditions the channel po-tential k,, with respect to ground potential is given by


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0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50VDS

Fig. 4. Measured threshold voltage versus drain bias for the SC-MOS-FET. For each device of a given channel length, the threshold voltage wasmeasured for dra in b ia ses of V D D = 0.1, 1 O, 2 O, 3.0,4.0,nd 5.OV. T hesource voltage was held at Vss = 0.0 V and the bulk bias was held at Vs s= 0.0 V. The measured threshold vo ltages are given by the 0.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO . 4, APRIL 1993

0.00 0.50 1.00 1.50 2.W 2.50 3.00 3.50 4.00 4.50 5.00 5.50vDO - V S (v)

Fig . 5 . Measured threshold voltage versus drain bias for the BC-MOS-FET. F or each device of a given channel length, the threshold voltage wasmeasured for drain biases of V D D= 10.0, 10.9, 11.9, 12.9, 13.9, an d 14.9V . The sou rce voltage was held at Vss = 9. 9 V and the bulk bias was heldat Vs s = 0.0 V. T he measured threshold voltages are given by the 0. helargest variation of threshold voltage VTH with drain bias occurs for th eBC-MOSFET with a channe l length of 3 p m .

where

an d(7)

Here NO is the donor concentration of the implanted chan-nel region, N A s the substrate acceptor concentration, andxi is the implanted channel depth. The carrier densities inthe buried channel at the source and drain can be ex-pressed asn ( 0 ) = ND ex p (9)

(10)( L ) = NO ex p (A h ; )where Vss an d V D D are the source drain biases w ith respectto ground. For the above relationships to hold, both Vs san d V D D must be maintained above the channel potential.The area of current flow under subthreshold conditionsis given by the channel width Wan d the channel thicknessAx . Th e channel thickness can be approximated by m ak-

ing use of the potential distribution in the channel depthdirection under pinch-off conditions [121. The potentialdistribution is given by

where $ch is given in (6) an d x , is the position (in thechannel depth direction) of the maximum channel poten-tial. The channel thickness A x is delineated by the posi-tions where the maximum channel potential $ch falls byk T / q on either side of the channel maximum. These po-sitions occur on either side of the maximum channel po-tential at

resulting in a channel thickness of

Substitution of A x , n( O ) , an d n ( L ) into (5) we arr ive a tan expression for the subthreshold current in a long-chan-


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V A N DE R TOL A N D C H A MB ER LA IN : D R A IN -IN D U C ED BARRIER LOWERING 745

ne1 B C -MOSFET

Our expression for the channel potential $ch can be sim-plified in a manner analogous to [111. Using a Taylor se-ries expansion of the $& bout a gate potential of VT Hwecan approximate the channel potential as

. (VGG- VTH) + other terms. (16)Truncating the Ta ylor series after the second term , we canapproximate the channel potential as

117$ch = $0 + - VGG - VTH>

$0 = $ChI V C C = VTH

(17)where

(18)an d

Substituting the new expression for the channel potentialinto (15) yields a new exp ression for the subthreshold cur-rent in the BC-MOSFET

In the case of the short-channel BC-M OSF ET, we modelthe DIBL by modifying the subthreshold current expres-sion such that it exhibits a strong dependence upon thedrain-to-source voltage. W e introduce this dependence ina similar fashion as in [2], [ lo]. Let the drain-to-sourcevoltage dependence in (20) be modeled by the barrierheight 4B n the following manner:

where

TABLEIq/ { RATIO N D VTHo V ER SU S C H A N N E LLENGTH FO R TH E BC-MOSFET'S

3 2 . 1 2 2 - 6 . 5 44 0 . 4 7 3 - 4 . 6 95 0 .2 3 8 - 4 .2 96 0 .1 3 4 - 4 .1 0

and { s the DIBL parameter for the buried-channel MOS-FE T. The formulation of the DIBL for the short-channelBC-MOSFET in (22) allows us to define the thresholdvoltage dependence on the drain-to-source voltage. M ore-over, the ratio v / { , as we will show, is dependent uponthe channel length L . Let the threshold v oltage (for a par-ticular drain bias) to be defined as the gate voltage whenis zero giving

where, as in the case of the surface-channel device, VTHois the threshold voltage for zero drain-to-source bias. Itshould be clear to the reader that the ration y / { is deter-mined directly from the experimental m easurements; thisratio is given by the slope of the curves given in Fig . 5 .Table I shows the calculation of the 11/ { ratio and the zerodrain bias threshold voltage VTHo obtained using linearregression techniques on the data in Fig. 5 according tothe formula

where N is the number of data points. T he numerical valuefo r 11 can also be computed directly from the experimentalmeasuremen ts. Consider our expression for the subthresh-old current in the BC-M OSFE T given in (21). Taking thenatural logarithm s of both sides of our subthreshold equa-tion yields an expression of the form:

In (ZDs) = K + (VGG1lirTH) (25)where K is equal to a constant. The value of 11 for a par-ticular subthreshold curve is calculated using

1 AVGG - -l- Vccz - VGG,Vr A In ( I D S ) (26)

where the data points (IDs2,V G e ) and (IDsl VGG, are takendirectly from linear portion of the subthreshold curves.Once 11 is known, the value for { and be calculated usingthe q / { ratio. The subthreshold current, as a function ofthe drain-to-source voltage was measured for each of theburied-channel devices. T he calculated values for ( nd 17are given in Table 11.

-1 V, In ( I D s ~- n ( IDS,


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746 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. N O . 4. APRIL 1993

TABLE I1AN D CALCULATIONSSING HE BC-MOSFET SUBTHRESHOLDU R R E N TEASUREMENTS

3 4 .5 6 3 6 .6 2 3 1 1 . 1 1 3 19 .36 3 40 .044 7 .3 8 4 7 .7 2 4 7 .8 2 4 8 .1 0 4 8 .3 55 11 .18 5 11 .68 5 11 .89 5 12.02 5 12.276 17 .84 6 17.76 6 18.73 6 18.21 6 18.73L ( r m ) 9 L (pm) ll L ( rm ) 9 L ( rm) 9 L (pm) 9

3 9 .68 3 14.04 3 23 .58 3 41 .09 3 84 .964 3 .49 4 3 .65 4 3 .7 0 4 3 .8 3 4 3 .9 55 2 .66 5 2 .78 5 2 .83 5 2 .8 6 5 2 . 9 26 2 .3 9 6 2 .3 9 6 2 .4 0 6 2 .4 4 6 2 .5 1

IV . SUBTHRESHOLDUR R ENT ODELINGIn this section we compare our analytic model for thesubthreshold current in the buried-channel MOSFET withexperimental measurements and numerical simulations.The subthreshold current for the buried-channel MOS-FET, including the drain-induced barrier-lowering effect

is expressed as

ex p ( cc - VTH) ex p "> (27)17vt(Here we assumed that V D D - Vs s > 5 k T / q . ) The aboveexpression can be further simplified by assuming that thesource potential is always held at V, In ( N s D / N D ) voltsabove the channel potential (where NsD is the doping onthe source and drain implants which is assumed to be 2.0X lo2'~ m - ~ ) .he subthreshold current becom es

ex p ( ">Fig. 6 illustrates the comparison between the analyticmodel for the subthreshold current and the measuredsubthreshold current for a drain-to-source voltage of VDs= 2 V (i.e. , V D D = 11.9 V and Vs s = 9.9 V). The valuesfo r 11 and {a re taken from Ta ble 11. In orde r to get a betterJit with the analytical model, the values for the thresholdvoltage had to be modified by 10%; hese are within ex-perimental error. The parameters used for the subthresh-old model are summarized in Table 111.

Using a two-dimensional device simulator [131 we de-termined the subthreshold currents fo r the BC-MOS FET'swith channel lengths of 6, 5, 4 , an d 3 pm. Thes e resultsare given in Fig. 6 and show good agreement with ourmodel. In Table IV the 7 nd { parameters obtained fromthe two-dimensional simulations are listed. Both 17 an d {

IDS ( A )10-2

10-3

10"

10-5

10-'

IO-;1400 - 1 2 0 0 -1000 -800 - 600 400 -200 OW

Gate Voltage ( V )Fig. 6. Comparison between the measured subthreshold current and thesubthreshold current model for the BC-MOSFET. For buried-channelMOSFET's with channel lengths L = 3 , 4 , 5 , and 6 pm, the subthresholdcurrent was measured for a drain bias of V,, = 1 1 .9 V and a source biasof Vss = 9 .9 V . T he bulk bias was held at VBB= 0.0 V. The measuredsubthreshold current values are given by the 0 . The dashed lines indicatethe subthreshold current obtained using the analytic exp ression in (2 8) withNo = 2 .1 3 x 10l6 ~ m - ~ ,m = 1179 cm2 . V -I . s-' , W = 80 p m , andthe parameters in Table 111. Other device parameters include x, = 0 .7 2 5pm, x,, = 0 .0637 pm, N A = 5 .2 5 x lO I4 c W 3 , and VFB= - 1 . 4 V . Th eo depict results obtain using a two-dimensional numerical simulator [131.

compare favorably with the results obtained from exper-imental measurements. Fig . 7 illustrates the channel po-tential for each of the BC-MOSFET's. The channel po-tential at a depth of 0.625 pm is plotted from the sourcediffusion to the drain diffusion. This corresponds to thepoint of maximum vertical channel potential in the sim-ulated device. For each device, V D D - Vss s varied from1 V through to 5 V. It is evident from these potential dis-tributions that the D IBL effects are present even for mod-erate channel lengths (3 pm ).


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VAN DER TOL AND CHAM BERLAIN: DRAIN-INDUCED BARRIER LOWERING

Channel Potential ( V ) Channel Potential (V 1141

ow OM 103 150 zo o 250 3 0 3 350 4 w 4 50 (w 55 0 61x1Distance along Channel ( pm)(a )Channel Potentlal ( V )

ow nso I W 15 0 2 m 2s o 100Distance along Channel ( @m

(d )Fig. 7. (a) Two-dimensional s imulat ions of the BC-MOSFET channel potent ial ( L = 6 pm). The potential distribution fromthe source to the drain at a depth of 0.625 pm is given for drain biases of V D D- Vs s = 1.0, 2 . 0 , 3.0, 4.0, an d 5.0 V . The gateand bulk biases are held at VGG = -4.0 V an d Vss = 0. 0 V , respect ively. (b) Two-dimensional s im ulat ions of the BC-MOS FETchannel potential (L = 5 pm). The potential distribution from the source to the drain at a depth of 0.625 pm is given for drainbiases of V D ~ V,, = 1.0, 2.0, 3.0, 4.0, an d 5. 0 V . The gate and bulk biases are held at VG G= -4.0 V and VBB = 0. 0 V ,respectively. (c ) Two-dimensional s imulat ions of the BC-MOSFET channel potent ial ( L = 4 pm). The potential distributionfrom the so urce to the drain at a depth of 0.625 pm is given for drain biases of VD D- Vs s = 1.0. 2.0, 3.0, 4.0, an d 5. 0 V .The gate and bulk biases are held at VG G= -4 .0 V an d V E B= 0.0 V , respectively. ( d) Two-dime nsional simulations of theBC-MOSFET channel potent ial ( L = 3 pm). The potential distribution from the source to the drain at a depth of 0.625 pm isgiven for drain biases of VoD - Vss = 1.0, 2.0 , 3 .0 , 4.0, an d 5.0 V . The gate and bulk biases are held at VG G= -4.0 V andVBB= 0. 0 V , respect ively.


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748 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. NO . 4. APRIL 1993

T A B L E IllS U M M A R YF S U B T H R E S H O L DO D E L A R A M E T E R SOR V D s= 2 .0 VL (Fm) t r VTH (V)

3 14.04 6 .6 2 -10.0 ( -10 .8 )4 3 .65 7 .72 -5 .0 ( -5 .55)5 2 .78 11 .68 -4 .3 ( -4 .67)6 2 .39 17 .76 -4 .0 ( -4 .36)N, , = 2 .0 X IO2 N D = 2 .13 X 10l6

phll = 1179

TABLE IV7 A N D { FROM S I M U L A T I O N SOR VD s = 2 .0 V

3 12 .33 5 .814 2 .40 5 .085 1.89 7.926 1.79 13.37

V . CONCLUSIONIn this paper we have clarified the relationship between

the threshold voltage shift and channel length reductionfor BC-MOSFETs. Using experimental measurementswe demonstrated the relationship between the thresholdvoltage and channel length reduction for normally-on BC -MOSFETs. These results were compared with similarmeasurements on surface-channel MOSFETs. From theexperimental evidence presented it is clear that normally-on (inverting) BC-MOSFETs are more prone to drain-induced barrier lowering. In addition, we analyzed thesubthreshold current as a function of channel length. Wederived an analytic model to describe the subthresholdcurrent and compared the results with experimental mea-surements and the subthreshold currents obtained usingtwo-dimensional num erical simulations. The analyticmodel for the subthreshold current in BC-MOSFETscompares favorably with our experimental m easurementsand the two-dimensional simulations.

ACKNOWLEDGMENTA G PX I1 computer given to us through the UW-DECagreement was used. Computing provided to us by ICRof Waterloo and partial support from ITRC is gratefullyappreciated. A special thanks is extended to DALS A Inc. ,CCD IMA GE S ENSORS, Water loo , On t. , for supply ingthe test devices and device fabrication details for this re-search.

RE FE RE NCE S[ I ] D. B. Scott and S . G. Chamberlain, A cal ibrated model for thesubthreshold operat ion of a short channel MOS FET including surfacestates , IEEE J. Solid-State Circuits, vol. S C - 1 4 , no. 3, pp. 633-644, June 1979.[2 ] S . G . Chamberlain and S . Ramanan , Drain - induced bamer- lower-ing analysis in VLSI MOSFET devices using two-dimensional nu-merical s imulat ions, IEEE Trans. Electron Devices, vol . ED-33,pp. 1745-1753, NOV. 1986.

[3] R. R. Troutm an, V LSI l imitat ions from drain-induced barrier low-er ing , IEEE Trans. Electron Devices, vol . ED-26, pp. 461-469,Apr. 1979.[4 ] K . Nishiuchi , H. Oka, T . Nakamura, H. Ishikawa, and M. Shinoda,A normally-off type buried channel MOSFET for VLSI circui ts ,in IEDM Tech. Dig., Dec. 1978, pp. 26-29.[SI S . M. Sze , Physics of Semiconductor Devices, 2nd ed. New York:Wi ley , 1981 .[6] M. Wordeman and R. Dennard, Threshold vol tage characteris t icsof dep le tion-mode MOS FETs , IEEE Trans. Electron Devic es, vol .ED-28, no. 9, pp. 1025-1030, Sept . 1981.[7] N. Ballay and B. Baylac, Analytical modeling of depletion modeMOSFET with short and narrow channel effects , Proc. Inst. Elec.Eng . , vol . 128, pp. 225-237, De c. 1981.[8 ] G. J . Hu and R. H. Bruce, D esign tradeoffs between surface andburied-channel FETs, IEEE Trans. Electron Devices, vol. ED-32,pp. 584-588, M ar. 1985.[9] T. Skotnicki and T. Pedron, Anom alous punchthrough in ULSI bur-ied-channel MOSFETs, IEEE Trans. Electron Devices, vo l . 36 ,no . 1 1, pp. 2548-2556, Nov. 1989.IO ] T. Grotjohn and B . Hoefflinger, A parametric short-channel MOSt ransis tor model for subthreshold and strong inversion current , IEEE

J. Solid-State Circuits, vol . SC-19, pp . 100-112 , Feb . 1984 .1I] T. E . Hendrickson, A simplified model for subpinchoff conductionin depletion-more IGFET s, IEEE Trans. Electron Devices, vol. ED -25, pp. 435-441, Apr. 1978.121 M. J. Van der To1 and S . G . Chamberlain, Potent ial and electrondistribut ion model for the buried-channel MOSFET, IEEE Trans.Electron Devices, vo l . 36 , no . 4 , pp . 670-689 , Apr . 1989 .[ I31 J . R. F . McMacken and S . G. Chamber l a in , CHORD: A modularsemiconductor device s imulat ion development tool incorporat ing ex-ternal network mo dels , IEEE Trans. Computed-Aided De s. , vo l . 6 ,no. 8, pp. 826-836, Aug. 1989.

Michael J . Van der To1 was born in Winnipeg,Man., Canada. He received the B.Sc. and M.Sc.degrees in electncal enginee ring from the Univer-si ty of Ma nitoba, Winnipeg, in 1981 and 198 3,respect ively, and the Ph.D. degree in electricalenginee nng from the Universi ty of Waterloo, Wa-terloo, Ont ., Canada, in 1990.From January 1984 to July 1986, he worked atBell-Northern Research Ltd., Ottawa, Ont ., Can-ada , on CAD tool development From January1990 through August 1991, he was em ployed atQuantic Laboratories , W innipeg, where he worked on CAD a nalysis tookIn September 19 91, he rejoined Bell-Northern Research at Ottaw a, He IScurrently working on ECA D analysis tools for P C P / M C M .

Savvas G . Chamberlain (M70-SM77-F90)received the first degree in electronics fromNorthern Polytechnic, London, England, in 1964,and the M.Sc. and Ph.D. degrees from Southamp-ton Universi ty, Southampton, England, in 1965and 1968, respect ively.He then joined the Allen Clark Research Centre,The Plessey Company Ltd., Caswell , England,where he contributed in pioneering the technologywhich led to the design and manufacture of MOS-FET self-scanned optical image sensor devices. In1969, he joined the Department of Electrical Engin eerin g, University ofWaterloo, Ont ., Canada, where he is present ly a Full Professor. BetweenSeptember 1982 and September 1986, he was Professor and AssociateChairman for Graduate Studies. H e also served fo r a short t ime as the Act-ing Chairman for this department . Pre sent ly, he is the recipient of the NC RMicroelectronics Fellowship. His research at the University included thedevelopment of MOSFET, CMOS, and CCD technology. His research re-sul ts have found their was as original contribut ions to textbooks on fun-damental theory of CCD image sensors , sol id-state photodetectors , and


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VAN DER TOL AN D CHAMBERLAIN: DRAIN- INDUC ED BARRIER LOWERING 149

MOSFET devices. He has supervised and trained many P h.D . and M.A.Sc.students . H e was also one of the principal contributors to the creat ion,development, and running of the Silicon Devices and Integrated CircuitsMicroelectronics Fabrication Laboratory at the University of Waterloo. In1971, on leave from the U niversi ty, he was with Bell-Northern Research,Ottawa, Ont ., where he was one of the principal researchers and a contrib-utor to the development of the BNR Charge-Coupled Device Design andFabrication Technology. From September 1974 to September 1975, andagain from August 1981 to September 1982, he was a Visiting Scientist atthe IBM Thomas 1. Watson Research Center, Yorktown Heights , NY,where he worked on CC D image sensors , sol id-state imaging arrays, mod-el ing of MOSFET devices, and MOSF ET integrated circui ts . In 1980, hefounded DALSA Inc., CCD Image Sensors , in Waterloo, Ont ., where heintroduced an Advanced CC D Image S ensor Technology. He has published

more than 100 papers in scientific refereed journals and has more than 15patents and patents pending on CCDs, integrated circuits, optical imagingdevices, and solid-state scanners.Dr. Chamberlain was elected Fel low of the IEEE in 1990 for Contri-but ions in CCD Imagers and MOS FETs. He also contributed to the ini-tial establishment and growth of the IEEE Custom Integrated Circuits Con-ference. H e served as the Program Technical C hairman and later ConferenceChairman and General Chairman of this conference. Fu rther, he served atvarious t imes as an Associate Editor and as Guest Editor of the IEEE JO UR-N A L OF SOLID-STATEIRCUITSnd IEEE TRANSACTIONSN E L E C T R O NE-V ICES. His other technical activities include: chairman of the NSERC op-erating research grants com mittee , involvement with the Federal Ne tworkof Center of Excellence in Microelectronics and the Information Tech nol-ogy Research Center of the Ontario Center of Excel lence.

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