E R3958 Pages: 2

Page 1 of 2

Reg No.:_______________ Name:__________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

THIRD SEMESTER B.TECH DEGREE EXAMINATION, DECEMBER 2018

Course Code: EC207

Course Name: LOGIC CIRCUIT DESIGN (EC, AE)

Max. Marks: 100 Duration: 3 Hours

PART A Answer any two full questions, each carries 15 marks. Marks

1 a) Convert the following

(i) (AB6)16 to Decimal (iii) (543.26)10 into Octal

(ii) (247.36)8 into Hexa Decimal (iv) (AF9.B0D)16 into

Binary

( 8)

b) Consider the signed binary numbers A = 01000110 and B = 11010011 where B is in 2’s complement form. Find the value of the following mathematical expression (i) A + B

(ii) A - B

(iii) B - A

(7 )

2 a) Hamming code was used to generate parity for a nibble. If received bit sequence

is 0101010 then write correct bit sequence with (i) Even parity (ii) Odd parity

(8)

b) Explain the operation of a 8x1 multiplexer and implement the following using

an 8x1 multiplexer

F(A, B, C, D) = ∑ m (0, 1, 3, 5, 6, 7, 8, 9, 11, 13, 14)

(7)

3 a) Minimize the following logic function using K- maps and realize using NAND

gates alone

F(A, B, C, D) = ∑ m (0, 3, 5, 8, 9, 11,15) + d (2, 3)

(10)

b) Design a magnitude comparator to compare two 2-bit numbers A = A1A0 and

B = B1B0

(5)

PART B Answer any two full questions, each carries 15 marks.

4 a) Draw the circuit and explain the operation of TTL NAND gate (10)

b) Compare TTL, CMOS logic families in terms of fan-in, fan-out, supply voltage,

propagation delay, power dissipation and noise margin

( 5)

5 a) Implement the following function using PLA

F1(x, y, z) = ∑ m ( 1, 2, 4, 6 )

F2(x, y, z) = ∑ m (0, 1 , 6, 7)

(8)

E R3958 Pages: 2

Page 2 of 2

b) Explain a MOD 6 asynchronous counter using J K Flip Flop (7)

6 a) Design a 3-bit synchronous counter using D Flip Flop (10)

b) Convert SR Flip Flop into J K Flip Flop (5)

PART C Answer any two full questions, each carries20 marks.

7 a) Draw the logic diagram of 3 bit PIPO shift register with LOAD/SHIFT control and explain its working.

(10)

b) Explain Moore and Mealy machine models. Compare the models (10)

8 a) Draw the logic diagram of 3 –bit Johnson counter and explain the working with

truth table.

(10)

b) For the given state diagram, design a sequential circuit with D flip flops

(i) Construct the state table.

(ii) Obtain the simplified input equations for all input flip flops and the

simplified equation for the output.

(10)

9 a) Minimize the state table using implication chart.

(10)

b) Design a 101 sequence detector ,for overlapping case, using D Flip Flop (10)

****

Dept o

f ECE,

SCMS C

ochin

E B3E011S Pages: 3

Page 1 of 3

Reg. No._______________ Name:______________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

THIRD SEMESTER B.TECH DEGREE EXAMINATION, JULY 2017

Course Code: EC 207

Course Name: LOGIC CIRCUIT DESIGN (AE, EC)

Max. Marks: 100 Duration: 3 Hours

PART A

Answer two questions, Question no. 3 is compulsory.

1. a) Convert the first twelve integers into Binary, Grey and BCD. (4)

b) Perform the following operations [show the intermediate steps]. (6)

i) 5743)8 – 3672)8

ii) CFD4)16 – 6A51)16

iii) 56)10 – 48)10 using 2’s and 1’s complement method

iv) 316.645)10 into Binary, Octal and Hexadecimal

c) What is Hamming code? How is the Hamming code word tested and corrected.

Encode the data bits “1101” into the 7-bit even parity Hamming code. (5)

2. a) Show how four single bit full adders can be combined to implement a four bit

ripple carry adder. Design and realize a four bit adder/subtract circuit using the four

bit adder block and logic gates. The add/�������������������� function can be selected by using

a control signal. Justify your answer with at least one example from each category.

(5)

b) For the Boolean function � = ��. ��. �� + �. ��. �� + ��. �. � + �. �. �� + ��. �. �.

Show how it can be implemented using i) One 16:1 multiplexer ii) One 8:1

multiplexer and one or more NOT gates. (10)

3. a) In a computer system, numbers are represented using words with a length of 4 bits.

(i) What is the range of positive numbers that can be represented using unsigned binary numbers? (ii) Explain how the 1’s and 2’s complement representation can be used to describe signed binary numbers. (iii) Prepare a table showing all the positive and negative numbers which can be represented using 4 bit words in “sign magnitude”, “1’s complement” and “2’s complement” representation and mark the maximum and minimum in each case. (8) b) Design and realize a 8:3 priority encoder. (7)

PART B

Answer two questions, Question no. 6 is compulsory.

4. a) Define the terms noise margin, voltage and current levels, propagation delay, fan

out and power dissipation related to a logic families. Prepare a comparison table

showing the values of each for the TTL, ECL and CMOS logic families. (6)

Dept o

f ECE,

SCMS C

ochin

E B3E011S Pages: 3

Page 2 of 3

b) Draw the circuit diagram of a transistor level TTL NAND gate and explain the

working. (5)

c) What is PLDs?. Differentiate between PAL and PLA. (4)

5. a) Realize a JK flip flop with NAND gates and describe its operation with detailed

truth table, characteristic equation and excitation table. Describe the race around

problem and suggest the methods to eliminate. (5)

b) A self starting synchronous binary up-counter having the state sequence 1; 2; 3; 4;

5; 6; 1; 2; : : : is to be implemented using T-flip flops. The flip flop outputs are

designated as Q2, Q1 and Q0, where Q0 represents the least significant digit of the

count. Give simplified expressions for the required next-state logic and the complete

circuit diagram. (10)

6. a) Draw the circuit diagram of a transistor level CMOS NOR gate and explain the

working with a truth table. (4)

b) Differentiate between the totem pole, open collector and tri-state logic related to

the TTL logic circuit. (3)

c) Describe the procedure for converting one type of flip flop in to another. Perform

the following conversions. (8)

i) T to JK ii) T to D

PART C

Answer two questions, Question no. 9 is compulsory.

7. a) Draw the logic diagram of a four bit Johnson counter and explain the working with

truth table and timing diagram. (10)

b) Obtain the state table, transition table and D flip flop excitation table for the state

diagram shown in figure. (10)

8. Draw the state diagram, state table, transition table, excitation table for the Mealy

clocked synchronous sequential system (modulo-4 up/down counter). Design and

realize it with minimum number of T-flip flops. The system has two control inputs

Dept o

f ECE,

SCMS C

ochin

E B3E011S Pages: 3

Page 3 of 3

and two outputs: input (mode) M is set at logic “0" to cause the counter to count up,

and at logic “1" to cause the counter to count down; input (enable) E is set at logic “1"

to enable the counter to count and at logic “0" to cause the counter to hold its current

state. The outputs “Y,Z” become “00”, “01”, “10”,and “11” in count up direction

and output “Y,Z” become “11”, “10”, “01”,and “00” in countdown direction against

the clock starting from the first state. (20)

9. a) Draw the logic diagram of a four bit, bi-directional serial in serial out (SISO) shift

register with mode control and explain the working with timing diagram.

(10)

b) Reduce the state table and identify the redundant states. (10)

Present state

Next state Output (Z) X=0 X=1 X=0 X=1

S0 S1 S2 0 0 S1 S3 S4 0 0 S2 S5 S6 0 0 S3 S7 S8 0 0 S4 S9 S10 0 0 S5 S11 S12 0 0 S6 S13 S14 0 0 S7 S0 S0 0 0 S8 S0 S0 0 0 S9 S0 S0 0 0 S10 S0 S0 1 0 S11 S0 S0 0 0 S12 S0 S0 1 0 S13 S0 S0 0 0 S14 S0 S0 0 0

****

Dept o

f ECE,

SCMS C

ochin

E E7253

Page 1 of 2

Total Pages: 2 Reg No.:_______________ Name:__________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY THIRD SEMESTER B.TECH DEGREE EXAMINATION, DECEMBER 2017

Course Code: EC207

Course Name: LOGIC CIRCUIT DESIGN (EC, AE)

Max. Marks: 100 Duration: 3 Hours PART A

Answer any two full questions, each carries 15 marks. Marks

1 a) Convert 326.87510 to binary, and Hex form. (3) b) Represent 47810 in BCD and Excess-3 codes. (3) c) Perform the arithmetic operation on these unsigned binary numbers. Show

intermediate steps. i) 10110.101+101.11 (ii) 100001-1011

(4)

d) Simplify using K-map F(a,b,c,d) = ∑m (4,5,7,8,9,11,12,13,15)

(5)

2 a) A function is defined as F(a,b,c,d) = a’b+a’c+c’+a’d+a’b’c’+a’bc’ i) Express the function in standard SOP (canonical) form. ii) Implement the function using single 8:1 MUX. iii) Simplify the function using K-map and implement the result using NAND gates only.

(10)

b) Design a logic circuit that produces a HIGH output whenever a 3-bit binary number A2A1A0 greater than 001 and less than 110 is applied as input (A2 is MSB).

(5)

3 a) A computer system uses 12 bits. What is the counting range of values, in decimal form, if the 12 bits are used to represent i) unsigned numbers only (ii) 2’s complement system (iii) 1’s complement system.

(5)

b) Perform arithmetic operation on the given decimal numbers using 2’s complement system. Use 8 bits for each number including sign bit. Express the result in binary form. : 15 - 4

(4)

c) Design the circuit of a 3-line to 8-line decoder using basic gates. (6)

PART B Answer any two full questions, each carries 15 marks.

4 a) Draw the circuit diagram of a standard 2 input CMOS NOR gate with 5V supply voltage. How does it work as a NOR gate. Write its truth table.

(5)

b) What are noise immunity and noise margin? Indicate the logic levels of the 5V CMOS and TTL gates.

(5)

c) What is open-collector output gate? State its use. What is tri-state logic? State its use.

(5)

5 a) Design the circuit of a mod-12 asynchronous up counter using JK flip-flop that starts counting at 0. Draw its output waveforms and indicate the sequence. Design an additional circuit to light an LED when the count is maximum.

(10)

b) Consider a 5 bit asynchronousup counter using JK flip-flop. Find its modulus. What is the lowest output frequency, if the input clock frequency is 160 kHz? What is the counting range?

(5)

6 a) Design a 3-bit synchronous up counter using T Flip-flop with outputs Q2Q1Q0

where Q0 is LSB. Write the complete truth table and excitation table. Derive the expression of T2, T1, T0 in terms of Q2 ,Q1, Q0. Draw the circuit diagram.

(10)

b) What is PLA?Showhowf1= a’bc+ab’+abc’, f2= a’b’c’+ac and f3= ab’c+ab can be (5)

Dept o

f ECE,

SCMS C

ochin

E E7253

Page 2 of 2

implemented in PLA. PART C

Answer any two full questions, each carries 20 marks. 7 a) Draw the state diagrams of JK flip-flop. Write its state table. (5) b) Design the logic circuit using JK flip-flop for the given state table where x is the

input. Draw the state diagram, transition table, JK flip-flop excitation table, logic diagrams.

Present state Next state Output x=0 x=1 x=0 x=1

A B A 0 0 B B C 0 0 C D A 0 1 D B C 0 1

(15)

8 a) Find the equivalent states and reduce the given state table using implication chart. x is the input

Present state Next state Output x=0 x=1 x=0 x=1

a e c 0 0 b c a 0 0 c b g 0 0 d g a 0 0 e f b 1 0 f e d 0 0 g d g 0 0

(10)

b) Design a 3-bit up/down synchronous counter using JK Flip-flop that counts up when the control input M=1 and counts down when M=0. Assume that JK flip-flop inputs are J2K2, J1 K1 ,J0 K0 and the corresponding outputs are Q2 Q1 Q0 respectively where Q0 is LSB. Draw its State table, Excitation Table and Logic diagram

(10)

9 a) A logic circuit is designed using the following modules. First module is a 3-bit ring counter. A clock signal of 480 kHz is applied at the clock input of this module. The output from its last FF is M. This output is connected to the clock input of the next stage which is a mod-4 ripple counter. The output from its last flip-flop is N. This output is connected to the clock input of the 2-bit Johnsons counter. The output P of its last Flip-flop is applied to the clock input of an edge triggered D flip-flop. The Q’ of the D flip-flop is connected to the D input. Find the frequency of the output signals at M, N, P and Q. Justify your answer. What is the overall modulus?

(10)

b) Design a 4-bit bi-directional shift register circuit using D flip-flops with shift control input M that shifts right when M=1 and shifts left when M=0. State how it works with examples.

(10)

****

P

Q

480

kHz

Clock

M N

3 bit Ring

Counter

Mod-4 Ripple

Counter

2 bit

Johnsons

Counter

D Q’

>CLK

Dept o

f ECE,

SCMS C

ochin

E B3E012 Total Pages:3

Page 1 of 3

Reg. No._____________ Name:________________________

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

THIRD SEMESTER B.TECH DEGREE EXAMINATION, JANUARY 2017

Course Code: EC 207

Course Name: LOGIC CIRCUIT DESIGN (AE, EC)

Max. Marks: 100 Duration: 3 Hours

PART A (2x15=30)

(Answer two questions, Question no. 3 is compulsory)

1. a) Prepare a table for the first 12 integers in Binary, Grey, Excess 3 and ASCII. (4)

b) Perform the following operations [showing the intermediate steps]. (6)

i) 110002 – 101112 using 1’s and 2’s complement method

ii) 74618 + 71578

iii) DC5A16 – 9B3C16

iv) 11001001101.10110112 into Decimal, Octal and Hexadecimal

c) What is Hamming code? How is the Hamming code word generated? The message

“1001001” is coded in the 7-bit even parity Hamming code, which is transmitted

through a noisy channel. Decode the message, assuming that at most a single error

occurred in each code word. (5)

2. a) A four variable Boolean function is given as � = �. �. � + �. ��. � + �. �. �

where �. �. ��. �� + �. ��. �. � + ��. ��. �. � are don’t cares. Use Karnaugh map to

find the minimal SOP expression for F. Design and realize the function F i) using

NAND gates only and ii) using NOR gates only. (8)

b) Design and realize a combinational circuit to compare two 3 bit numbers A

(A2A1A0) and B (B2B1B0) as inputs and “AGT”(A>B), “AEQ”(A=B) and

“ALT”(A<B) are the outputs.[Use algorithmic approach]. (7)

3. a) Perform each of the following conversions [show the intermediate steps]. (8)

(i) 160.6710 into Hexadecimal (ii) A63.B516 into Decimal

(ii) ABBA into ASCII (iv) 1210 into BCD

(iii) 83510 into ASCII (vii) 28.310 into Ternary(Radix 3)

(iv) 241.325 into Decimal (viii) -8510 into 2’s complement

Dept o

f ECE,

SCMS C

ochin

E B3E012 Total Pages:3

Page 2 of 3

b) Draw the gate level circuit diagram and logic equations for a 1 to 4 de-multiplexer.

For the Boolean function F = (� + �). (� + �). (� + �). Show how it can be

implemented using a 1: 8 de-multiplexer and one or more gates. (7)

PART B (2x15=30)

(Answer two questions, Question no. 6 is compulsory)

4. a) Draw the circuit diagram of a transistor level CMOS NAND gate and explain the

working with a truth table. (5)

b) Define the terms noise margin, voltage and current levels, propagation delay, fan

out and power dissipation related to a logic families. Prepare a comparison table

showing the values of each for the TTL, ECL and CMOS logic families. (6)

c) What is PLDs? Differentiate between PAL and PLA. (4)

5. a) Show how four 2-input NAND gates can be connected together to implement a

clocked SR latch. Describe its operation with its detailed truth table; also derive its

characteristic equation and excitation table.

b) An up/down binary counter is required. There is one control input (M) and a clock

(CLK). The outputs are to be labelled Q0, Q1 and Q2. If M=1 then the counter counts

up every clock period, if M=0 it counts down. Realize this counter in terms of AND,

OR and XOR gates, and T flip flops. Provide equations for the inputs to the flip flops

and a circuit diagram of the complete system.

6. a) Draw the circuit diagram of a transistor level TTL NOT gate and explain the

working with a truth table. (4)

b) Draw a circuit to control an LED via a TTL inverter for the following conditions:

When the input to the inverter is 1, the LED should illuminate and the ON current

should not exceed 15 mA, at which point the voltage drop across the LED will be

1.5V. Find the resistor values and justify your answer with sourcing and sinking mode

of operation. (3)

c) Design a circuit to obtain the sequence 2; 4; 3; 6; 2; 4; : : : using JK flip flops. (8)

PART C (2x20=40)

(Answer two questions, Question no. 9 is compulsory)

7. a) Draw the logic diagram of a four bit, parallel in serial out (PISO) shift register with

LOAD/�������������� control and explain its working. (10)

b) Draw the state diagram, transition table, D flip flop excitation table and state

equation for the given state table. (10)

Dept o

f ECE,

SCMS C

ochin

E B3E012 Total Pages:3

Page 3 of 3

Present

state

Next state Output (Z)

X=0 X=1 X=0 X=1

A (00) A B 0 0

B (01) C B 0 0

C (10) A D 0 0

D (11) C B 1 0

8. A serial data line carries binary data to a system with input X. The system is required

to detect a sequence 0 1 0 in the data and give an output Y = 1 at the end of the

sequence. Only non-overlapping sequences should be detected in the data. For

example, the output y should only be 1 for the 0 underlined in the input sequence : : :

1 0 1 0 1 0 1 0 : : :.

Draw the state diagram, state table, transition table, excitation table for the Mealy

clocked synchronous sequential system and realize it with minimum number of D-flip

flops after state reduction, if possible. (20)

9. a) Draw the logic diagram of a four bit ring counter and explain the working with

truth table and timing diagram. (10)

b) Minimize the state table using implication chart. The state machine is having nine

states, one input and two output variables. Re-assign the simplified state variables as

A, B, C, D and E. (10)

Present state

Next state Output (Z1Z2) X=0 X=1 X=0 X=1

0 0 1 00 00 1 4 2 00 00 2 7 1 00 00 3 2 6 01 10 4 6 5 10 00 5 3 4 01 11 6 1 6 01 10 7 3 8 10 00 8 8 7 01 11