ECE 15B Computer OrganizationSpring 2011

Dmitri Strukov

Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy,

ECE 15B Spring 2011

Agenda

• Instruction formats• Addressing modes• Advanced concepts

ECE 15B Spring 2011

Instruction formats

Simple datapath picture

Let’s add more details on this figure to see why instruction decoding could be simple and to see what is happening with for different instructions ECE 15B Spring 2011

Below the Program

lw $t0, 0($2)lw $t1, 4($2)sw $t1, 0($2)sw $t0, 4($2)

High Level Language Program (e.g., C)

Assembly Language Program (e.g.,MIPS)

Machine Language Program (MIPS)

Hardware Architecture Description (e.g., block diagrams)

Compiler

Assembler

Machine Interpretation

temp = v[k];v[k] = v[k+1];v[k+1] = temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

Logic Circuit Description(Circuit Schematic Diagrams)

Architecture Implementation

ECE 15B Spring 2011

Assembly instruction

0000 1001 1100 0110 1010 1111 0101 1000

Binary code

lw $t0, 0($2)

always 32 bitsOne assembly instruction = 32 bit vector

Macro or pseudo instruction > one line of codeExamples: shift and rotate from Quiz 1rol $a0, $a1, $a2 subu $t0, $0, $a2

srlv $t0, $a1, $t0sllv $a0, $a1, $a2or $a0, $a0, $t0

One to one mapping

Datapath With Control

ECE 15B Spring 2011

ECE 15B Spring 2011

Instruction formats

op rs rt rd shamt funct

6 bits 6 bits5 bits 5 bits 5 bits 5 bits

R-format:

op rs rt constant or address6 bits 5 bits 5 bits 16 bits

op address6 bits 26 bits

I-format:

J-format:

R-format Example

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

op rs rt rd shamt funct6 bits 6 bits5 bits 5 bits 5 bits 5 bits

note the order!(green card)

ECE 15B Spring 2011

R-Type Instruction

ECE 15B Spring 2011

ECE 15B Spring 2011

Instruction formats

op rs rt rd shamt funct

6 bits 6 bits5 bits 5 bits 5 bits 5 bits

R-format:

op rs rt constant or address6 bits 5 bits 5 bits 16 bits

op address6 bits 26 bits

I-format:

J-format:

Load Instruction

ECE 15B Spring 2011

ECE 15B Spring 2011

Instruction formats

op rs rt rd shamt funct

6 bits 6 bits5 bits 5 bits 5 bits 5 bits

R-format:

op rs rt constant or address6 bits 5 bits 5 bits 16 bits

op address6 bits 26 bits

I-format:

J-format:

Target Addressing Example• Loop code from earlier example

– Assume Loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32

lw $t0, 0($t1) 80008 35 9 8 0

bne $t0, $s5, Exit 80012 5 8 21 2

addi $s3, $s3, 1 80016 8 19 19 1

j Loop 80020 2 20000

Exit: … 80024

ECE 15B Spring 2011

Branch-on-Equal Instruction

ECE 15B Spring 2011

MIPS PC-relative or branch addressing

• Branch instructions specify– Opcode, two registers, target address

• Most branch targets are near branch– Forward or backward

op rs rt constant or address6 bits 5 bits 5 bits 16 bits

PC-relative addressing Target address = PC + offset × 4 PC already incremented by 4 by this time

ECE 15B Spring 2011

ECE 15B Spring 2011

Instruction formats

op rs rt rd shamt funct

6 bits 6 bits5 bits 5 bits 5 bits 5 bits

R-format:

op rs rt constant or address6 bits 5 bits 5 bits 16 bits

op address6 bits 26 bits

I-format:

J-format:

Target Addressing Example• Loop code from earlier example

– Assume Loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32

lw $t0, 0($t1) 80008 35 9 8 0

bne $t0, $s5, Exit 80012 5 8 21 2

addi $s3, $s3, 1 80016 8 19 19 1

j Loop 80020 2 20000

Exit: … 80024

ECE 15B Spring 2011

Datapath With Jumps Added

ECE 15B Spring 2011

Pseudodirect or Jump Addressing• Jump (j and jal) targets could be anywhere

in text segment– Encode full address in instruction

op address6 bits 26 bits

(Pseudo)Direct jump addressing Target address = PC31…28 : (address × 4)

ECE 15B Spring 2011

Implementing Jumps

• Jump uses word address• Update PC with concatenation of

– Top 4 bits of old PC– 26-bit jump address– 00

• Need an extra control signal decoded from opcode

2 address

31:26 25:0

Jump

ECE 15B Spring 2011

Branching Far Away

• If branch target is too far to encode with 16-bit offset, assembler rewrites the code

• Examplebeq $s0,$s1, L1

↓bne $s0,$s1, L2j L1

L2: …

ECE 15B Spring 2011

ECE 15B Spring 2011

Note on the PC incrementing

• Technical term for auto-incrementation of PC is “delayed branch”

• By default in SPIM “delayed branch” is not checked. To see you SPIM settings look at simulator settings

• You can also check it by loading code to SPIM to check

main : bne $s0, $s0, main

ECE 15B Spring 2011

Loading constant values to registers

• Any immediate is 16 bit• To load 32 bits constant one can use addi, sll +

addi or better way to use lui rd, const (load upper immediate)

Specific Addressing Mode in MIPS

ECE 15B Spring 2011

ECE 15B Spring 2011

Various specific addressing modes in other ISAs

• Absolute address• Immediate data• Inherent address• Register direct• Register indirect• Base register• Register indirect with index register• Register indirect with index register and displacement• Register indirect with index register scaled• Absolute address with index register• Memory indirect• Program counter relative

Example: Basic x86 Addressing Modes

• Two operands per instructionSource/dest operand Second source operand

Register Register

Register Immediate

Register Memory

Memory Register

Memory Immediate

Memory addressing modes Address in register Address = Rbase + displacement Address = Rbase + 2scale × Rindex (scale = 0, 1, 2, or 3) Address = Rbase + 2scale × Rindex + displacement

ECE 15B Spring 2011

ECE 15B Spring 2011

Advanced Topics:Code density examples

ECE 15B Spring 2011

Recent study (2009)

ECE 15B Spring 2011

Code density examples

ECE 15B Spring 2011

Advanced topics: Pipelining

Datapath With Control

ECE 15B Spring 2011

Pipelining Analogy• Pipelined laundry: overlapping execution

– Parallelism improves performance

Four loads: Speedup

= 8/3.5 = 2.3 Non-stop:

Speedup= 2n/0.5n + 1.5 ≈ 4= number of stages

ECE 15B Spring 2011

Pipeline registers• Need registers between stages

– To hold information produced in previous cycle

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Multi-Cycle Pipeline Diagram• Traditional form

ECE 15B Spring 2011

ECE 15B Spring 2011

Advanced topics: Cache design basics

Datapath With Control

ECE 15B Spring 2011

Principle of Locality

• Programs access a small proportion of their address space at any time

• Temporal locality– Items accessed recently are likely to be accessed again

soon– e.g., instructions in a loop, induction variables

• Spatial locality– Items near those accessed recently are likely to be

accessed soon– E.g., sequential instruction access, array data

ECE 15B Spring 2011

Taking Advantage of Locality

• Memory hierarchy• Store everything on disk• Copy recently accessed (and nearby) items

from disk to smaller DRAM memory– Main memory

• Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory– Cache memory attached to CPU

ECE 15B Spring 2011

Direct Mapped Cache• Location determined by address• Direct mapped: only one choice

– (Block address) modulo (#Blocks in cache)

#Blocks is a power of 2

Use low-order address bits

ECE 15B Spring 2011

Tags and Valid Bits

• How do we know which particular block is stored in a cache location?– Store block address as well as the data– Actually, only need the high-order bits– Called the tag

• What if there is no data in a location?– Valid bit: 1 = present, 0 = not present– Initially 0

ECE 15B Spring 2011

Example: Direct mapped cache

ECE 15B Spring 2011