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ECE 44 8 – FPGA and ASIC Design with VHDL

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ECE 448: Lab 1 Review of Aldec Active HDL Implementing Combinational Logic in VHDL. ECE 44 8 – FPGA and ASIC Design with VHDL. George Mason University. Part 1. Introduction to Aldec Active-HDL. Example: MLU. MLU Block Diagram. MUX_0. 0 1. 0 1. 0 1. A1. A. MUX_4_1. Y1. IN0. - PowerPoint PPT Presentation
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ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448: Lab 1 Review of Aldec Active HDL Implementing Combinational Logic in VHDL
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Page 1: ECE 44 8 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL George Mason University

ECE 448: Lab 1

Review of Aldec Active HDL

Implementing Combinational Logic in VHDL

Page 2: ECE 44 8 – FPGA and ASIC Design with VHDL

Example: MLU

Part 1

Introduction to Aldec Active-HDL

Page 3: ECE 44 8 – FPGA and ASIC Design with VHDL

MLU Block Diagram

B

A

NEG_A

NEG_B

IN0

IN1

IN2

IN3

OUTPUT

SEL1SEL0

MUX_4_1

L0L1

NEG_Y

Y

Y1

A1

B1

MUX_0

MUX_1

MUX_2

MUX_3

0

1

0

1

0

1

Page 4: ECE 44 8 – FPGA and ASIC Design with VHDL

Experiment 1Problem 1

ALU of PicoBlaze

http://teal.gmu.edu/courses/ECE448/experiments_S06/448_exp1.htm
http://teal.gmu.edu/courses/ECE448/experiments_S06/448_exp1.htm
http://teal.gmu.edu/courses/ECE448/experiments_S06/448_exp1.htm
Page 5: ECE 44 8 – FPGA and ASIC Design with VHDL

PicoBlaze Overview

Page 6: ECE 44 8 – FPGA and ASIC Design with VHDL

Register File of PicoBlaze0

1

7

7

7

0

0

0

Address

7 0

7 0

7 0

7 0

7 0

16 Registers

8-bit

7 0F

s0s1s2s3s4s5s6s7

234567

sF

Page 7: ECE 44 8 – FPGA and ASIC Design with VHDL

Condition Code Registers (Flags) and its Definition

Z = 1 if result = 0 0 otherwise

Zero flag - Z zero condition

Example*C = 1 if result > 28-1 or result < 0 0 otherwise*Applies only to addition or subtraction related instructions, refer to following slides otherwise

Carry flag - C overflow, underflow, or various conditions

Flags are set or reset after ALU operations

Page 8: ECE 44 8 – FPGA and ASIC Design with VHDL

Syntax and Terminology

Syntax Example Definition

sX

kk

PORT(kk)

PORT((sX))

RAM(kk)

s15

14

PORT(2)

PORT((S10))

RAM(4)

Value at register 15

Value 14

Input value from port 2

Input value from port specified by register 10

Value from RAM location 4

Page 9: ECE 44 8 – FPGA and ASIC Design with VHDL

Addressing modes

Direct mode

INPUT s10, 28ADD s10, s15

PORT(28) s10s10 + s15 s10

Indirect mode

INPUT s9, s2STORE s3, s10

PORT((s2)) s9 s3 RAM((s10))

s2 + 15 + C s2s7 – 7 s7

Immediate mode

ADDCY s2, 15SUB s7, 7

Page 10: ECE 44 8 – FPGA and ASIC Design with VHDL

Assembly language vs. machine code

Assembly language

mnemonic [operands]

ADDCY s2, 16

SUB s7, s8

Machine code*

1A 2, 10 1A2101C 7, 8 1C780

opcode [operands] instruction

*Value in HEX

Page 11: ECE 44 8 – FPGA and ASIC Design with VHDL

Logic instructions

1. ANDAND sX, sY

sX & sY => sXAND sX, kk

sX & kk => sX

2. OROR sX, sY

sX & sY => sXOR sX, kk

sX & kk => sX

3. XORXOR sX, sY

sX & sY => sXXOR sX, kk

sX & kk => sX

IMM, DIR

C Z

IMM, DIR

IMM, DIR

Page 12: ECE 44 8 – FPGA and ASIC Design with VHDL

Arithmetic Instructions1. Addition

1.1 ADD sX, sY sX + sY => sX

ADD sX, kk sX + kk => sX

1.2 ADDCY sX, sY sX + sY + CARRY => sX

ADDCY sX, kk sX + kk + CARRY => sX

2. Subtraction2.1 SUB sX, sY

sX - sY => sX SUB sX, kk

sX - kk => sX2.2 SUBCY sX, sY

sX - sY - CARRY => sX SUBCY sX, kk sX - kk - CARRY => sX

IMM, DIR

C Z

IMM, DIR

Page 13: ECE 44 8 – FPGA and ASIC Design with VHDL

Test and Compare Instructions

TEST TEST sX, sY

sX & sY => none TEST sX, kk

sX & kk => none

COMPARE COMPARE sX, sY

sX – sY => none COMPARE sX, kk

sX – kk => none

C Z

IMM, DIR

IMM, DIR

Page 14: ECE 44 8 – FPGA and ASIC Design with VHDL

Data Movement Instructions (1)

LOAD LOAD sX, sY

sY => sX LOAD sX, kk

kk => sX

STORE STORE sX, PP

sX => RAM(PP) STORE sX, (sY)

sX => RAM((sY))

FETCH FETCH sX, PP

RAM(PP) => sX FETCH sX, (sY)

RAM((sY)) => sX

IMM, DIR

DIR, IND

C Z

- -

- -

- -DIR, IND

Page 15: ECE 44 8 – FPGA and ASIC Design with VHDL

Data Movement Instructions (2)

INPUT INPUT sX, PP

sY => PORT(PP) INPUT sX, (sY)

sX => PORT((sY))

OUTPUT OUTPUT sX, PP

PORT(PP) => sX OUTPUT sX, (sY)

PORT((sY)) => sX

DIR, IND

DIR, IND

C Z

- -

- -

Page 16: ECE 44 8 – FPGA and ASIC Design with VHDL

Edit instructions - Shifts

*All shift instructions affect Zero and Carry flags

Page 17: ECE 44 8 – FPGA and ASIC Design with VHDL

Edit instructions - Rotations

*All rotate instructions affect Zero and Carry flags

Page 18: ECE 44 8 – FPGA and ASIC Design with VHDL

PicoBlaze ALU Instruction Set Summary (1)

Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD sX, kk 0 1 1 0 0 0 x x x x y y y y 0 0 0 0

ADD sX, sY 0 1 1 0 0 1 x x x x k k k k k k k k

ADDCY sX, kk 0 1 1 0 1 0 x x x x y y y y 0 0 0 0

ADDCY sX, sY 0 1 1 0 1 1 x x x x k k k k k k k k

AND sX, kk 0 0 1 0 1 0 x x x x y y y y 0 0 0 0

AND sX, sY 0 0 1 0 1 1 x x x x k k k k k k k k

COMPARE sX, kk 0 1 0 1 0 0 x x x x y y y y 0 0 0 0

COMPARE sX, sY 0 1 0 1 0 1 x x x x k k k k k k k k

FETCH sX, ss 0 0 0 1 1 0 x x x x 0 0 s s s s s s

FETCH sX, (sY) 0 0 0 1 1 1 x x x x y y y y 0 0 0 0

INPUT sX, (sY) 0 0 0 1 0 1 x x x x y y y y 0 0 0 0

INPUT sX, PP 0 0 0 1 0 0 x x x x p p p p p p p p

LOAD sX, kk 0 0 0 0 0 0 x x x x k k k k k k k k

LOAD sX, sY 0 0 0 0 0 1 x x x x y y y y 0 0 0 0

OR sX, kk 0 0 1 1 0 0 x x x x k k k k k k k k

OR sX, sY 0 0 1 1 0 1 x x x x y y y y 0 0 0 0

OUTPUT sX, (sY) 1 0 1 1 0 1 x x x x y y y y 0 0 0 0

OUTPUT sX, PP 1 0 1 1 0 0 x x x x p p p p p p p p

Page 19: ECE 44 8 – FPGA and ASIC Design with VHDL

PicoBlaze ALU Instruction Set Summary (2)

Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RL sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 1 0

RR sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 0 0

SL0 sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 0

SL1 sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 1

SLA sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 0 0

SLX sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 0 0

SR0 sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 0

SR1 sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 1

SRA sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 0 0

SRX sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 1 0

STORE sX, ss 1 0 1 1 1 0 x x x x 0 0 s s s s s s

STORE sX, (sY) 1 0 1 1 1 1 x x x x y y y y 0 0 0 0

SUB sX, kk 0 1 1 1 0 0 x x x x k k k k k k k k

SUB sX, sY 0 1 1 1 0 1 x x x x y y y y 0 0 0 0

SUBCY sX, kk 0 1 1 1 1 0 x x x x k k k k k k k k

SUBCY sX, sY 0 1 1 1 1 1 x x x x y y y y 0 0 0 0

TEST sX, kk 0 1 0 0 1 0 x x x x k k k k k k k k

TEST sX, sY 0 1 0 0 1 1 x x x x y y y y 0 0 0 0

XOR sX, kk 0 0 1 1 1 0 x x x x k k k k k k k k

XOR sX, sY 0 0 1 1 1 1 x x x x y y y y 0 0 0 0

Page 20: ECE 44 8 – FPGA and ASIC Design with VHDL

Part 2

Mini ALU

Page 21: ECE 44 8 – FPGA and ASIC Design with VHDL

opcode

A

B

M

RMini ALU

4

4

4

4

4

Page 22: ECE 44 8 – FPGA and ASIC Design with VHDL

Mnemonic Operation Opcode

ADDAB R= A + B 0000

ADDAM R = A + M 0001

SUBAB R = A - B 0010

SUBAM R = A - M 0011

NOTA R = NOT A 0100

NOTB R = NOT B 0101

NOTM R = NOT M 0110

ANDAB R = A AND B 0111

ANDAM R = A AND M 1000

ORAB R = A OR B 1001

ORAM R = A OR M 1010

XORAB R = A XOR B 1011

XORAM R = A XOR M 1100

Page 23: ECE 44 8 – FPGA and ASIC Design with VHDL

Block diagram

Page 24: ECE 44 8 – FPGA and ASIC Design with VHDL

Example 3

Variable Rotator

Page 25: ECE 44 8 – FPGA and ASIC Design with VHDL

Function

C = A <<< B

A – 4-bit data inputB – 2-bit rotation amount

Page 26: ECE 44 8 – FPGA and ASIC Design with VHDL

Interface

4

4

2

A

B

C

Page 27: ECE 44 8 – FPGA and ASIC Design with VHDL

Block diagram

C

Page 28: ECE 44 8 – FPGA and ASIC Design with VHDL

Fixed Shifts in VHDL

A(3) A(2) A(1) A(0)

A(3) A(2) A(1)

A>>1

A_shiftR <= ‘0’ & A(3 downto 1);

‘0’

‘0’

Page 29: ECE 44 8 – FPGA and ASIC Design with VHDL

Arithmetic Functions in VHDL (1)

To use arithmetic operations involving

std_logic_vectors you need to include the

following library packages:

library ieee;use ieee.std_logic_1164.all;use ieee.STD_LOGIC_UNSIGNED.ALL;

Page 30: ECE 44 8 – FPGA and ASIC Design with VHDL

Arithmetic Functions in VHDL (2)

You can use standard +, - operators

to perform addition and subtraction:

signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0);

……

C<= A + B;


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