ECE 554 MiniprojectECE 554 Miniproject

Spring 2002www.engr.wisc.edu/ece/courses/ece554.html

OBJECTIVESOBJECTIVES

To get familiar with the lab environment prior to the class project

To provide the basic I/O interface to the class project

Configuration DownloadConfiguration Download

XSV BoardXSV Board

XSV Block DiagramXSV Block Diagram

XSV Board: FeaturesXSV Board: Features

Xilinx Virtex FPGA (Compute)2 MB Memory (Store for Read/Write)Parallel & Serial Ports to PC

(I/O from/to Outside World)Keyboard (PS/2) PortVGA Output to VGA MonitorAudio/Video Converter

Current SetupCurrent SetupParallel Cable

Serial Cable

NT machine running

HyperTerminal

Parallel port: Configuration downloadSerial port: Miniproject

Asynch Serial CommunicationAsynch Serial Communication

Start bit (1 bit wide)Data bits (8 bits)Parity(None, Even, Odd)Stop bit (1 bit wide)

Baudrate and SamplingBaudrate and Sampling

4800 and 9600 bit per secondSampling rate = x16 of the baud rate

(bit rate)Divide the clock (5 and 20 MHz) to

get the “Enable” signal (sampling rate)

TransmittingTransmitting

Tx must be tested first.Tx shifts the “LSB” out from Tx

buffer first.Tx sends “stop bit” when there is

nothing to send.

ReceivingReceiving

Receiver samples the RxD to get the beginning of the “start bit”

Use “resynchronization” to avoid “metastability” of any flip-flop

Processor InterfaceProcessor Interface

Data is sent/received across the “bidirectional” data bus

Handshaking (status) signalsTBR: Transmit Buffer Ready (Empty)RDA: Receive Data AvailableCS: Chip SelectR/W_: Read or Write Bar signal

Testbench (mock Processor)Testbench (mock Processor)

A finite state machineReceives data on the RxD and

transmits back on the TxD (echos) back to the HyperTerminal

Note that it is not provided.

DemonstrationDemonstration

baud rate CLK4800 5 MHz4800 20 MHz9600 5 MHz9600 20 MHz