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1ECE 667 - Synthesis & Verification - Lecture 10
ECE 697B (667)ECE 697B (667)Spring 2006Spring 2006
Synthesis and Verificationof Digital Systems
Binary Decision DiagramsBinary Decision Diagrams
(BDD)(BDD)
ECE 667 - Synthesis & Verification - Lecture 10 2
OutlineOutline
• Background– Canonical representations
• BDD’s– Reduction rules
– Construction of BDD’s
– Logic manipulation of BDD’s
– Application to verification and SAT
• Reading:
read one of the BDD tutorials available on class web site– Anderson, or
– Somenzi
ECE 667 - Synthesis & Verification - Lecture 10 3
Common RepresentationsCommon Representations• Boolean functions ( f : B B )
– Truth table, Karnaugh map– SoP, PoS, ESoP– Reed-Muller expansions (XOR-based)– Decision diagrams (BDD, ZDD, etc.)
• Each minimal, canonical representation is characterized by– Decomposition type
• Shannon, Davio, moment decomposition, Taylor exp., etc.– Reduction rules
• Redundant nodes, isomorphic sub-graphs, etc.– Composition method (“Apply”, compose rule)
• What they represent– Boolean functions (f : B B)
– Arithmetic functions (f : B Int )
– Algebraic expressions (f : Int Int )
ECE 667 - Synthesis & Verification - Lecture 10 4
Binary Decision Diagrams (Binary Decision Diagrams (BDDBDD))
• Based on recursive Shannon expansion
f = x fx + x’ fx’
• Compact data structure for Boolean logic– can represents sets of objects (states) encoded as Boolean
functions
• Canonical representation– reduced ordered BDDs (ROBDD) are canonical– essential for verification
ECE 667 - Synthesis & Verification - Lecture 10 5
ROBDD’sROBDD’s
• Directed acyclic graph (DAG)• one root node, two terminals 0, 1• each node, two children, and a variable• Shannon co-factoring tree, except reduced and ordered
(ROBDD)– Reduced:
• any node with two identical children is removed• two nodes with isomorphic BDD’s are merged
– Ordered: • Co-factoring variables (splitting variables) always follow
the same order along all paths
xi1 < xi2
< xi3 < … < xin
ECE 667 - Synthesis & Verification - Lecture 10 6
ExampleExample
Two different orderings, same function.Two different orderings, same function.
a
b b
c c
d
0 1
c+bd b
root node
c+dc
d
f = ab+a’c+bc’d a
c
d
b
0 1
c+bd
d+b
b
1
0
ECE 667 - Synthesis & Verification - Lecture 10 7
ROBDDROBDDOrdered BDD (OBDD) Input variables are ordered - each path from root to
sink visits nodes with labels (variables) in ascending order.
a
c c
b
0 1
orderedorder = a,c,b
Reduced Ordered BDD (Reduced Ordered BDD (ROBDDROBDD) - reduction rules:) - reduction rules:1.1. if the two children of a node are the if the two children of a node are the samesame, the node is eliminated: f , the node is eliminated: f
= vf + vf= vf + vf2.2. if two nodes have if two nodes have isomorphic isomorphic graphs, they are replaced by one of graphs, they are replaced by one of
themthemThese two rules make it so that each node represents a distinct logic These two rules make it so that each node represents a distinct logic function.function.
a
b c
c
0 1
notordered
b
ECE 667 - Synthesis & Verification - Lecture 10 8
Efficient Implementation of BDD’sEfficient Implementation of BDD’s• BDDs is a compressed Shannon co-factoring tree:
• f = v fv + v fv
• leafs are constants “0” and “1”
• Three components make ROBDDs canonical (Proof: Bryant 1986):
– unique nodes for constant “0” and “1”
– identical order of case splitting variables along each paths
– hash table that ensures:
• (node(fv) = node(gv)) (node(fv) = node(gv)) node(f) = node(g)
– provides recursive argument that node(f) is unique when using the unique hash-table
v0 1
f
fv fv
ECE 667 - Synthesis & Verification - Lecture 10 9
Onset is Given by all Paths to “1”Onset is Given by all Paths to “1”
Notes:• By tracing paths to the 1 node, we get a cover of pair wise disjoint cubes.• The power of the BDD representation is that it does not explicitly
enumerate all paths; rather it represents paths by a graph whose size is measures by its nodes and not paths.
• A DAG can represent an exponential number of paths with a linear number of nodes.
• BDDs can be used to efficiently represent sets– interpret elements of the onset as elements of the set– f is called the characteristic function of that set
F = b’+a’c’ = ab’+a’cb’+a’c’ all paths to the 1 node
a
cb
0 1
10
1
10
0
f
fa= b’fa = cb’+c’
ECE 667 - Synthesis & Verification - Lecture 10 10
ImplementationImplementationVariables are totally ordered: If v < w then v occurs “higher” up in the ROBDDTop variable of a function f is a variable associated with its root node.Example: f = ab + a’bc + a’bc’. Order is (a < b < c).
fa = b, fa = b
a
b
0 1
f b is top variable of f
b
0 1
f
reducedf does not depend on a,
since fa = fa .
Each node is written as a triple: f = (v,g,h) where g = fv and h = fv . We read this triple as:
f = if v then g else h = ite (v,g,h) = vg+v ’ h
vf
0 1
h g
1 0f
v
g h
mux
v is top variable of f
ECE 667 - Synthesis & Verification - Lecture 10 11
BDD ConstructionBDD Construction• Reduced Ordered BDDReduced Ordered BDD
1 edge
0 edgea b c f
0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1
Truth table
f = ac + bc
Decision tree
10 0 0 1 0 10
a
b
c
b
c c c
f
ECE 667 - Synthesis & Verification - Lecture 10 12
BDD Reduction Rules -1BDD Reduction Rules -1• Eliminate redundant nodes Eliminate redundant nodes
(with both edges pointing to same node)(with both edges pointing to same node)
f = fa g(b) + fa’ g(b) = g(b)
(fa + fa’ = 1)bg
a
b
f
g
ECE 667 - Synthesis & Verification - Lecture 10 13
BDD Reduction Rules -2BDD Reduction Rules -2• Merge duplicate nodes (Merge duplicate nodes (isomorphicisomorphic subgraphs) subgraphs)
• Nodes must be unique
f1 = fa’ g(b) + fa h(c) = f2 f = f1 = f2
a a
b chg
f1 f2
a
b cg h
f
ECE 667 - Synthesis & Verification - Lecture 10 14
BDD Construction – cont’dBDD Construction – cont’d
10
a
b
c
b
c c c
f f
10
a
b
c
b
c
10
a
b
c
f = (a+b)c
2. Merge duplicate nodes
1. Merge terminal nodes 3. Remove redundant nodes
ECE 667 - Synthesis & Verification - Lecture 10 15
APPLYAPPLY Operator Operator
• Useful in constructing BDD for arbitrary Boolean logicUseful in constructing BDD for arbitrary Boolean logic
• Any logic operation can be expressed using Any logic operation can be expressed using Apply (ITE)Apply (ITE)
• Efficient algorithms, work directly on BDD graphsEfficient algorithms, work directly on BDD graphs
• Apply: F G, Apply: F G, any Boolean operationany Boolean operation((AND, OR, XOR, AND, OR, XOR, ))
=
F G
0 1 0 10 1
F G
ECE 667 - Synthesis & Verification - Lecture 10 16
Logic Manipulation using BDDsLogic Manipulation using BDDs
• Useful operatorsUseful operators
– Complement ¬ F = F’
(switch the terminal nodes)
– Restrict: F|x=b = F(x=b) where b = const
¬
1 00 1
F F’
0 1
F(x,y)
x=b 0 1
F(y)Restrict
ECE 667 - Synthesis & Verification - Lecture 10 17
Useful BDD Operators – Apply OperationUseful BDD Operators – Apply Operation• Basic operator for efficient BDD manipulation (structural)Basic operator for efficient BDD manipulation (structural)• Based on recursive Shannon expansionBased on recursive Shannon expansion
F F OPOP G = x (F G = x (Fxx OPOP G Gxx) + x’(F) + x’(Fx’x’ OPOP G Gx’x’))
wherewhere OPOP = OR, AND, XOR, etc = OR, AND, XOR, etc
ECE 667 - Synthesis & Verification - Lecture 10 18
Apply Operation (cont’d)Apply Operation (cont’d)
• Apply: F GApply: F Gwhere stands for any Boolean operator (AND, OR, XOR, where stands for any Boolean operator (AND, OR, XOR, ))
=
F G
0 1 0 10 1
F G
• Any logic operation can be expressed using only Restrict and
Apply
• Efficient algorithms, work directly on BDDs
ECE 667 - Synthesis & Verification - Lecture 10 19
Apply Operation - Apply Operation - ANDAND
10
a
c
aca AND c
10
a 2
c
10
3
0.3
2.3a
c1.3
1.11.0
AND
= =
ECE 667 - Synthesis & Verification - Lecture 10 20
Apply Operation - Apply Operation - OROR
OR
ac
10
a
c
4
5
bc
10
b
c
6
7 ==
10
a
b
c
f = ac+bc
c
4+6
0+0
a
7+5
1
0+6 b6+5
0+5
0
0+7
ECE 667 - Synthesis & Verification - Lecture 10 21
Application to VerificationApplication to Verification
• Equivalence Checking of Equivalence Checking of combinationalcombinational circuits circuits• CanonicityCanonicity property of BDDs: property of BDDs:
– if F and G are equivalent, their BDDs are identical (for the same if F and G are equivalent, their BDDs are identical (for the same ordering of variablesordering of variables))
10
a
b
c
F = a’bc + abc +ab’c G = ac +bc
10
a
b
c
ECE 667 - Synthesis & Verification - Lecture 10 22
Application to SATApplication to SAT
• Functional test generationFunctional test generation– SAT, Boolean SAT, Boolean satisfiability satisfiability
analysisanalysis
– to test for H = 1 (0), find a path to test for H = 1 (0), find a path in the BDD to terminal in the BDD to terminal 11 (0) (0)
– the path, expressed inthe path, expressed in function function variables, gives a satisfying variables, gives a satisfying solution (solution (test vectortest vector)) ab
ab’c
H
0 1
a
b
c
• Problem: size explosionProblem: size explosion
ECE 667 - Synthesis & Verification - Lecture 10 23
Efficient Implementation of BDD’sEfficient Implementation of BDD’s
Unique Table:• avoids duplication of existing nodes
– Hash-Table: hash-function(key) = value– identical to the use of a hash-table in AND/INVERTER circuits
Computed Table:• avoids re-computation of existing results
hash valueof key
collisionchain
hash valueof key
No collision chain