ECE U530 Digital Hardware Synthesisohm.bu.edu/~pbohn/__Engineering_Reference/ECEU530_HDL...ECEU530...

ECEU530

ECE U530Digital Hardware Synthesis

• Lecture 2:• CAD TOOLS: Xilinx and Modelsim• Levels of Design• VHDL Introduction

ECE U530 F06lect02.ppt

Prof. Miriam [email protected]

Sept 11, 2006

ECE U530 F’062lect02.ppt

Programming Assignments• All assignments are expected to represent individual

work !

• Programming assignments will be done on the WinCOE system

• Tools:• Xilinx ISE version 6.2i • Modelsim 5.7e

• Programming Assignments will be submitted electronically on the COE system

• You must have a COE account for this class

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WinCOE information• http://www.coe.neu.edu/computer/

has the information you need to get started• You must have a COE account for this class• Go to http://www.coe.neu.edu/computer/

then click on HELP!then click on Account Information For New Users

• WinCOE computers are available on the second floor of Snell Engineering


Xilinx and Modelsim• I have the tools on a PC (at work or at home). Can I

work there, then upload the solutions ?• Yes, but ...

It is your responsibility to make sure:Your programs run under the WinCOE versions.i.e. no problems with incompatibilities, file formats, etc.

• We will grade programs on the WinCOE system. It is your responsibility to make sure that they run there. • Version 6.2i of the Xilinx ISE tools• Version 5.7e of Modelsim

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Your files on WinCOE• The WinCOE system loads your COE home directory

every time you log in• Create a directory for this course in your COE home

directory:• Open an Explorer window

(right click on Start and choose Explore)• Navigate to Coewin �� winusers �� User_Name

This is your directory on the COE system• Create a new folder called 530local:

right click in the directory and choose New �� Folder• (You may already have a folder called ECEU530)

• Note: It is important that you not put empty spaces in any directory in the path for this course. The software tools do not recognize empty spaces. All names must be 8 characters or less.


Xilinx and Modelsim Tutorial• You should work through the ISE Quick Start Tutorial

by Wednesday, September 23.

• Start up the Xilinx tools, then click on:

Help -> Tutorials -> ISE Quickstart

and follow the instructions.

I have also put a copy on Blackboard under Homework

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Projects• Describe a large system in VHDL,

simulate with Modelsim• Work is expected to be individual• Deadlines

• Oct 4: Tell me your project idea• Oct 18: Formal project proposal• Nov 8: Progress report• Nov 20: Preliminary project report• Dec 13: Final project report

• Project ideas:• simple processor• robot controller• elevator controller


How to Describe Hardware Designs• Use CAD Tools

• CAD Tools translate your design into a hardware architecture

• Two types of design entry:• Schematic capture

–This is what you used in ECE U322/ECEU323• Hardware Description Language

–This is what this class is about

• CAD tools translate both types of descriptions to hardware

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The Need for HDLs• Technology trends

• 1 billion transistor chip running at 3 GHz

• Need for Hardware Description Languages• Systems become more complex• Design at the gate and flip-flop level becomes

very tedious and time consuming

• HDLs allow• Design and debugging at a higher level before

conversion to the gate and flip-flop level• Tools for synthesis do the conversion

• VHDL, Verilog are the most popular• VHDL – VHSIC Hardware Description Language


HDLs vs. Programming Languages• Procedural programming languages provide

algorithms, or the how of implenting a design• for computation• for data manipulation• typically independent of the hardware it is running on

• Hardware description languages describe a system• Interfaces are important• May want to describe in different ways

–behavior–structure

• May want to specify specific physical properties

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HDLs vs. Programming Languages (2)• Procedural programming languages:

• sequential execution• structural information less important• exact timing information is NOT important

• Hardware description languages:• Parallel execution• I/O ports, building blocks• Exact timing information IS important


Sequential vs. concurrent• This is a legal fragment of VHDL code• What order do these statements execute in?

A <= B + C;

C <= D + E;

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Why Describe a System?• Design Specification

• Unambiguous definition of components and interfaces• Documentation

• Design Simulation• verify performance prior to/after design implementation

–functional correctness–timing

• Design Synthesis• Automatic generation of a hardware design

• Component and Design Reuse• Technology Independence


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Domains and Levels of Modeling

high level of abstraction

FunctionalStructural

Geometric “Y-chart” due to Gajski & Kahn

low level of abstraction





Algorithm(behavioral)

Register-TransferLanguage

Boolean Equation

Differential Equation

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Processor-MemorySwitch

Register-Transfer

Gate

Transistor





Polygons

Sticks

Standard Cells

Floor Plan

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Design Levels

How Boolean logic and flipflops are implemented

Lower Levels: transistors, look up tables, ...

Boolean logic equations and flip-flops

Logic or Gate Level

Registers, wires, adders, muxes, etc. required to implement behavior

Register Transfer Level

Function of the system specified as pure behavior: a + b

Behavioral or Architectural Level

Type of DescriptionLevel


Abstraction levels and synthesis

Architectural level Logic level Circuit level

Beh

avio

ral l

evel

Stru

ctur

al le

vel

For I=0 to I=15Sum = Sum + array[I]

0

0 0

0

State

Memory

+

Control

Clk

Architecturesynthesis

Logicsynthesis

Circuitsynthesis

Layout level

Layoutsynthesis

Ideal synthesis system

(Library)(register level)

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Language Syntax and Semantics• The syntax of a language is the set of strings that

form legal programming constructs• External look of a language• Specified by a grammar

• The semantics of a language describes the meaning of a language

• Ideally the semantics is defined in terms of some abstract concept or mathematical model• various different ways to specify language semantics

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VHDL Syntax and Semantics• The VHDL standard specifies the syntax of VHDL,

NOT the semantics

• The semantics of VHDL is defined in terms of the VHDL simulator

• Many constructs have no meaning without reference to how the VHDL simulator works:

C <= A and B after 5 ns;


Introduction to VHDL• Developed originally by DARPA

• for specifying digital systems

• International IEEE standard (IEEE 1076-200x)• Last major revision is IEEE 1076-2001• This is the version used in the class text

• Hardware Description, Simulation, Synthesis• Provides a mechanism for digital design and

reusable design documentation• Support different description levels

• Structural (specifying interconnections of the gates), • Dataflow (specifying logic equations), and • Behavioral (specifying behavior)

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Introduction to VHDL (2)• Q: What does VHDL stand for?• A: VHSIC Hardware Description Language• Q: What is VHSIC?• A: Very High Speed Integrated Circuits• Q: What is VHDL used for?• A: To describe and test a digital circuit in a high level

language environment. • VHDL is defined by IEEE Standard 1076

• The latest major language revision was in 2001

• VHDL enables hardware modeling from the gate to the system level

• VHDL provides a mechanism for digital design and reusable design documentation


History of VHDL• Developed by IBM, Texas Instruments and

Intermetrics as part of the DARPA funded VHSIC program in the 1980s

• Standardized by the IEEE in 1987: • IEEE 1076-1987

• Last major language modification defined in 2001:• IEEE 1076-2001• (IEEE 1076-1993 was previous major modification)

• Standardized packages provide definitions of data types and expressions of timing data:• IEEE 1164 data types• IEEE 1076.3 numeric• IEEE 1076.4 timing

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Basic VHDL Concepts• Interfaces• Behavior• Structure• Test Benches• Analysis, elaboration, simulation• Synthesis

• A Hardware component is described as an entity/architecture pair• The entity defines the interfaces• One entity may have several associated architectures:

–Structural, behavioral, dataflow …


Modeling Interfaces• Entity declaration

• describes the input/output ports of a module

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end entity reg4;

entity name port names port mode (direction)

port typereserved words

punctuation

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Modeling Behavior• Architecture body

• describes an implementation of an entity• may be several per entity

• Behavioral architecture• describes the algorithm performed by the module• contains

–process statements, each containing»sequential statements, including

signal assignment statements andwait statements


Behavior Example

architecture behav of reg4 isbegin

storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;

beginif en = '1' and clk = '1' then

stored_d0 := d0;stored_d1 := d1;stored_d2 := d2;stored_d3 := d3;

end if;q0 <= stored_d0 after 5 ns;q1 <= stored_d1 after 5 ns;q2 <= stored_d2 after 5 ns;q3 <= stored_d3 after 5 ns;wait on d0, d1, d2, d3, en, clk;

end process storage;end architecture behav;

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Modeling Structure• Structural architecture

• implements the module as a composition of subsystems• contains

–signal declarations, for internal interconnections»the entity ports are also treated as signals

–component instances»instances of previously declared entity/architecture pairs

–port maps in component instances»connect signals to component ports

–wait statements


Structure Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0d_latchd

clk

q

bit1d_latchd

clk

q

bit2d_latchd

clk

q

bit3d_latchd

clk

q

gateand2

a

b

y

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Structure Example• First declare D-latch and and-gate entities and

architectures

entity d_latch isport ( d, clk : in bit; q : out bit );

end entity d_latch;

architecture basic of d_latch isbegin

latch_behavior : process isbegin

if clk = ‘1’ thenq <= d after 2 ns;

end if;wait on clk, d;

end process latch_behavior;end architecture basic;

entity and2 isport ( a, b : in bit; y : out bit );

end entity and2;

architecture basic of and2 isbegin

and2_behavior : process isbegin

y <= a and b after 2 ns;wait on a, b;

end process and2_behavior;end architecture basic;


Structure Example• Now use them to implement a register

architecture struct of reg4 issignal int_clk : bit;

beginbit0 : entity work.d_latch(basic)

port map ( d0, int_clk, q0 );bit1 : entity work.d_latch(basic)



port map ( d3, int_clk, q3 );gate : entity work.and2(basic)

port map ( en, clk, int_clk );end architecture struct;

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Structure Example in VHDL-87• First declare D-latch and and-gate entities and

architectures

entity d_latch isport ( d, clk : in bit; q : out bit );

end d_latch;

architecture basic of d_latch isbegin

latch_behavior : processbegin

if clk = ‘1’ thenq <= d after 2 ns;

end if;wait on clk, d;

end process latch_behavior;end basic;

entity and2 isport ( a, b : in bit; y : out bit );

end and2;

architecture basic of and2 isbegin

and2_behavior : processbegin

y <= a and b after 2 ns;wait on a, b;

end process and2_behavior;end basic;


Structure Example in VHDL-87• Declare corresponding components in register

architecture body

architecture struct of reg4 iscomponent d_latch

port ( d, clk : in bit; q : out bit );end component;component and2

port ( a, b : in bit; y : out bit );end component;signal int_clk : bit;

...

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Structure Example in VHDL-87• Now use them to implement the register

...begin

bit0 : d_latchport map ( d0, int_clk, q0 );




gate : and2port map ( en, clk, int_clk );

end struct;


Structure Example in VHDL-87• Configure the register model

configuration basic_level of reg4 isfor struct

for all : d_latchuse entity work.d_latch(basic);

end for;for all : and2

use entity work.and2(basic)end for;

end for;end basic_level;

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Mixed Behavior and Structure• An architecture can contain both behavioral and

structural parts• process statements and component instances

–collectively called concurrent statements• processes can read and assign to signals

• Example: register-transfer-level model• data path described structurally• control section described behaviorally


Mixed Example

shift_reg

reg

shift_adder

control_section

multiplier multiplicand

product

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Mixed Exampleentity multiplier is

port ( clk, reset : in bit;multiplicand, multiplier : in integer;product : out integer );

end entity multiplier;

architecture mixed of mulitplier issignal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;

beginarith_unit : entity work.shift_adder(behavior)

port map ( addend => multiplicand, augend => full_product,sum => partial_product,add_control => arith_control );

result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,

en => result_en, reset => reset );...


Mixed Example…multiplier_sr : entity work.shift_reg(behavior)

port map ( d => multiplier, q => mult_bit,load => mult_load, clk => clk );

product <= full_product;

control_section : process is-- variable declarations for control_section-- …

begin-- sequential statements to assign values to control signals-- …wait on clk, reset;

end process control_section;end architecture mixed;

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Behavioral

Architecture

Dataflow

Architecture

Structural

Architecture

Package

EntityGeneric Ports

Functional

Architecture

Modeling Hardware With VHDL


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Modeling Hardware with VHDL (2)

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Design Processing• Analysis• Elaboration• Simulation• Synthesis


Analysis• Check for syntax and semantic errors

• syntax: grammar of the language• semantics: the meaning of the model

• Analyze each design unit separately• entity declaration• architecture body• …• Analyzed design units are placed in a library

in an implementation dependent internal form• current library is called work

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Elaboration• “Flattening” the design hierarchy

• create ports• create signals and processes within architecture body• for each component instance, copy instantiated entity and

architecture body• repeat recursively

–bottom out at purely behavioral architecture bodies

• Final result of elaboration• flat collection of signal nets and processes


Elaboration Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0d_latchd

clk

q

bit1d_latchd

clk

q

bit2d_latchd

clk

q

bit3d_latchd

clk

q

gateand2

a

b

y

reg4(struct)

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Elaboration Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0

bit1

bit2

bit3

gate

reg4(struct)d_latch(basic)d

clk

q

d_latch(basic)d

clk

q

d_latch(basic)d

clk

q

d_latch(basic)d

clk

q

and2(basic)a

b

yprocess with variables

and statements


Simulation• Execution of the processes in the elaborated model• Discrete event simulation

• time advances in discrete steps• when signal values change—events

• A processes is sensitive to events on input signals• specified in wait statements• resumes and schedules new values on output signals

–schedules transactions–event on a signal if new value different from old value

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Simulation Algorithm• Initialization phase

• each signal is given its initial value• simulation time set to 0• for each process

–activate–execute until a wait statement, then suspend

»execution usually involves scheduling transactions on signals for later times


Simulation Algorithm• Simulation cycle

• advance simulation time to time of next transaction• for each transaction at this time

–update signal value»event if new value is different from old value

• for each process sensitive to any of these events, or whose “wait for …” time-out has expired–resume–execute until a wait statement, then suspend

• Simulation finishes when there are no further scheduled transactions

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VHDL’s Discrete Event Simulator• Simulator models:

• delays • events • concurrency

• An event is a change in value on a signal• Assumption:

Events happen instantaneously at discrete points in time

• Discrete event simulation: Model time when an event is scheduled to happen: Used in VHDL

• Alternative: continuous time simulation model• NOT used in VHDL• Advance time to next time step, look for events


VHDL’s Discrete Event Simulator(2)1. Initialize all signals, set time to t =02. For all signals that have events at time t,

activate processes, statements or gatestriggered by those signals

3. Evaluate processes and schedule events on outputs to occur at future time (never NOW !)by putting events in time queue

4. If there are more events (or simulation time not over)Then update t to next event and go to step 2Else simulation over

Next event may be at t + δδδδ, t + 5ns, t + 2 minutes ...

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Test Benches• Testing a design by simulation• Use a test bench model

• an architecture body that includes an instance of the design under test

• applies sequences of test values to inputs• monitors values on output signals

–either using simulator–or with a process that verifies correct operation

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Test Bench Exampleentity test_bench isend entity test_bench;

architecture test_reg4 of test_bench issignal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;

begindut : entity work.reg4(behav)

port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );stimulus : process isbegin

d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns;en <= ’1’; wait for 20 ns;clk <= ’1’; wait for 20 ns;d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns;en <= ’0’; wait for 20 ns;…wait;

end process stimulus;end architecture test_reg4;


Regression Testing• Test that a refinement of a design is correct

• that lower-level structural model does the same as a behavioral model

• Test bench includes two instances of design under test• behavioral and lower-level structural• stimulates both with same inputs• compares outputs for equality

• Need to take account of timing differences

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Regression Test Examplearchitecture regression of test_bench is

signal d0, d1, d2, d3, en, clk : bit;signal q0a, q1a, q2a, q3a, q0b, q1b, q2b, q3b : bit;

begindut_a : entity work.reg4(struct)

port map ( d0, d1, d2, d3, en, clk, q0a, q1a, q2a, q3a );dut_b : entity work.reg4(behav)

port map ( d0, d1, d2, d3, en, clk, q0b, q1b, q2b, q3b );stimulus : process isbegin

d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns;en <= ’1’; wait for 20 ns;clk <= ’1’; wait for 20 ns;…wait;

end process stimulus;...


Regression Test Example…verify : process isbegin

wait for 10 ns;assert q0a = q0b and q1a = q1b and q2a = q2b and q3a = q3b

report ”implementations have different outputs”severity error;

wait on d0, d1, d2, d3, en, clk;end process verify;

end architecture regression;

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Synthesis• Register Transfer Level Synthesis:

• Translates register-transfer-level (RTL) design into gate-level netlist

• Restrictions on coding style for RTL model• Tool dependent

• High Level Synthesis• Translate behavioral code to RTL level• Beyond the scope of this course

• Logic Level Synthesis• Tranlate gate-level net list into implementation technology

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Basic Design Methodology

Requirements

SimulateRTL Model

Gate-levelModel

Synthesize

Simulate Test Bench

ASIC or FPGA Place & Route

TimingModel Simulate


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Combinational Hardware in VHDL


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