ECE471� Energy E�cient VLSI Design

Project 2 � Cadence Setup and Creation of an Inverter

Due Date � 11:30pm on Friday, January 25th 2013

Introduction

This project will �rst walk you through the setup for use of the 0.25µm process with Cadence Design Framework II. Thenyou will create the schematic, symbol, and layout of an inverter. Much of the information in this lab manual was takenfrom Dr. Moon's Design Framework Tutorial. For more information you can refer to his page at:

http://web.engr.oregonstate.edu/~moon/ece423/cadence/

Setup

Following these steps will help you setup the Cadence Design Framework.

1. To run Cadence, you just need to have /usr/local/apps/bin in your path (this is valid both for the ECE andfor the ENGR machines). To check this go to your home directory and look at the PATH variable inside of your.cshrc �le.

2. To setup Cadence you must create a directory inside of you ECE471 folder named �cadence� in which you cansave your Cadence projects. Change your current directory to �cadence�. Once you have changed your currentdirectory to your Cadence project directory, run the Cadence setup script by typing the following command at theterminal:/nfs/guille/u1/c/cdsmgr/cdsmgr/process/CDK1.4/tsmc025/setup

This sets your directory to work with the TSMC 0.25µm process and copies the appropriate �les to that directory.

3. Next you will need to edit your .cshrc �le. This �le is found in you home directory, and it is a hidden �le (it startswith a '.'). If you're using a graphical �le browser, simply specify that hidden �les should be displayed. If you usea terminal window, you can �nd the �le by typing �ls -all� or many other commands. Once you've found the.cshrc �le, open it in a text editor and append the following commands to the end of the �le:setenv CDS_SITE /nfs/guille/u1/c/cdsmgr/cdsmgr/pdk/CDK1.4/local

setenv SKIP_CDS_DIALOG 0

setenv USE_NCSU_CDK 0

setenv CDS_Netlisting_Mode Analog

4. You must also replace one of the cadence initialization �les. The script above creates some basic init �les. Unfortu-nately, the layout tool will not work unless you replace the .cdsinit �le that was placed in your cadence directory.Simply save the �cdsinit� �le from the lab webpage in your cadence directory as �.cdsinit�. Remember, this isa hidden �le, so you won't be able to see it unless you specify that you want to view hidden �les.

5. Now you'll need to change a location in one �le. Open cds.lib and change any line with �~cdsmgr/� to�/nfs/guille/u1/c/cdsmgr/� This can be done with a simple sed if you prefer:sed "s/~cdsmgr/\/nfs\/guille\/u1\/c\/cdsmgr\/cdsmgr/g" cds.lib

6. Next you must add the local cadence icfb shortcut �le. Download this �le from Lab webpage and copy it into yournewly created cadence folder. Then change the permissions to ensure its executable (either �chmod u+x icfb� orbrowse to the �le in your �le browser, right click, go to the permissions tab and select the executable box).

7. You can now start DFII by typing �./icfb� from that directory.

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Creating a layout

This section will walk you through the process of creating a design and layout. In this case, we will make an inverter.

Create a library for your new design

From the library manager window go to:File→ New → LibraryType a new name, such as ECE471. Under the heading �Technology File�, choose �Compile a new tech�le�. Then

from the drop-down menu choose �TSMC 0.24u CMOS025/DEEP (5M, HV FET)�. Click OK.

Create a new cell, where you will design the inverter

In Library Manager, highlight your new library (ECE471 if that is what you chose). Go to:File→ New → CellviewChoose library ECE471, cell name �inverter�, view name �schematic�, and Tool �Composer- Schematic�. Click OK.

Design your circuit

The next step is to create the schematic for your circuit.

Placing components

For this inverter, you will need a nmos transistor, a pmos transistor, and power and ground nodes.

• From Schematic window: Add→ Instance The Add Instance and Component Browser windows will open. Makesure the Library in the Component Browser is set to NCSU_Analog_Parts.

• Use the Component Browser window ('i' is hot key for Component browser instantiate) and single click N_Transistors,then select nmos4 and place it. Place the component. Do the same for a pmos (P_Transistors and pmos4) Eschot key helps you to escape.

• Also, from the NCSU_Analog_Parts, get the symbols for vdd and gnd from Supply_Nets (they de�ne the netnames for the power and ground nodes).

• Create input and output pins by pressing 'p'. Give each pin an appropriate name and select the proper direction(input or output).

• To size the transistors properly �rst highlight the NMOS transistor and press 'q', then change the width to 480nm.Next change the PMOS width to 960nm. Be sure to include the 'nm' post�x.

• Use wires to connect the parts accordingly (Be sure that the PMOS bulk is connected to vdd, and the NMOS bulkis connected to gnd).

• Go to: Design→ Check and Save to save the design and check for any errors. If there are errors, they will showup in the icfb log window.

Some other hot keys are 'f' for re-centering screen and 'w' for placing wires.

Generating HSPICE netlist from schematic

To create a netlist, go to Tools → Analog Environment → Simulation → Netlist → Create F inal. To save thenetlist go to File→ Save As and type in the full path to where you want it saved. (For example, mine would be savein the location: ~/ECE471/Lab2/netlist.spi)

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Creating a symbol

Creating a symbol for your circuit is useful for integration into a larger design. If you are creating a circuit that usesinverters, it is handy to view the inverters in a schematic as the inverter symbol, rather than just seeing it at transistorlevel.

• In your schematic window go to: Design → Create Cell view → From Cell view. Make sure that the From

View Name �eld is �schematic�, and the To View Name �eld is �symbol�. Press OK.

Figure 1: Schematic symbol of an inverter.

• We want the our symbol to simply look like this inverter symbol seen in �gure 1. To do this, go to Add→ Shapeand add the necessary shapes (use polygon to create a triangle). Your �nal symbol should match �gure 2.

Figure 2: Final symbol of an inverter.

Creating the layout

• To start a new inverter layout, go back to the library manager window, highlight your ECE471 library and go to:File → New → Cell view. In the View Name �eld put �layout�, and in the Tool �eld select �Virtuoso.� PressOK.

• To add new parts, once again press 'i'. Choose Browse, and highlight: NCSU_TechLib_tsmc03d→ nmos→layout. Change the width to 480nm, then go ahead and place the NMOS on the grid. Repeat this process withthe PMOS (changing the width to 960nm), and place it above the NMOS, and then press �Shift+f� keys. Yourscreen should look similar to �gure 3.

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Figure 3: Layout with NMOS and PMOS mosfets.

• Now we want to connect the drains of the transistors. To do this, go to the LSW window and highlight the metal1box, press 'r', and draw metal1 connecting both drains to each other similar to �gure 4.

Figure 4: Metal connecting mosfets.

• Now we need to connect the gates, select the �poly drw� box in the LSW window, and connect the gates similarto �gure 5.

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Figure 5: Gates connected.

• Next we will place the ntap and ptap. For the ntap press 'i', then select browse and highlight: NCSU_techLib_tsmc03d→ntap→ layout and place it as shown in �gure 6, then add the ptap in a similar manner.

Figure 6: Mosfets with taps.

• Using M1 (metal1), connect the source of the NMOS to gnd and PMOS to vdd as shown in �gure 7.

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Figure 7: Connecting to supply rails.

• We want for our �in� pin to connect on metal1, and our �out� pin to connect on metal3. To do this we willhave to use vias. Press 'i', and highlight: NCSU_TechLib_tsmc03d → M1 − Poly → layout, and place theconnector as shown in �gure 8 for the input. For the output, compound an M1-M2 connector with a M2-M3connector as shown in �gure 8. We will also take both M1 and M3 and extend the input and output.

Figure 8: Input and output pins.

• Next we want to place the pins. Go to: Create→ Pin, change the terminal name to �in� and set the I/O type toinput. Change Pin type to metal1. Click on Display Pin and change layer to metal1-dg. Repeat this processfor the �out� pin, making all the necessary changes. Make sure the pins are placed on the appropriate spots (onthe appropriate metal layers).

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• Finally, we want to add vdd and gnd. These will be added using pins, but this time, the I/O type will be set toInput/Output. Set the metal layer properly and place the pins on the correct locations.

Running DRC/Parasitic Extraction

• Go to V erify → DRC and press OK. If your design has any errors they will show up in your icfb Log window. Ifyou have errors take a look at them and see if you can �x them.

• To do parasitic extraction go to: V erify → Extract, in that window select: Set Switches→ Extract Parasitics Capsand press OK. ICFB should show you no errors. There will be a new cell called extracted in your Cadence LibraryManager, open this up.

• In this window go to: Tools → Analog Environment → Simulations → Netlist → Create F inal. This willcreate the new netlist containing your extracted view.

What to turn in

Turn in a PDF to TEACH by Friday, January 25th by 11:30pm with the following things:

• Screenshots of your completed, error free schematic and HSPICE schematic netlist.

• A screenshot of your completed symbol.

• Screenshots of your completed, DRC clean layout, and your extracted HSPICE netlist.

• An explanation of any problems you may have had.

• Answer to the following question:Why is it important to simulate your circuit both after schematic and post-layout? (after parasitic extraction)

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