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Last (family) name: _________________________ First (given)
name: _________________________ Student I.D. #:
_____________________________ Circle section: Hu Saluja
Department of Electrical and Computer Engineering University of
Wisconsin - Madison
ECE/CS 352 Digital System Fundamentals
Quiz #4 Thursday, April 25, 2002, 5:30-6:45 PM
Instructions: 1. Closed book examination.2. No calculator,
hand-held computer or portable computer allowed. 3. Five points
penalty if you fail to enter name, ID#, or instructor selection. 4.
Answer must be entered into specified boxes if provided. 5. You
must show your work to receive full or partial credit for your
answers. 6. No one shall leave room during last 5 minutes of the
examination. 7. Upon announcement of the end of the exam, stop
writing on the exam paper immediately.
Pass the exam to isles to be picked up by a TA. The instructor
will announce when to leave the room.
8. Failure to follow instructions may result in forfeiture of
your exam and will be handled according to UWS 14 Academic
misconduct procedures.
ECE/CS 352 Quiz #3 11/19/02
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Problem Points Score
1 15
2 25
3 20
4 25
5 15
Total 100 1. (15 points) Registers
(a) (5 points) The content of a 4-bit bi-directional shift
register with parallel load (shown in the text book as SHR4) was
1011 initially. The parallel load data is 1111. The right serial
input (RSI) is connected to a logic “0” and the left serial input
(LSI) is connected to the left serial output Q3 as shown below:
SHR 4 RSI
Q3 Q2 Q1 Q0
S1 S0
LSI
D3 D 2 D 1 D 0Specify the output of this shift register Q3Q2Q1Q0
after executing the operation on the left in each row of the
following table.
Answer:
Operations Q3 Q2 Q1 Q0
Initially 1 0 1 1
Left shift
left shift
Parallel load
Right shift
Left shift
S02, ECE/CS 352 Quiz #4
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(b) (10 points) A 4-bit multi-function register operates
according to a function table where S1, S0 are two mode selection
inputs.
S1 S0 Register operation 0 0 No change 0 1 Load Parallel data 1
0 1's Complement of current content 1 1 Shift left
This register is to be implemented by cascading four identical
1-bit modules. The i-th bit module has two outputs Q t and ( )i (
)iQ t , and four external inputs, S1, S0, Ii(t) (parallel load
data), and Qi−1(t) (shift left). Implement this i-th bit module
using a D-type positive edge triggered flip-flop and a SOP
realization of flip-flop input equations with minimum number of
AND, OR, NOT logic gates. Give the logic diagram
Answer:
Qi(t)
clock
Qi(t)
D
ECE/CS 352 Quiz #4
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2. (25 points) Counters (a) (3 points) A 4-bit ring counter is
implemented with a (right-shift) shift register that will
be initialized to a value of 1000. Specify the remaining counter
outputs of this ring counter in correct order. Answer:
(b) (4 points) A switch-tail ring counter (a.k.a. Johnson
counter, twist ring counter) uses the complement of the serial
output as the serial input to a (right-shift) shift register. If
such a counter is initialized with 1000, specify the remaining
counter outputs. Answer:
ECE/CS 352 Quiz #4
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(c) (8 points) CTR4 is the four bit up-counter with parallel
load discussed in the text book. CO is carry out and is not needed
for this problem. Our goal is to design a counter that will count
from the 10 excess-3 coded decimal digits: 0011, 0100, … , 1100.
Use as few as possible logic gates and a single CTR4 counter to
design this synchronous excess-3 binary coded counter. Use "1" to
indicate logic 1, and "0" to indicate logic 0 where-ever needed in
your implementation. Specify the K-map of the input “Load”.
Answer:
Q3Q2\Q1Q0 00 01 11 1000
01
11
10
CTR4
Load Count D0 Q0 D1 Q1 D2 Q2 D3 Q3 CO
Clock
ECE/CS 352 Quiz #4
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(d) (10 points) Draw the logic diagram of a 3-bit synchronous,
binary down-counter that counts in the following sequence: 111,
110, 101, 100, 011, 010, 001, 000, 111, …. Use 3 J-K type
flip-flops, and AND, OR, NOT logic gates. Specify count enable
signal EN and carry out signal CO. The JK flip-flop excitation
table is provided for your convenience. Answer:
Q2
Q1
Q0
K Q
Q J
K Q
Q J
K Q
Q J
Clock
JK Flip-Flop Q(t) Q(t+1) J K
0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0
ECE/CS 352 Quiz #4
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3. (20 points) Memory organization (CHAPTER 6, WILL NOT BE ON
QUIZ 4) (a) (4 points) With coincident selection scheme (2D
memory), a 128K × 1 memory employs
two decoders to provide the row select and column select
signals. Suppose there are twice as many row-select lines (they are
output lines of the row select decoder) than the column-select
lines. How many address lines are feeding into the column-select
decoder?
Answer: address lines are connected to the column select
decoder.
(b) (4 points) A 64K × 1 memory chip is made of a square memory
cell arrays. First part (most significant bits) of an address will
feed into the row-select decoder and the remaining address lines
will feed into column select decoder. Suppose the address in
hexdecimal format is A2BEH. Find the physical location (column and
row numbers) of the memory cell that is addressed.
Answer: Row number: = ; column number: =.
(c) (3 points) How many 16K × 4 RAM chips are required to build
a 128K × 16 RAM subsystem?
Answer: chips.
ECE/CS 352 Quiz #4
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(d) (4 points) A random access read/write memory is constructed
of four 1024 word by 4 bit integrated circuits chips with all
address, data, and R/W lines tied in parallel (ie: A0 on Chip 0 to
A0 on Chip 1, to A0 on Chip 2, to A0 on Chip 3, etc.). The chip
select lines are separately tied to the outputs of a 2-line to
1-of-4 decoder which has S1 and S0 inputs tied to Address bit A11
and A10 respectively. Fill in the blanks below.
Answer: The size of the RAM is
1024×4 RAM DATA ADRS CS R/W
R/W
10 1010 10
2 A(11:10)
A(9:0)
2-to-4 Decoder
1024×4 RAM DATA ADRS CS R/W
1024×4 RAM DATA ADRS CS R/W
1024×4 RAM DATA ADRS CS R/W
(e) (5 points) Connect the inputs of three 3-state buffers so
that it implements a Boolean function G = A⋅B + C⋅D + E⋅F where
A+C+E = 1 and A⋅C=C⋅E=E⋅A = 0
ECE/CS 352 Quiz #4
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4. (25 points) PLA, PAL implementation (CHAPTER 6, WILL NOT BE
ON QUIZ 4) (a) (8 points) Implement the following two Boolean
functions using a PLA. The objective is
to minimize the number of product terms needed. Give your answer
by filling in the PLA programming table below. You should also
specify that whether the outputs need to be Complemented (C) or
remain in original form: True (T). Note that you should not need
more than six product terms!
∑∑
=
=
)6,4,1(),,(
)7,5,0(),,(
2
1
mcbaF
mcbaF
Answer:
Inputs Outputs Product Term a b c F1 F2 1
2
3
4
5
6
Enter T or C:
ECE/CS 352 Quiz #4
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(b) (9 points) The following four Boolean functions are to be
implemented using a PAL that has 3 inputs, four outputs, and a
two-wide AND-OR structure (each output OR gate has two inputs).
Complete the PAL connection map below. Label each output or the OR
gates, and mark each required connection with “×”.
∑∑∑∑
=
=
=
=
)7,4,3,2(),,(
)4,3,2(),,(
)6,5,4,1,0(),,(
)7,6,3(),,(
mzyxD
mzyxC
mzyxB
mzyxA
x y z w
z
y
x
ECE/CS 352 Quiz #4
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(c) (8 points) For the same set of Boolean functions as
specified in part (b), implement them using a ROM. Specify the
minimum size of the ROM and its address and corresponding contents:
Answer: The minimum size of the ROM is by . The addresses and
contents are:
Address Content
ECE/CS 352 Quiz #4
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5. (15 points) Hazards The circuit shown below is constructed of
gates that have a delay of 5 nanoseconds. Initially, all signals
are stable as shown on the left edge of the diagram. Inputs "D0"
and "S" simultaneously change from 0 to 1 while D1 remains stable
at "0", causing the change shown in signal "a" and no change in
signal "d".
b
c
da
D1
D0
S F
5 ns.
D1
S
a
b
c
d
0
0
0
0
0
0
0 1
1
1
1
1
1
1 D0 0
1
F
(a) (6 points) On the diagram above, plot the waveforms for "b",
"c", and "F".
ECE/CS 352 Quiz #4
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(b) (3 points) Circle the type of hazard that the circuit will
have. (CIRCLE ALL THAT ARE TRUE)
SICS
Zero
Hazard
SICS
One
Hazard
Function
Hazard
(MICS Hazard)
Dynamic
Hazard
(c) (6 points) A Boolean function f(A, B, C, D) is implemented
in SOP format as follows: ( , , , )f A B C D A D B C D A B C= ⋅ + ⋅
⋅ + ⋅ ⋅
Identify ALL the product terms that need to be added to this SOP
expression to guarantee that it is free of all the static and
dynamic hazards.
Answer:
ECE/CS 352 Quiz #4
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Department of Electrical and Computer EngineeringECE/CS 352
Digital System FundamentalsQuiz #4
Thursday, April 25, 2002, 5:30-6:45 PMInstructions:
ProblemJK Flip-Flop
JK000X011X10X111X0((A(A(A(A(((�APTIOPabcFF12
