EDA Trends on IP-Based Design -1- nweum 1999. 7. 31. EDA Trends on IP-Based Design Nak-Woong Eum.

nweumEDA Trends on IP-Based Design -1-

1999. 7. 31.

EDA Trends on IP-Based Design

Nak-Woong Eum


Contents▣ Introduction

◈ Co-design versus IP-based design

◈ System level design language initiative

◈ Roadmap of system level design

▣ Trends of Design Reuse

▣ Requirements on IP-Based Design

▣ Trends of IP Design◈ IP Design Tools

◈ IP Verification

◈ IP Security

▣ Conclusion


Introduction▣ Forecast of SIA (Semiconductor Industry Association)

◈ Silicon density : 58 %/year, but CAD tool capacity : 21%/year

◈ Silicon density in 2001 : 107 gates/chip System-on-a-chip (SoC)

▣ New Concept : Design reuse◈ Reusable Core, Module, or Block : Virtual Component

◈ VC + License (copyright, patent and trade secrete) IP (Intellectual Property)

▣ System Level Design◈ Co-design : SLDL (System Level Design Language) Initiative

o Deliver an entirely new technology at the front end of the process

o Facilitate reuse by allowing true HW/SW co-design and system constraint budgeting

◈ IP-based design : VSI (Virtual Socket Interface) Allianceo Establish common standards that will facilitate large-scale design reuse on silicon

o Provide better infrastructure for HW implementation by leveraging existing technologies


System Level Design ?▣ Perspectives of Systems

◈ System function

◈ Processing platform on which that system is running

◈ Methodology and process by which the function is mapped onto the platform

▣ SoC may include◈ Dual DSP/micro-controller chips, the drive toward standard embedded

software/operating systems/hardware platforms

◈ Mapping a system onto a processing platform is not trivial

▣ New approach to SLD (current approach: manual)◈ Reassigning the division of labor between processors, memory hierarchies, operating

systems, and compilers in order to optimize design cost

▣ Drawbacks of existing languages and methodologies◈ Model of concurrency requires high overhead when running on a target platform

“System-level design is neither software design nor hardware design, and the languages and tools for doing them are not applicable at the system level” - Cary Ussery

Introduction


specification capture

functional specification

system-level description

design space exploration

specification refinement

software&hardware design

transformation, allocation, partitioning, estimation

memories, interfacing, arbitration, generation

software synthesis, high-level synthesis, logic synthesis, ...

model creation, description generation

co-v

erif

icat

ion,

val

idat

ion

Scope of Co-design▣ Design flow model

Introduction


global system specification and design

specification language

exploration&partitioning&architecture selection

software synthesis

interface&communication synthesis

hardware synthesis

co-verification

prototype/real product development

property assessment (performance, cost, power, ...)

Co-design Research Focus

- by D. Gajski

Introduction


System Level Design Language▣ Requirements and Features for SLDL

◈ Requirements and constraintso Specify the value and the meaning of the parametric values

o State things in a domain-independent fashion

o Specify cross-domain constraint specification

◈ Hardware/software co-designo Support abstract performance models of microprocessors, real-time operating systems, and

application algorithms

o Provide semantic consistency for interfaces of performance models regardless of abstraction level

o Allow smooth transition from system-level into implementation domains

o Establish a structured mapping between an event at the system level and an event, or a set of events, at the component level

◈ Formal semanticso Partial specifications permit incomplete descriptions that can be analyzed using formal

consistency techniques

Introduction


Semantic Requirements Cube (S. Schulz)

System Level Design Language (Cont’d)▣ Phase I :

◈ Cross-domain constraint specifications (timing and operational parameters)

◈ Information flow between components

◈ Structural descriptions of component interaction

▣ Phase II : ◈ Consistent abstractions of time

◈ Consistent semantics for information flow

◈ Integrating several behavioral models

by “Bridging semantics”

Introduction


System Level Design Language (Cont’d)

SLDL Plug and Play Architecture (S. Schulz)

Introduction


System Level Design Language (Cont’d)▣ Rosetta (www.inmet.com/SLDL)

◈ Sponsored by VHDL International, EDA Industry Council, IEEE DASC, European CAD Standardization Initiative, and U.S. Air Force Research Labs

◈ Describe SoC design constraints and behavior at architectural levels prior to HW-SW partitioning

◈ SLDL assisted silicon is scheduled by Q4 2000

▣ VHDL+ (www.eda.org/sid) ◈ VHDL extensions to cover system and interface based design

◈ Proposed by “System and Interface Design” Working Group

◈ Submitted to IEEE NesCom (National Engineering Standards Committee) at April 1999

▣ Suave (www.cs.adelaide.edu.au/~petera)◈ VHDL extensions for system-level modeling◈ One of individual experiences

“Considerations on system-level behavioural and structural modeling extensions to VHDL,” VHDL International Users Forum(VIUF), pp. 42 -50, 1998

Introduction


Roadmap of Design & Test - SIA

Introduction


Roadmap of System Level Design - SIA

Introduction


▣ Introduction



▣ Trends of IP Design

▣ Conclusion


Design Reuse

Mix-and-Match

Trends of design reuse


Types of IP (Core, VC)▣ Soft: Synthesizable RTL HDL

▣ Firm: {Floor-planning + generic library} or {Placement + target library (no routing)}

▣ Hard: Physical layout

▣ AMS hard: Physical layout + Analog mixed signal specific features

- from VSIA



Issues Relating to IP▣ Standardization of IP Deliverables : A key to mix-and-match

◈ Integration : Interfacing IPs

◈ Verification : Function, performance, fabrication

▣ Marketing◈ IP marketing strategy, media, license, pricing policy

▣ Security ◈ Tradeoff between accessibility and marketability

▣ Management◈ Version control, search, backup and interface between CAD tools

Target is design reuse !!



Organizations for EDA Standardization▣ International organizations

◈ IEC (International Electrotechnical Commission) : www.iec.ch

◈ ISO (International Organization for Standardization) : www.iso.ch

▣ Some regional and national organizations◈ CENELEC(European Committee for Electrotechnical Standardization): www.cenelec.be

◈ ANSI (American National Standards Institute) : www.ansi.org

▣ De facto standard organizations◈ IEEE (Institute of Electrical and Electronics Engineers) : www.ieee.org

◈ EIA (Electronic Industries Association) : www.eia.org

◈ SI2 (Silicon Integration Initiative, formerly CFI) : www.si2.org

◈ ECSI (European CAD Standardization Initiative) : www.ecsi.org

◈ OVI (Open Verilog International) : www.ovi.org

◈ VI (VHDL International) : www.vhdl.org See “www.eda.org” for further info.



Organizations for IPs▣ IP Standard Deliverables

◈ VSI Alliance (www.vsi.org) : Jun. 1996o Establish common standards for large-scale design reuse on silicono Provide an infrastructure for HW implementation by leveraging existing technologies

▣ IP Business & Marketing◈ RAPID (www.rapid.org) : Sep. 1996

o RAPID : Reusable Application-Specific Intellectual Property Developers

o IP market research, legal issues and industry activities

◈ Design and Reuse (www.design-reuse.com) : Oct. 1997, A private company but public o IP yellow pages and IP selector

o IP marketing/sales assistance service

o Tools and services on IP qualification and IP prototyping are scheduled

Define, develop, authorize, test and promote open standard specifications relating to data formats, interfaces, and test methodologies.



VSI Alliance▣ Steering Working Group (SWG)

◈ First specification for VC deliverables : “Architectural Document”, Mar. 1997.

▣ Committees : Pilot (PC), Technical (TC), Marketing (MC)▣ Development Working Groups (DWG): Define details of VC deliverables

◈ System Level Designo “VSIA System Level Design Model Taxonomy Document”, Jan. 1999.

◈ Manufacturing Related Testo “Test Data Interchange Formats and Guidelines for VC Providers”, June 1999.

◈ On-chip Busseso “On-Chip Bus Attributes”, Aug. 1998.

◈ Mixed Signal Designo “Analog/Mixed-Signal VSIA Extension”, June 1998.

◈ Implementation/Verificationo “Soft and Hard VC Structural, Performance and Physical Modeling”, May 1999.

◈ IP Protection◈ Virtual Component Transfer



VSI Alliance (Cont’d)▣ VSI-Compliant Chips - Pilot Committee

◈ Applying VSI standards to actual chip developmento Validation of VC documents

o Promotion of VC documents

◈ Do not discriminate membership in the participation

Milestone of Pilot Project

VSI Spec development

Spec adoption

VSI-compliant chips inproduction

1997 1998 1999



Soft IP Design FlowFrom block integration

DEVELOPspecification

for prototype chip

TRANSLATEVerilog<->VHDL

InterHDL

SYNTHESIZEto multiple

technologiesDesign Compiler

CREATEuser docs

(Datebook)

DESIGN chip

SYNTHSIS chipDesign Compiler

Scan insertion, ATPG, and coverage analysis

Test Compiler

FLOORPLAN

PLACEand ROUTE

VERIFY timing

FABRICATE

TEST chipin demo board

REGRESSIONTEST

translated codeVSS/Verilog/VCS,

ModelSim

RUN TESTSon multiplesimulatiors

RUN gate sim onone technology

VSS/Verilog/VCS,ModelSim

FORMALVERIFICATION

RTL vs. gatesFormality

RELEASE - from RMM



Soft IP Productization Flow

- from Mentor Graphics



Hard IP Productization Flow

GDSII, SPEF, SDF, LEF, SPICE are also needed to describe physical data.- from Mentor Graphics



▣ Introduction



▣ Trends of IP Design

▣ Conclusion


Requirements on IP-Based Design▣ Standardization of IP Deliverables

◈ Data format

◈ Test

◈ Interface

▣ IP Verification

▣ Modeling Guideline for Design Reuse

Requirements on IP-based design


Deliverables of VC - VSIA▣ Behavioural model▣ Emulation model▣ Test sheet▣ Synthesizable RTL HDL model▣ Related Test Bench▣ Gate level net-list▣ Test Vector



Deliverables of VC - VSIA (Cont’d)



Deliverables of VC - VSIA (Cont’d)



Data Formats Relating to VC▣ Standard data formats defined by VSIA

◈ Verilog (IEEE 1364-1995)◈ VHDL (IEEE 1076-1987)◈ EDIF (2 0 0)◈ VC Hspice (1.0) - Avant!

o Structural netlist for transistor level VCo Connectivity between the devices, not including parastics

◈ VC LEF (1.0) - Cadenceo Physical data for hard VCo Interface pins, routing obstructions, power and ground connections

◈ GDSII (6 0 0) - Cadenceo Physical implementation of VCo Used for LVS, DRC, mask generation

◈ SPEF (IEEE P1481, v1.0.4) -SI2o A part of the Delay and Power Calculation System standard from SI2

o SPEF : Standard Parasitics Exchange Format o Detailed parasitics on the interface nets of hard VC



Interfacing IPs▣ PCB ( = Processor + Peripheral) shrinks to SoC

▣ Interface between HW and HW◈ FIFO-based interface: I/O

◈ On-chip bus is required global system specification and design

specification language

exploration&partitioning&architecture selection

software synthesis

interface&communication synthesis

hardware synthesis

co-verification

prototype/real product development

property assessment (performance, cost, power, ...)


Co-design research focus


Interfacing IPs (Cont’d)▣ On-chip bus : System Bus & Peripheral Bus

▣ Candidates for standard on-chip bus◈ ARM (www.arm.com)

o ASB(Advanced System Bus) / APB(Advanced Peripheral Bus)◈ IBM (www.chips.ibm.com)

o PLB(Processor Local Bus) / OPB(On-chip Peripheral Bus) ◈ PALM Chip (www.palmchip.com)

o M Bus / Palm Bus ◈ Mentor Graphics (www.inventra.com)

o FISP Bus◈ OMI (www.omimo.be)

o PI (Peripheral Interconnect) Bus ◈ Fujitsu (www.fujitsu.com)

o Spcl Bus

Hierarchy of on-chip bus (from VSIA)



IP Verification▣ REQUEST (REuse and QUality ESTimation) Project

◈ http://eis.informatik.uni-oldenburg.de

◈ Project Goalso Raise the level of abstraction for modeling as well as the degree of model reusability.

o Improve the quality of VHDL models in terms of readability, reusability, suitability for further design steps (synthesis), testability, simulation efficiency, and confidence in validation.

◈ Partnerso SIDSA (Spain) - Project leader

o Deutsche Telekom AG (Germany)

o France Telecom CNET (France)

o Italtel (Italy)

o Telefonica I+D (Spain)

o LEDA Languages for Design Automation (France)

o Cadence (formerly: Synthesia, Sweden)

o Politecnico di Milano (Italy)

o OFFIS (Germany)



Modeling Guideline▣ VHDL

◈ Is very powerful and flexible

◈ Support algorithm, timing functionality, and physical structure

◈ Provide a lot of freedom in the choice of modeling styles to describe a single thing

▣ Modeling rules are depend on◈ Style of the developer

◈ Modeling culture of the company

▣ Modeling Guideline◈ Standards

◈ De facto standards

◈ Individual experiences

Interoperability may be poor



Modeling Guideline (Cont’d)▣ International standard

◈ IEEE 1076.4, “Standard VITAL ASIC Modeling Specification”o VITAL : VHDL Initiative Towards ASIC Libraries (www.eda.org/vital/)

◈ EIA-567A, “VHDL Hardware Component Modeling and Interface Standard”o EIA : Electronics Industries Alliance (www.eia.org)

▣ De facto standard◈ OMI 326, “VHDL Coding Standard”

o OMI : Open Microprocessor systems Initiative

◈ TIREP, “A VHDL Modeling Guide”o TIREP : Technology Independent Representation of Electronic Products

◈ ESA, “VHDL Modeling Guidelines”o ESA : European Space Agency



Modeling Guideline (Cont’d)▣ Synthesis

◈ IEEE Std 1076.3-1996, “IEEE Standard VHDL Synthesis Packages”

◈ IEEE PAR 1364.1, “Verilog Synthesis Subset”

◈ European VHDL Synthesis Working Group (EVSWG), “Level-0 VHDL Synthesis Syntax and Semantics”

▣ Simulation◈ IEEE Std 1164-1991, “IEEE Standard Logic Package”

◈ IEEE 1076.4, “Standard VITAL ASIC Modeling Specification”

◈ ESA, “VHDL Modeling Guidelines” & “VHDL Models for Board-level Simulation”

▣ Test ◈ IEEE Std 1029.1-1991, “Waveform and Vector Exchange Specification (WAVES)”

▣ Analog modeling◈ IEEE DASC 1076.1, “VHDL-AMS: Analog and Mixed Signal Extensions for VHDL”

▣ Another factors considered previously◈ FSM, protocol, timing, performance, test bench



Modeling Guideline (Cont’d)

Status Intended usage Relation to VHDL

Guidelinesstd

de facto

std

syn-

thesis

simu-

lationtest full subset

exten-

sion

VITAL o o o

EIA-567A o o o

ESA mod. guide o o o

ESA board-level o o o

OMI 326 o o o o o

TIREP o o o

VHDL-AMS o o o

Synth. 1076.3 o o o

WAVES o o o

Std_logic_1164 o o o o



Modeling Guideline for Reuse▣ Needs :

◈ Consistency, Readability, Portability, Interoperability, Synthesizabiliy in RTL Code

▣ Modeling guideline recommended by Synopsys◈ Register all outputs (even inputs if possible)◈ Not latch but flip-Flop ◈ Single edge & single clock◈ Avoid state dependent timing◈ Use synchronous RAM

▣ HDL RTL Coding Rules of Synopsys◈ Naming convention : signal, variable, port name and more◈ Coding for portability◈ Guidelines for clocks and resets◈ Coding for synthesis◈ Designing with memories◈ Code profiling



▣ Introduction



▣ Trends of IP Design(IP Design Tools, IP Verification, IP Security)

▣ Conclusion


IP Design Teamwork

SPECIFY and DOCUMENTfunctional requirements, I/O, timing, performance

area, goals, and test strategyCREATE behavioral model and test cases

DEVELOPmacro

testbench andtest cases

SPECIFYblock function, I/O,timing, test stategy

COORDINATEtiming specs

between blocks

CODE andTEST

SYNTHESIZE

TEST SYNTHESIZE

CHECK AGAINST EXIT CRITERIA

TESTTEAM

DESIGNTEAM

SYNTHESISTEAM

MacroSpecifications,behavioralmodel

Macropartitionsand blockspecifications

Blockdesign

Blockintegration

- from RMM

Trends of IP design


IP Design Tools▣ CoreBuilder & CoreConsultant (Synopsys)

◈ CoreBuilder : IP creation

◈ CoreConsultant : IP reuse

▣ MORE (Measure Of Reuse Excellence) Program - www.synopsys.com

Trends of IP design


IP Verification

- from TransEDA

Trends of IP design


IP Verification (Cont’d)▣ Factors

◈ Modeling Rule Check◈ Easy of simulation / synthesis

◈ HDL Lint◈ Code / FSM Coverage◈ Clock domain analysis ◈ Testability in RT level

SDF

RTL Design(VHDL, Verilog)

Lint

Integration

Synthesis/Timing

FloorplanPlace & Route

FSM Coverage

Code Coverage

Trends of IP design


IP Verification Tools▣ Modeling guideline

◈ ProVHDL(LEDA), ProVerilog(LEDA), Nova-ExplorerRTL(Avant!)

▣ Lint ◈ VHDLint & VeriLint (Avant!)

▣ Code coverage◈ Coverit (Avant!), HDLScore (Summit Design), VHDLCover (TransEDA), CoverMeter

(Synopsys), Nova-ExplorerRTL(Avant!)

▣ Testability◈ Testit (Avant!), DFT Advisor (Synopsys), CoverPlus (TransEDA)

▣ Timing◈ Nova-ExplorerRTL(Avant!)

▣ Power Analysis◈ Coolit (Avant!), PowerSure (TransEDA)

Trends of IP design


- from LEDA

Modeling Guideline Checker▣ ProVHDL

◈ RMM : reuse

◈ OMI 326 : synthesis, simulation, test

◈ IEEE 1076.3 : synthesis

◈ User customization

Trends of IP design


Lint Analysis▣ Goal : Purification of RTL code before synthesis and simulation

▣ Checks◈ Syntax and semantics

◈ Questionable synthesis constructs

◈ Questionable simulation constructs

▣ Reduces design iterations

Trends of IP design


Code Coverage Analysis▣ Goal : Verification of testcases

◈ tightly coupled with a simulator

▣ Captures toggle counts of ◈ signals

◈ variables

◈ execution counts of expressions

◈ conditional branches.

▣ Reports ◈ the switching activity of each testcase

◈ the coverage summary on all testcases

◈ any potential power reduction in the design

Trends of IP design


Testability Analysis▣ Goal : Enhancing the overall testability (Observability & Controllability)

▣ Detects ◈ Design For Test (DFT) rule violations

◈ Questionable testability in RTL code and gate-level netlist

▣ Reports◈ Uncontrollable clock, reset and memory control signals

◈ Recommendations to fix each DFT violation

Trends of IP design


Timing Analysis

Clock domain analysis

Asynchronous loop detection Longest/shortest path analysis

Snake path analysis

Trends of IP design


Power Analysis▣ Goal : Power analysis at RTL

◈ Find and correct problems early using real RTL code, real circuit activity

◈ Explore package alternatives & make decisions early◈ Predict performance with multiple usage models◈ Analyze cooling & mechanical tradeoffs◈ Ensure IP power characteristics match user’s requirements◈ Eliminate wasted power◈ Manage power risk - eliminate re-design

Trends of IP design


IP Security▣ Krypton (www.leda.fr)

▣ CyclopsPro/Gates (www.topdown.com)

▣ Visual IP (www.summit-design.com)

▣ IP Evaluation Kit : Mentor Graphics + GateField + Aptix◈ Mentor Graphics (http://www.inventra.com/inventra)

◈ GateField (www.gatefield.com)

◈ Aptix (www.aptix.com)

Trends of IP design


IP Security (Cont’d)▣ Krypton (www.leda.fr)

◈ Transforms VHDL input into a functionally equivalent modelo Names are scrambled and made unreadable (still ASCII)

o Constant declarations are removed and their values are propagated throughout the code

o All locally static expressions are removed and replaced by their values

o Comments are removed and indentations broken

Trends of IP design


IP Security (Cont’d)▣ CyclopsPro/Gates (www.topdown.com)

◈ Generates cycle-based simulation model from VHDL or Verilog netlists

◈ Accelerates simulation 10 to 50 times

◈ Reduces memory demands 70-80%

Trends of IP design


IP Security (Cont’d)▣ Visual IP (www.summit-design.com)

◈ Generates protected simulation model Run-time licensing required

◈ Can controls internal signal visibility

◈ Back annotation of timing via protected SDF files

◈ Simulators supported :o Model Technology's ModelSim

o Cadence's Leapfrog and Verilog-XL

o Synopsys' VCS and VSS

Trends of IP design


IP Security (Cont’d)▣ IP Evaluation Kit : Mentor Graphics + GateField + Aptix

◈ IP Source : Inventra (Mentor Graphics)

◈ Transportation : Serially numbered IP in a flash-based FPGA (GateField )o Protects reverse-engineering

◈ Evaluation : Plugging those FPGAs into a reconfigurable prototyping system (Aptix)o Verify IPs in the target system through MP4

Configuration of the evaluation using System Explorer, MP4 of Aptix

Trends of IP design


Profiles of IP Providers- from Design and Reuse

Conclusions▣ Design reuse is important concept.

▣ A reusable block or module can be sold as a product.

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