EE 330Lecture 12

Flash Memory Design Issues

Guest Lecture by Ryan Marion of Micron

Note: Ryan is an ISU ECpE graduate, class of 2016, and is a past TA for this course

©2014 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

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Intro to Flash Memory Design

NVE Product Engineering | Micron Technology

Iowa State University

September 21, 2017

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Agenda

o Types of Memory

o Flash Memory Cells

o Program, Erase, Read Operations

o 2D to 3D NAND

o Basic Device Physics

o Technical Issues with 3D NAND

o

o

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Micron’s Core Memory Technologies

September 21, 2017

Volatile Non-Volatile

DRAM NAND

Flash

NOR

Flash

Types of Semiconductor Memory

• Volatile – loses data when power is removed (within milliseconds)

• Non-volatile – retains data when power is removed (for years)

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DRAM

NAND

New Memory Technology

Leading-Edge Technology Status

Images are not to scale

1Xnm DRAM

3D NAND

3D X-point

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Flash Memory Cell

• Single FET with dual gate

• Electrically isolated floating gate is the storage element

• Electrons added to or removed from the floating gate shift the Vt of the cell to store a 1 or a 0

• Two types: NAND and NOR

• NAND – Better array efficiency, lower cost per die for mass-storage

• NOR – Faster read/write speeds for code storage and execution

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NAND vs NOR – Physical Comparison

SourceDrainDrain

Gate

DrainSource

NOR

Parallel layout

NAND

Serial layout

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Basic NAND Flash Operation

• The operation of the NAND Flash cell depends on two basic electrical concepts:

Capacitive division

Fowler-Nordheim tunneling

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Capacitive Division

• If you have capacitors in series, a voltage applied to one node will be distributed across the intermediate nodes

• V2 = V1 * C1 / (C1+C2)

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Fowler-Nordheim Tunneling

• By setting up a large potential difference across an insulator, you can decrease the effective width of the energy barrier, and increase the probability that an electron will tunnel through the insulator.

SemiconductorInsulator

Semiconductor

eee

e

e

eee e

- +

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NAND Flash Operation – Program

• Store a 0 to a cell

Inject electrons onto floating gate through F-N tunneling

Control gate

Floating gate

N+ N+

p-well

N-well

p-sub

Floating 0V

20V

0V 0V

Program ‘0’

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NAND Flash Operation – Erase

• Store a 1 to a cell

Remove electrons from the floating gate through F-N tunneling

Control gate

e- e- e- e- e- e-

N+ N+

p-well

N-well

p-sub

Floating Floating

0V

0V 20V

Erase

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Floating

Gate

Bitline

Rowline

VRead

To read the cell, apply a voltage (VRead) to the rowline

(VT > VRead) => No current, logic ‘0’

(VT < VRead) => Current, logic ‘1’

• By storing electrons on the floating gate, we can change the effective threshold voltage (VT)

• FET conducts current if VGS > VT

NAND Flash Operation – Read

Why is it called “NAND”?

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NAND CMOS Gate Floating Gate Transistor NAND Memory String

Storage Node

A

BC …

A B C

0 0 1

0 1 1

1 0 1

1 1 0

NAND Logic Function

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NAND Read Operation

3V

1V

2V

-3V

-1V

-2

0V

5V

“1”“0”

5V

5V

5V

5V

5V

5V

SGD

SGS

Vcc

WL

WL

WL

WL

WL

WL

1. Precharge bitline and unselected wordlines

3. Sense current

2. Drive selected wordline and connect stringto bitline

The NAND String

• Notice that it has n doping on the source and drain that is repeated across a horizontal plane.

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Moving to 3D NAND – Change to the Channel

• Elimination of Pwell/Atub

• Loss of LDD (Lightly Doped Drain) – Pillar

• Vertical Stacking of Cell’s

• Device Physics Change

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1. With n- LDD (2D)

2. No LDD, P-type channel

3. No LDD, N-type thin channel

n np

n

p

Low Vt-ldd

Low Vt-ldd

High Vt-ldd

Si Substrate

Ch

ann

el \

‘Pillar’

Si Substrate (Pwell/Atub)

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2D vs 3D NAND

TunOx Block Ox

Storage

Channel ControlGate

3D NAND2D NAND

ChannelTunOx

StorageBlock Ox

Control Gate

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What goes into designing a Flash memory chip?• Core memory array

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• Lots of other circuitry:

Sense amplifiers and digital registers to read and store the contents of the memory array

Command and address decoders to select which location to read/write, and which operation to perform

Bandgap reference to generate a voltage reference that is stable across temperature and supply voltage

Charge pumps to generate voltages above or below the supply voltages for the chip

Voltage regulators to regulate the precise voltages required to read/write the array

Thermometer to adjust voltages as needed vs. temperature

DACs and ADCs for converting internal signals between analog and digital domains

Current sources/mirrors to be used for providing reference currents to key circuits throughout the chip

Microcontroller and digital control logic to control the read/write algorithms for the array

I/O drivers for communicating with the outside world

High speed datapath for sending data back and forth between the Chip I/Os and memory array

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Q & A

September 21, 2017

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End of Lecture 12