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EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011

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EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011. Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc. Summary of V a > 0 current density eqns. Ideal diode, J s expd ( V a /( h V t )) ideality factor, h Recombination, J s,rec exp ( V a /(2 h V t )) - PowerPoint PPT Presentation
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EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011 Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc
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Page 1: EE 5340 Semiconductor Device Theory Lecture  17  –  Spring 2011

EE 5340Semiconductor Device TheoryLecture 17 – Spring 2011

Professor Ronald L. [email protected]

http://www.uta.edu/ronc

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Summary of Va > 0 current density eqns.• Ideal diode, Jsexpd(Va/(hVt))

– ideality factor, h• Recombination, Js,recexp(Va/(2hVt))

–appears in parallel with ideal term• High-level injection,

(Js*JKF)1/2exp(Va/(2hVt))–SPICE model by modulating ideal Js

term• Va = Vext - J*A*Rs = Vext - Idiode*Rs

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1N ,V2N

Vt

aexp~

1N ,VN

Vt

aexp~

Vext

ln(J)

data Effect of Rs

2NR ,VNR

Vt

aexp~

VKF

Plot of typical Va > 0 current density equations

Sexta RAJ-VV

KFS JJln

recsJln ,

SJln

KFJln

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)pn( ,ppp and ,nnn wherekT

EfiEcoshn2npnpnU

dtpd

dtndGRU

oo

oTi

2i

For Va < 0 carrierrecombination in DR• The S-R-H rate (no = po = o) is

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Reverse bias (Va<0)=> carrier gen in DR• Consequently U = -ni/20• 0 = mean min. carr. g/r lifetime

NNN/NNN and

qNVV2W where ,2

WqnJ

(const.) U- G where ,qGdxJ

dadaeff

effabi

0igen

x

xgen

n

p

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Reverse bias (Va< 0),carr gen in DR (cont.)

gensagen

abigengens

ra

J or J of largest hetJ set then ,0 V when 0J since :note model SPICE

VVJ where ,JJJ current generation the plus bias negative

for current diode ideal the of value Thecurrent the to components two are there

bias, reverse ,)0V(V for lyConsequent

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Ecrit for reverse breakdown (M&K**)

Taken from p. 198, M&K**

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Reverse biasjunction breakdown• Avalanche breakdown

–Electric field accelerates electrons to sufficient energy to initiate multiplication of impact ionization of valence bonding electrons

–field dependence shown on next slide• Heavily doped narrow junction will

allow tunneling - see Neamen*, p. 274–Zener breakdown

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Reverse biasjunction breakdown• Assume -Va = VR >> Vbi, so Vbi-Va--

>VR

• Since Emax~ 2VR/W = (2qN-VR/())1/2, and VR = BV when Emax = Ecrit (N- is doping of lightly doped side ~ Neff)

BV = (Ecrit )2/(2qN-)

• Remember, this is a 1-dim calculation

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Junction curvatureeffect on breakdown• The field due to a sphere, R, with

charge, Q is Er = Q/(4pr2) for (r > R)

• V(R) = Q/(4pR), (V at the surface)• So, for constant potential, V, the

field, Er(R) = V/R (E field at surface increases for smaller spheres)

Note: corners of a jctn of depth xj are like 1/8 spheres of radius ~ xj

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BV for reverse breakdown (M&K**)

Taken from Figure 4.13, p. 198, M&K**Breakdown voltage of a one-sided, plan, silicon step junction showing the effect of junction curvature.4,5

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Diode equivalentcircuit (small sig)

ID

VDVQ

IQ

tQ

dd

VDD

VI

r1gdV

dI

Qh

h is the practical

“ideality factor”

Qt

difft

Qdiffusion

mintrdd

IVr , V

IC

long) for short, for ( , Crh

h

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Small-signal eqcircuit

Cdiff Cdep

l

rdiff

Cdiff and Cdepl are both charged by

Va = VQQabi

ajojdepl VV

VVCCC

,12/1

Va

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Diode Switching• Consider the charging and

discharging of a Pn diode – (Na > Nd)– Wn << Lp– For t < 0, apply the Thevenin pair VF

and RF, so that in steady state • IF = (VF - Va)/RF, VF >> Va , so current

source– For t > 0, apply VR and RR

• IR = (VR + Va)/RR, VR >> Va, so current source

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Diode switching(cont.)

+

+ VF

VR

DRR

RF

SwR: t >

0

F: t < 0

ItI s

FF

F RVI0tI

VF,VR >> Va

FF

FaF

Q RV

RVVI

0,t for

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Diode chargefor t < 0

xn xncx

pn

pno

DpWA

IWVxqpQ

NTR

TRFnFnndiffp

2

,,'

2

,

D

2ino

V/VnoFn N

np ,epV,xp tF

dxdpqDJ since ,qAD

Idxdp

ppp

F

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Diode charge fort >>> 0 (long times)

xn xncx

pn

pno

tF V/Vnon ep0t,xp

t,xp

sppp

S JdxdpqDJ since ,qAD

Idxdp

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Equationsummary

Q discharge to flowsR/VI current, a 0, but small, t For

RVI ,qAD

Idxdp

AJI ,AqDI

JqD1

dxdp

RRR

FF

Fp

F0t,F

ssp

s

,ppt,R

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Snapshot for tbarely > 0

xn xncx

pn

pno

pF

qADI

dxdp

pR

qADI

dxdp

tF V/Vnon ep0t,xp 0t,xp Total charge

removed, Qdis=IRt st,xp

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I(t) for diodeswitching

ID

t

IF

-IR

ts ts+trr

- 0.1 IR

sRdischargep

Rs

tIQ

constant, a is qADI

dxdp ,tt 0 For

pnpp2

is L/WtanhLD

qnI

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Ideal diode equation for EgN = EgN

Js = Js,p + Js,n = hole curr + ele currJs,p = qni

2Dp coth(Wn/Lp)/(NdLp), [cath.] = qni

2Dp/(NdWn), Wn << Lp, “short” = qni

2Dp/(NdLp), Wn >> Lp, “long”Js,n = qni

2Dn coth(Wp/Ln)/(NaLn), [anode] = qni

2Dn/(NaWp), Wp << Ln, “short” = qni

2Dn/(NaLn), Wp >> Ln, “long”Js,n<<Js,p when Na>>Nd , Wn & Wp cnr wdth

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Ideal diode equationfor heterojunction

• Js = Js,p + Js,n = hole curr + ele currJs,p = qniN

2Dp/[NdLptanh(WN/Lp)], [cath.] = qniN

2Dp/[NdWN], WN << Lp, “short” = qniN

2Dp/(NdLp), WN >> Lp, “long”Js,n = qniP

2Dn/[NaLntanh(WP/Ln)], [anode] = qniP

2Dn/(NaWp), Wp << Ln, “short” = qniP

2Dn/(NaLn), Wp >> Ln, “long”

Js,p/Js,n ~ niN2/niP

2 ~ exp[[EgP-EgN]/kT]

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Bipolar junctiontransistor (BJT)• The BJT is a “Si

sandwich” Pnp (P=p+,p=p-) or Npn (N=n+, n=n-)

• BJT action: npn Forward Active when VBE > 0 and VBC < 0

P n p

E B C

VEB VCB

Charge neutral Region

Depletion Region

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npn BJT topology

Charge Neutral Region

Depletion Region

xx’

p-Base n-CollectorN-Emitter

z0 WB WB+W

C

-WE

0 x”c

x”0 x

B

0x’E

IE IC

IB

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BJT boundary andinjection cond (npn)

0p

p , VVfexppp

0p

p , VVfexppp

C

C

2i

E

E

2i

x"xnC

Nn

0nCtBC0nC0"xnC

x'xnE

Nn

0nEtBE0nE0'xnE

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BJT boundary andinjection cond (npn)

. V

Vfexpnn

n , VVfexpnn

dependent-inter are BC Base the that Note

tBC0pBxBxpB

Nn

0pBtBE0pB0xpB B

2i

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IC npn BJT(*Fig 9.2a)

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References* Semiconductor Physics and

Devices, 2nd ed., by Neamen, Irwin, Boston, 1997.

**Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986.

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References* Semiconductor Physics and

Devices, 2nd ed., by Neamen, Irwin, Boston, 1997.

**Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986.


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