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EE1411
© Digital Integrated Circuits2nd Wires
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
The WireThe Wire
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
July 30, 2002
EE1412
© Digital Integrated Circuits2nd Wires
The WireThe Wire
transmitters receivers
schematics physical
EE1413
© Digital Integrated Circuits2nd Wires
Interconnect Impact on ChipInterconnect Impact on Chip
EE1414
© Digital Integrated Circuits2nd Wires
Wire ModelsWire Models
All-inclusive model Capacitance-only
EE1415
© Digital Integrated Circuits2nd Wires
Impact of Interconnect ParasiticsImpact of Interconnect Parasitics
Interconnect parasitics reduce reliability affect performance and power
consumption Classes of parasitics
Capacitive Resistive Inductive
EE1416
© Digital Integrated Circuits2nd Wires
10 100 1,000 10,000 100,000
Length (u)
No
of
ne
ts(L
og
Sc
ale
)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Nature of InterconnectNature of Interconnect
Local Interconnect
Global Interconnect
SLocal = STechnology
SGlobal = SDie
So
urc
e:
Inte
l
EE1418
© Digital Integrated Circuits2nd Wires
Capacitance of Wire InterconnectCapacitance of Wire Interconnect
VDD VDD
VinVout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CL
SimplifiedModel
EE1419
© Digital Integrated Circuits2nd Wires
Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model
Dielectric
Substrate
L
W
H
tdi
Electrical-field lines
Current flow
WLt
cdi
diint
LLCwire SSS
SS
1
EE14111
© Digital Integrated Circuits2nd Wires
Fringing CapacitanceFringing Capacitance
W - H/2H
+
(a)
(b)
EE14112
© Digital Integrated Circuits2nd Wires
Fringing versus Parallel PlateFringing versus Parallel Plate
(from [Bakoglu89])
EE14113
© Digital Integrated Circuits2nd Wires
Interwire CapacitanceInterwire Capacitance
fringing parallel
EE14114
© Digital Integrated Circuits2nd Wires
Impact of Interwire CapacitanceImpact of Interwire Capacitance
(from [Bakoglu89])
EE14115
© Digital Integrated Circuits2nd Wires
Wiring Capacitances (0.25 Wiring Capacitances (0.25 m CMOS)m CMOS)
EE14117
© Digital Integrated Circuits2nd Wires
Wire Resistance Wire Resistance
W
L
H
R = H W
L
Sheet ResistanceRo
R1 R2
EE14119
© Digital Integrated Circuits2nd Wires
Dealing with ResistanceDealing with Resistance
Selective Technology Scaling Use Better Interconnect Materials
reduce average wire-length e.g. copper, silicides
More Interconnect Layers reduce average wire-length
EE14120
© Digital Integrated Circuits2nd Wires
Polycide Gate MOSFETPolycide Gate MOSFET
n+n+
SiO2
PolySilicon
Silicide
p
Silicides: WSi 2, TiSi2, PtSi2 and TaSi
Conductivity: 8-10 times better than Poly
EE14123
© Digital Integrated Circuits2nd Wires
Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process
5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric
EE14126
© Digital Integrated Circuits2nd Wires
The Lumped ModelThe Lumped Model
Vout
Driver
cwire
VinClum pe d
RdriverVout
EE14127
© Digital Integrated Circuits2nd Wires
The Lumped RC-ModelThe Lumped RC-ModelThe Elmore DelayThe Elmore Delay
EE14129
© Digital Integrated Circuits2nd Wires
Wire ModelWire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
EE14131
© Digital Integrated Circuits2nd Wires
Step-response of RC wire as a Step-response of RC wire as a function of time and spacefunction of time and space
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (V
)
x= L/10
x = L/4
x = L/2
x= L
EE14133
© Digital Integrated Circuits2nd Wires
Driving an RC-lineDriving an RC-line
Vi n
Rs Vo ut
(rw,cw,L)
EE14134
© Digital Integrated Circuits2nd Wires
Design Rules of ThumbDesign Rules of Thumb
rc delays should only be considered when tpRC >> tpgate of the driving gate
Lcrit >> tpgate/0.38rc rc delays should only be considered when the
rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line
trise < RC when not met, the change in the signal is slower
than the propagation delay of the wire
© MJIrwin, PSU, 2000