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EE241 Spring 2008EE241 - Spring 2008Advanced Digital Integrated Circuits

TuTh 3:30-5pm293 Cory

Practical InformationInstructor:

Borivoje Nikolić550B C H ll 3 9297 b @550B Cory Hall , 3-9297, bora@eecsOffice hours: M 10:30am-12pm

Reader: Kenneth Duongkeduong@eecs

Admin: Rosita Alvarez-Croft

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253 Cory Hall, 3-4976, rosita@eecs

Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s08

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Class TopicsThis course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies components in state of the art MOS technologies.

Emphasis is on the circuit design, and optimization for both high performance high speed and low power for use in applications such as microprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of

li d b i ff t i bilit i t t i l

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scaling, deep sub-micron effects, variability, interconnect, signal integrity, power distribution and consumption, and timing.

EECS141 vs. EECS241EECS 141:

Basic transistor and circuit modelsBasic circuit design stylesBasic circuit design stylesFirst experiences with design – creating a solution given a number of specs

EECS 241:Transistor models of varying accuracyDesign under constraints: power-constrained, flexible, robust,…

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g pLearning more advanced techniques Study the challenges facing design in the coming yearsCreating new solutions to challenging design problems

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EECS141 vs. EECS241EECS141

0.25μm CMOSUnified transistor model

EECS241Mostly 45nm CMOSDifferent modelsUnified transistor model

Basic circuit design techniquesWell defined design projectCadence/Hspice Focus on principles

Different modelsAdvanced circuit techniquesOpen design/research projectAny tool that does the jobFocus on principles

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Special Focus in Spring 2007

Current technology issuesPower and performance optimizationPower and performance optimizationProcess variationsRobust designSRAM

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Timing strategies

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Class TopicsFundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks) Introduction to variability: SRAM example (2.5 weeks)

Sources of variability, modeling SRAM in scaled technologies

Power-performance tradeoffs in design (4 weeks)Design for deep-submicron CMOSStatic CMOS, high-speed CMOS design styles, dynamic logic analysis of power consumption sources Power performance tradeoffs at the technology circuit and architecture level

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Power-performance tradeoffs at the technology, circuit, and architecture levelArithmetic circuits – adders, multipliers (2 weeks) Driving interconnect, high-speed signaling (1 week) Timing (2 weeks)

Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed design, clock generation and distribution, phase-locked loops

Class Organization5 (+/-) assignments1 term-long design project

Phase 1: Proposal (week after ISSCC)Phase 2: Study (report by week 8)Phase 3: Design (presentation and report by final week)Report and presentations last week of classes

Final exam (Monday 12, in-class)

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( y )

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Class MaterialBaseline: “Digital Integrated Circuits - A Design Perspective”, 2nd ed. by J. M. Rabaey, A. Chandrakasan B NikolićChandrakasan, B. NikolićOther reference books:

“Design of High-Performance Microprocessor Circuits,” edited by A. Chandrakasan, W. Bowhill, F. Fox“Low-Power Electronics Design,” C. Piguet, Ed.“CMOS VLSI Design,” 3rd ed, N.Weste, D. Harris“Analysis and Design of Digital ICs,” 3rd ed, D.A. Hodges, H.G. Jackson,

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y g g , , g , ,R.A. Saleh“High-Speed CMOS Design Styles, by K. Bernstein, et al.“Leakage in Nanometer CMOS Technologies,” by Narendra and Chandrakasan, Ed.“Digital Systems Engineering” by W. Dally

Class MaterialList of background material available on web-siteSelected papers will be made available on web-site

Linked from IEEE Xplore and other resourcesNeed to be on campus to access, or use library proxy, library VPN (check http://library.berkeley.edu)

Class-notes on web-site

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SourcesIEEE Journal of Solid-State Circuits (JSSC)IEEE International Solid-State Circuits Conference (ISSCC)Symposium on VLSI Circuits (VLSI)Other conferences and journals

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Project TopicsVariability studiesRobust designPower-performance tradeoffsLeakage suppressionSRAM design

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Tools

HSPICEYou need an account on cory eecsYou need an account on cory.eecs

Predictive sub-100nm models (former BPTM)http://www.eas.asu.edu/~ptm/

0.18 /0.13/0.09 μm CMOS device modelsOther tools, schematic or layout editors are optional

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Cadence, Synopsys, available on quasar.eecsMore information on the web-site.

EE241 Spring 2007EE241 - Spring 2007Advanced Digital Integrated Circuits

Lecture 1: IntroductionTrends and Challenges in Trends and Challenges in

Digital Integrated Circuit Design

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Suggested ReadingInternational Technology Roadmap (http://public.itrs.net) Chandrakasan, Bowhill, Fox, Chapter 1 – Impact of physical technology on architecture (J.H. Edmondson),Ch d k B hill F Ch t 2 CMOS li d i i Chandrakasan, Bowhill, Fox, Chapter 2 – CMOS scaling and issues in sub-0.25μm systems (Y. Taur)Baseline: Rabaey et al, Chapter 3.Selected papers from the web:

G.E. Moore, No exponential is forever: but "Forever" can be delayed! Proc. ISSCC’03, Feb 2003. T.-C. Chen, Where CMOS is going: trendy hype vs. real technology. Proc. ISSCC’06, Feb 2006.

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S. Chou, Innovation and Integration in the Nanoelectronics Era, Proc. ISSCC’05, Feb. 2005.S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.

The contributions to this lecture by a number of people (J. Rabaey, P. Gelsinger, S, Borkar, etc) are greatly appreciated.

Semiconductor Industry Revenues

16M. Chang, “Foundry Future: Challenges in the 21st Century,” ISSCC’2007

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Moore’s Law

In 1965, Gordon Moore noted that the number of t i t hi d bl d 12 thtransistors on a chip doubled every 12 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue if not to increase Over the longer term the rate of increase is a bit more

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continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”Gordon Moore, Cramming more Components onto Integrated Circuits, (1965).

Moore’s Law - 1965““Reduced cost is one of the big Reduced cost is one of the big attractions of integrated attractions of integrated electronics, and the cost electronics, and the cost advantage continues to increaseadvantage continues to increase

TransistorsTransistorsPer DiePer Die

101099

10101010

advantage continues to increase advantage continues to increase as the technology evolves as the technology evolves toward the production of larger toward the production of larger and larger circuit functions on a and larger circuit functions on a single semiconductor substrate.”single semiconductor substrate.”Electronics, Volume 38, Electronics, Volume 38, Number 8, April 19, 1965Number 8, April 19, 1965

101088

101077

101066

101055

101044

101033

1819601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

1010

101022

101011

101000

Source: IntelSource: Intel

1965 Data (Moore)1965 Data (Moore)

Graph from S.Chou, ISSCC’2005

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Moore’s Law - 2005TransistorsTransistors

Per DiePer Die

101099

10101010

256M256M512M512M

1G1G 2G2G

80808080 808680868028680286

386™ Processor386™ Processor486™ Processor486™ Processor

PentiumPentium® ® ProcessorProcessorPentiumPentium® ® II ProcessorII Processor

PentiumPentium®® III ProcessorIII ProcessorPentiumPentium®® 4 Processor4 Processor

ItaniumItanium™ ™ ProcessorProcessor101088

101077

101066

101055

101044

10103380088008

ItaniumItanium™ ™ 22 ProcessorProcessor

1K1K4K4K

64K64K256K256K

1M1M

16M16M4M4M

64M64M256M256M

128M128M

16K16K

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400440041010

101022

101011

101000

800880081965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessorMemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

Source: IntelSource: IntelGraph from S.Chou, ISSCC’2005

Moore’s law and cost

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Progress in Nano-TechnologyMillipede

Spintronic device

Molecular Electronics

Spintronic Storage

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Silicon Nanowires

Nanomechanics

T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

Technology Strategy / Roadmap 2000 2005 2010 2015 2020 2025 2030

Plan A: Extending Si CMOSPlan A: Extending Si CMOS

Plan B: Subsytem IntegrationPlan B: Subsytem Integration

R D

R D

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Plan C: Post Si CMOS Options Plan C: Post Si CMOS Options

R R&D

Plan Q:Plan Q:

R D

Quantum ComputingQuantum Computing

T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

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Technology EvolutionInternational Technology Roadmap for Semiconductors - 2003 data

Year 2004 2007 2010 2013 2016D ½ it h [ ] 90 65 45 32 22Dram ½ pitch [nm] 90 65 45 32 22

MPU transistors/chip 550M 1100M 2200M 4400M 8800MWiring levels 10-14 11-15 12-16 12-16 14-18

High-perf. physical gate [nm] 37 25 18 13 9High-perf. VDD [V] 1.2 1.1 1.0 0.9 0.8Local clock [GHz] 4.2 9.3 15 23 40

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High-perf. power [W] 160 190 220 250 288Cost-perf. power [W] 84 104 120 138 158Low-power VDD [V] 0.9 0.8 0.7 0.6 0.5

‘Low-power’ power [W] 2.2 2.5 2.8 3.0 3.0

ITRS Acceleration Continues

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Printed vs. Physical Gate

25ITRS’2003

Printed vs. Physical Gate10000100001010

Nominal feature sizeNominal feature size

MicronMicron

10001000

100100

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0.10.1

NanoNano--metermeter

130nm130nm

90nm90nmGate LengthGate Length 65nm65nm

45nm45nm32nm32nm

0.7X every 2 years

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10100.010.01

NanotechnologyNanotechnology(< 100nm)(< 100nm)

70nm70nm50nm50nm

35nm35nm

19701970 19801980 19901990 20002000 20102010 20202020

32nm32nm22nm22nm

25nm25nm18nm18nm

12nm12nm

Source: IntelGraph from S.Chou, ISSCC’2005

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Some Recent DevicesIn production:65nm strained Si

In research:10nm device

L = 10 nmg

C d t

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Corresponds tosub-22nm node(>10 years)

Some Recent Devices

Intel’s 30nm transistor, circa 2002

Ion = 570μm/μmIoff = 60nA/ μm

28[B. Doyle, Intel]

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More Recent Devices

Intel’s 20nm transistor, circa 2002

29[B. Doyle, Intel]

@0.75V

More Recent Devices

SOI: Silicon-on-InsulatorUltra-Thin-Body (UTB) MOSFET

SOI: Silicon-on-Insulator

30[Choi, UCB]

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18nm FinFET

Double-gate structure + raised source/drain

BOX Si fin - Body!

DrainSource

GateGate

Silicon Fin

150200250300350400

I d[u

A/u

m]

-1.50 V

-1.00 V

-0.75 V

-1.25 V

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Si fin Body!

X. Huang, et al, 1999 IEDM, p.67~70

050

100150

-1.5 -1.0 -0.5 0.0Vd [V]

-0.50 V

-0.25 V

Sub-5nm FinFET

32Lee, VLSI Technology, 2006

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Major Roadblocks1. Managing complexity

How to design a 10 billion transistor chip?And what to use all these transistors for?And what to use all these transistors for?

2. Cost of integrated circuits is increasingIt takes >$10M to design a chipMask costs are more than $3M in 45nm technology

3. The end of frequency scaling - Power as a limiting factor

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factorDealing with leakages

4. Robustness issuesVariations, SRAM, soft errors, coupling

5. The interconnect problem

Next LectureImpact of technology scalingCharacteristics of sub-100nm technologies

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