EE241 - Spring...

EE241

1

UC Berkeley EE241 J. Rabaey, B. Nikolić

EE241 - Spring 2003Advanced Digital Integrated Circuits

Lecture 28Self-Test and Flash Memory

Based on a talk by Ken Takeuchi, Toshiba


Project ReportsShould be in paper format – max of 5 pages! Title of the project/ your names and e-mail addresses! Abstract (100 words)! Motivation! Problem statement! Possible solutions from literature (from midterm report)! Proposed comparison/solution. Discuss why did you select this

particular one.! Conditions/assumptions of your design! Analysis: Does it work? Analytical analysis, simulation results.! Conclusion. What is this approach good for? What else could

be done?! References! Due on May 8, at 5pm (on the web)

EE241

2


Self-test

(Sub)-Circuit

Under

Test

Stimulus Generator Response Analyzer

Test Controller

Rapidly becoming more important with increasingchip-complexity and larger modules


Linear-Feedback Shift Register (LFSR)

S0 S1 S2

R R R

1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0

Pseudo-Random Pattern Generator

EE241

3


Signature Analysis

R

Counter

In

Counts transitions on single-bit stream≡≡≡≡ Compression in time


BILBO

S0

R R R

S1 S2

ScanOutScanIn mux

D2D1D0B0

B1

Operation modeB0

Normal

Scan

Signature analysis

1 1

0 0

1 0 Pattern generation or

0 1 Reset

B1

EE241

4


BILBO Application

Logic

Combinational

Logic

Combinational

BIL

BO

-B

BIL

BO

-A OutIn

ScanIn ScanOut


Memory Self-Test

FSMMemory Signature

AnalysisUnder Test

data

address &

R/W control

-in

data-out

Patterns: Writing/Reading 0s, 1s,Walking 0s, 1sGalloping 0s, 1s

EE241

5


Boundary Scan (JTAG)Printed-circuit board

Logic

scan path

normalinterconnect

Packaged IC

Bonding Pad

Scan-in

Scan-out

si so

Board testing becomes as problematic as chip testing


Testing on-chip Logic

EE241

6


Testing Mixed Analog-Digital ICs


Self-test

(Sub)-Circuit

Under

Test

Stimulus Generator Response Analyzer

Test Controller

Rapidly becoming more important with increasingchip-complexity and larger modules

EE241

7


Linear-Feedback Shift Register (LFSR)

S0 S1 S2

R R R

1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0

Pseudo-Random Pattern Generator


Signature Analysis

R

Counter

In

Counts transitions on single-bit stream≡≡≡≡ Compression in time

EE241

8


BILBO

S0

R R R

S1 S2

ScanOutScanIn mux

D2D1D0B0

B1

Operation modeB0

Normal

Scan

Signature analysis

1 1

0 0

1 0 Pattern generation or

0 1 Reset

B1


BILBO Application

Logic

Combinational

Logic

Combinational

BIL

BO

-B

BIL

BO

-A OutIn

ScanIn ScanOut

EE241

9


Built-In Self-Test


Memory Self-Test

FSMMemory Signature

AnalysisUnder Test

data

address &

R/W control

-in

data-out

Patterns: Writing/Reading 0s, 1s,Walking 0s, 1sGalloping 0s, 1s

EE241

10


Boundary Scan (JTAG)Printed-circuit board

Logic

scan path

normalinterconnect

Packaged IC

Bonding Pad

Scan-in

Scan-out

si so

Board testing becomes as problematic as chip testing


Testing on-chip Logic

EE241

11


Testing Mixed Analog-Digital ICs

9/19/02 22

Embedded SoftwareEmbedded Software--Based SelfBased Self--Testing forTesting forProgrammable System ChipsProgrammable System Chips

BusInterface Master Wrapper

BusArbiter

Low-CostTester

On-ChipMemory

Testprogram

Responses

VCISignatures

DSP

VCI

IP CoreVCI

System MemoryVCI

On-chip Bus

BusInterfaceMaster Wrapper

BusInterface Target WrapperBusInterface Target Wrapper

Loading testprogram atlow speed

Self-test atoperational

speed

Unloadingresponse

signature atlow speed

"" LowLow--cost testercost tester"" HighHigh--quality atquality at--speed testspeed test"" Low test overheadLow test overhead"" NonNon--intrusiveintrusive

Test in normal operational modeTest in normal operational mode"" No violation of power consumptionNo violation of power consumption"" More accurate speedMore accurate speed--binningbinning

CPU

EE241

12


EE241 - Spring 2003Advanced Digital Integrated Circuits

Lecture 28Flash Memory

Based on a talk by Ken Takeuchi, Toshiba


Semiconductor Memory Trends(up to the 90’s)

Memory Size as a function of time: x 4 every three years

EE241

13


Semiconductor Memory Trends(updated)

From [Itoh01]


Trends in Memory Cell Area

From [Itoh01]

EE241

14


Some new(?) kids on the block! FRAM (Ferroelectric RAM): Use a

“programmable capacitor” (made ofPerovskite crystals).» During write, capacitor is polarized» During read, an electrical field is applied and

current is measured

! MRAM (Magnetoresistive RAM): usemagnetic charges in contrast to electricalcharges – very similar to old core memories» Magneto-resistive material changes resistivity

when placed in a magnetic field


Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n� source n� drainprogramming

Many other options …

EE241

15


Cross-sections of NVM cells

EPROMFlashCourtesy Intel


Basic Operations in a NOR Flash Memory―Erase

S D

12 VG

cell arrayBL0 BL1

open open

WL0

WL1

0 V

0 V

12 V

EE241

16


Basic Operations in a NOR Flash Memory―Write

S D

12 V

6 VG

BL0 BL1

6 V 0 V

WL0

WL1

12 V

0 V

0 V


Basic Operations in a NOR Flash Memory―Read

5 V

1 VG

S D

BL0 BL1

1 V 0 V

WL0

WL1

5 V

0 V

0 V

EE241

17


History of Flash Memories

�84 �85 �86 �87 ��91 �92 �93 …PRESENT

SanDisk-type

DiNOR-type

SanDisk-type

NOR-type

NAND-type

DiNOR-type

AND-type

SST-typeX

SST-type

X

File-Storage

Code-Storage

NOR-type

NAND-type

ACEE-type

AND-type

Split-gate-type

FLASHMEMORYInvention


Flash Memory Comparison - Code vs File Storage -

Code Storage

File Storage

Applications Type of Flash memoryPerformance

Program storage for- Cellular Phone- DVD- Set TOP Box

BIOS for- PC and peripherals

Small form factor card for- Digital Still Camera- Silicon Audio- PDA ... etc

Mass storage as- Silicon Disk Drive

Important :

Acceptable :

• High speed random access

• Byte programming

• Slow programming

• Slow erasing

• High speed programming

• High speed erasing

• High speed serial read

• Slow random access

Important :

Acceptable :

NOR• Intel / Sharp• AMD / Fujitsu / Toshiba

DINOR• Mitsubishi

NAND• Toshiba / Samsung

AND• Hitachi

•SanDisk: NOR

EE241

18


Requirements for File Storage Memory

! Low Bit Cost <$1/MByte! High Density >32MByte! High Speed Programming >2MByte/sec

and Erasing <3msec/block! High Speed Serial Read! Low Power Consumption! Good Program/Erase Endurance >1 million

cycles


Device Technologies

! Low Bit Cost <$1/MByte! High Density >32MByte! High Speed Programming

>2MByte/secand Erasing <3msec/block

! High Speed Serial Read! Low Power Consumption! Good Program/Erase Endurance

>1 million cycles

NAND Cell w.Self-Aligned STI

Uniform FN-FNProgram/Erase

EE241

19


Cell Array Comparison

Simplest wiringSmallest area

NOR SanDisk AND NAND

Erase gate(poly)

Unit Cell Unit Cell

Word line(poly) Word line(poly)

Source line(Diff. Layer)

Word line(poly)

Bit line(metal)


Unit Cell

Contact


Word line(poly)

Bit line /Source line(metal)

Unit Cell

Sub Bit line(Diff. Layer)

9F2 8F2 4F210F2


Word linesSelect transistor

Bit line contact Source line contact

Active area

STI

NAND Cell Array (Top view)

EE241

20


NAND Cell Array (Cross sectional view)

Word line

Word line

Bit line

Select gate

A A’

A A’

Source line


Cell Size Shrink by Self-Aligned STI(Shallow Trench Isolation)

Current

��

3� Floating Gate

Word Line

LOCOS_NAND : 6F2+�LOCOS_NAND : 6F2+�

��

��

STI_NAND : 4F2+�STI_NAND : 4F2+�

�F�F

EE241

21


NAND Cell Array (Cross sectional view)

Word line

Word line

STI

1st floating gate

2nd floating gate

B B’

B B’

Si


+ Multi Level Cell

Floating Gate

LOCOS

Control Gate

3.5F

3F

2F

3F

NAND-type Cell(Contactless)

2F

2F

Self-AlignedSTI Cell

2F

2F

Self-Aligned STI Cell

Floating Gate

STI

Control Gate

Cell Size 10-11F2 6-7F2 4-5F2 2-2.5F2

Isolation LOCOS LOCOS SA-STI SA-STI

NOR-type Cell

NAND Cell Trend

EE241

22


NAND Flash Cell Size Trend

Start of Mass Production

Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan-‘93 ‘94 ‘95 ‘96 ‘97 ‘98 ‘99 ‘00 ‘01 ‘02 ‘03 ‘04

0.1

10

Cel

lSiz

e(

um2

)

1

LOCOS SA-STI

MLC

0.01

Multi Level Cell

Floating Gate

LOCOSTunnel Oxide

Control GateWSiONO

Control Gate ONOFloatingGate

TunnelOxide STI

WSi

SA-STI

0.25um

0.175um

0.13um0.10um


Program / Erase Method

Electron Injection (Program)

-Page program - Byte program

Hot Electron

Program Current< 2-5mA

S D

VD

Vpp

Channel-FNtunneling

Program Current< 1uA

Vpp

Electron Emission (Erase)

- High SpeedErase

( 3ms/Block )

High VPE( 20v )

VPE

Channel-FNtunneling

- Low SpeedErase

(1s /Block)

LowVPE( 12v )

S D

VPE

Edge-FNtunneling

- High SpeedErase

(3ms/Block)

HighVPE( 20v )

S D

Poly-FNtunneling

VPE

EE241

23


Cell Function

FN tunnelingEdge-FN tunnelingHot Electron

NOR SANDISK AND

PROG.

ERASE

Prog. Speed

Vth

0V

20V

20V 20V

0V0V

18V

0V

-8V

6V

0V

Open

10V

-8V

-8V -8V

10V

0V

0V 7V

0V

0V

22V

12V

5V

0V

Open

0V

F

0V

12V

0.1MB/sec 0.5MB/sec

FN tunneling FN tunnelingPoly-FN tunnelingEdge-FN tunneling

Hot Electron

Vth(V)

Number

Vth(V)

Number

Vcc

Vth(V)

Number

Vcc

Vth(V)

Number

Vcc

0

0 0

0

Access Mode

2.0MB/secVery Fast2.5MB/sec

Random Serial Serial Serial

NAND


Writing Flash Memory

Num

ber

of m

emor

y ce

lls

0V 1V 2V

Vt of memory cells

Verify level � 0.8 V Word-line level � 4.5 V

3V 4V

Result of 4 timesprogram

R e ad le v el (4.5 V)

N u mb er of ce lls

100

0V 1V 2V

Vt of memory cells

3V 4V

102

104

106

108

Evolution of thresholds Final Distribution

From [Nakamura02]

EE241

24


1 Gbit Flash Memory

Sense Latches(1024 � 32) � 8

Data Caches(1024 � 32) � 8

Sense Latches(1024 � 32) � 8

Data Caches(1024 � 32) � 8

Wor

d L

ine

Dri

ver

Wor

d L

ine

Dri

ver

Wor

d L

ine

Dri

ver

Wor

d L

ine

Dri

ver

512Mb Memory Array 512Mb Memory Array

BL0 BL1 ····· BL16895 BL16996 BL16897 ··· BL33791

SGDWL31

WL0SGS

Block0

BLT0

Block1023

Block0

Block1023

Bit Line Control CircuitBLT1

I/OI/O

From [Nakamura02]


125mm2 1Gbit NAND Flash Memory

10.7

mm

11.7mm

2kB

Pag

ebu

ffer

&ca

che

Cha

rge

pum

p

16896 bit lines

32 word linesx 1024 blocks

EE241

25


125mm2 1Gbit NAND FlashMemory

! Technology 0.13µµµµm p-sub CMOS triple-well1poly, 1polycide, 1W, 2Al

! Cell size 0.077µµµµm2! Chip size 125.2mm2! Organization 2112 x 8b x 64 page x 1k block! Power supply 2.7V-3.6V! Cycle time 50ns! Read time 25µµµµs! Program time 200µµµµs / page! Erase time 2ms / block

! Technology 0.13µµµµm p-sub CMOS triple-well1poly, 1polycide, 1W, 2Al

! Cell size 0.077µµµµm2! Chip size 125.2mm2! Organization 2112 x 8b x 64 page x 1k block! Power supply 2.7V-3.6V! Cycle time 50ns! Read time 25µµµµs! Program time 200µµµµs / page! Erase time 2ms / block

From [Nakamura02]


That’s all Folks

Thanks for the fun semester.See you next Thursday and Friday

Date post:	01-Oct-2020
Category:	Documents
Upload:	others
View:	1 times
Download:	0 times

EE241 - Spring...

Documents