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Abstract — As SRAM scales to smaller technology nodes, there is an increasing need for high on-current, low leakage, and variation resistant transistors. A new advancement in sub-32nm technology is the tri-gate FET or FinFET, which provides effective performance, but is limited by quantized device widths, a concern for 6T SRAM design. In this work, we analyze the dynamic margins of both unassisted and assisted 6T FinFET-based 1kbit SRAM cell array. Using 32nm transistor models from BSIM-CMG, we successfully mitigated the drawbacks caused by quantized device sizing. For a read stable cell, the write time was reduced by up to 39.3%, and for a write stable cell, the read time was reduced by 10% - all without significantly affecting the stability of half-selected cells.

Index Terms—Tri-gate transistors, SRAM stability, dynamic margin, assist techniques, variability.

I. INTRODUCTION

EDUCTION of supply voltage (VDD) has enabled continued scaling of embedded SRAM over the past few decades.

However, further VDD scaling for SRAM has been limited by increased gate leakage, degraded ION/IOFF ratio, and the random dopant fluctuation (RDF). Recent advancements such as strained silicon technology, high-K gate dielectric, and metal gate electrodes to suppress these effects have been effective, but a more drastic measure is required for sub-32nm technology scaling. One attractive option is the tri-gate FET, or FinFET [1]. Because the channel is controlled by the gate from multiple sides, short-channel effects such as drain-induced barrier lowering threshold voltage roll-off and off-state leakage current are improved. In addition, lightly-doped channel reduces effects of random dopant fluctuations on the threshold voltage.

Circuit design using FinFET presents a new challenge due to quantized transistor widths. This discrete width sizing is shown in Fig. 1, which demonstrates Intel’s latest implementation of SRAM cell array in 22nm technology [2]. This constraint significantly affects SRAM operation because optimal stability margins of a 6T cell are achieved with pull-down and pull-up transistor ratio between 1 and 2. However, using FinFETs, the quantized width forces designers to size the pull-down device either to W or 2W, where W is the width of the pull-up and access devices. This is shown again in Fig. 1 where Intel has published two such cells: High Density Cell

(HDC) with 1-fin NMOS pull-down and Low Voltage Cell (LVC) with 2-fin NMOS pull-down. For each cell architecture choice, we have a different design tradeoff. A cell with smaller pull-down devices will have compromised read and retention margins, but can operate at higher frequency because of reduced cell write time. On the other hand, with larger pull-down devices, the cell will operate at lower supply voltage, but will be slower and larger.

In combating reduced stability and reduced access times, there have been examinations of various assist techniques and their design tradeoffs in FinFET to improve SRAM stability mechanisms [2–5]. The common techniques include wordline under-drive for read assist [2], negative bitline write assist [3] and modulating the cell supply voltage [4]. Extra circuitry will add overhead, but is necessary to improve the overall yield and the cell retention of the SRAM array in modern processes. Although [2–4] have demonstrated the effectiveness of a few assist techniques in 6T FinFET SRAM cell, they use static noise margins derived from DC operating points of the cell as the metrics used to define cell stability during different operations and therefore fail to capture the dynamics of switching cells in the actual SRAM array. Furthermore, an extensive analysis of assist techniques for FinFET and its effect on optimal sizing and variability is truly lacking. In order to advance the tri-gate technology, all of these issues must be addressed.

Therefore, in this paper, we define and use dynamic margin as the metrics for unassisted 6T FinFET-based SRAM cell stability. This will offer some insight into the unassisted performance of inherently write-stable or read-stable cells. Then, we propose and study a number of different SRAM assist techniques and assess their impact on the cell stability by computing the improved dynamic margins. Finally, we present a compact model of variation in FinFET SRAM cell and investigate its effect on cell stability.

II. DYNAMIC MARGIN

SRAM cell stability is mainly characterized by four failure mechanisms: retention stability, readability, read stability, and write-ability. Retention stability measures the ability of the cell to retain or hold its internal node values when the word- line is de-activated. This metric can be used to extract the

Analysis of 6T FinFET SRAM Assist Techniques and Variability

Dongjin Seo and Filip Maksimovic

Department of Electrical Engineering, University of California, Berkeley Email: djseo@eecs.berkeley.edu, fil@eecs.berkeley.edu

R

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(a) (b) (c)

Fig. 1 FinFET-based SRAM cell array published by [1]. High Density Cell (a) uses one-fin for pull-down NMOS sizing while the Low Voltage Cell (b) uses two-fins for pull-down NMOS sizing. This shows an inherent tradeoff between cell density and cell stability. (c) shows the SRAM cell array. [1] Dynamic Retention Voltage (DRV), defined as the minimum supply voltage a cell can sustain until leakage paths through the gates causes the cell to lose its internal node value. Readability is defined as the ability of the cell to discharge the bitline to trigger the column sense amplifier. This is directly related to the cell’s read current. Read stability, on the other hand, is defined as the fight between the two sides of the 6T SRAM cell under read stress. In other words, it is a metric that quantifies the condition in which the cell accidentally writes and change contents of the internal node during a read operation. Finally, write-ability quantifies the contention between PMOS pull-up transistor and the NMOS access transistor to flip the internal node voltage during a write.

The conventional way of quantifying the cell stability is through static noise margins (SNMs) [6]. For both retention stability and read stability, the DC voltage transfer curve of a half-cell and its inverse when both bitlines are precharged to VDD is plotted and the SNM is defined as the side of the largest square that can be inserted between the two curves. The write-ability SNM is measured the same way when one bit line is discharged. There are other methods, such as examining the read current and plotting the N-curve as the test of read stability or write current and plotting its N-curve as the way of measuring write-ability. Based on the quantities measured over a large sample or obtained via Monte Carlo simulation, designers can approximate each failure mechanism with a Gaussian distribution.

However, SNMs are obtained assuming a DC operating conditions of the SRAM cells. Therefore, it cannot capture the nonlinear dynamics of the SRAM cell in real read and write operation with finite duration pulses. Write margin is optimistic and read margin is pessimistic compared to actual cell operation. Therefore, dynamic stability, which incorporates both the amplitude and the duration of these pulses, is more desirable and serves as the better indication of the cell failure probabilities [7, 8].

There are several definitions to quantify the dynamic read and write margin. For example, [9] defines the write dynamic margin as the time it takes for the precharged node to cross the

trip voltage of the inverter while [7] defines it as the time it takes for the precharged node to fully discharge. Although this is a subtle difference in the definition, the former by definition will underestimate dynamic write failure while the latter will overestimate the write failure probability.

In this work, we use two metrics for cell performance: read access time (readability) and write stability. We define write stability, TDW, as the wordline pulse width required to change the cell state within 200ps to allow the SRAM array to operate at 5GHz – similar to [8]. Fig. 3 shows a successful write (internal node voltages flip) and an unsuccessful write. The readability, TDR, is the minimum pulse width needed for the bitlines to differ by 100mV, a difference that can be resolved by a standard sense amplifier design [7, 8]. Fig. 4 illustrates this. Notice that there is very little variation in the bitline voltages after the wordline turns off. This is because in the transistor models we used, the leakage current for minimum sized devices is on the order of nA – too small to change the voltage on the bitline capacitors over this time period.

Fig. 3. Write Success (top) and Failure (bottom)

Fig. 4. Dynamic Read Success and Failure

Fig. 2. A conventional 6T SRAM cell

vl vr

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III. A MODEL OF VARIATION

The yield of FinFET SRAM cell is limited by both local and global variation in the device parameters. Local variations of individual transistors within the SRAM cell are uncorrelated while global variations of cell transistors are fully correlated. Generally, a series of Monte Carlo simulations computes a statistical distribution of design metrics. However, this approach is computationally intensive because it relies on random sampling of points in order to accurately capture the full statistics. Therefore, in this section, we propose a model of variability in the FinFET SRAM.

In our model, we consider three major sources of variation: random dopant fluctuation (RDF), channel length !, and fin thickness !!"#. We assume that the number of dopants in the channel follows a Poisson distribution. Therefore, the standard deviation of doping concentration due to RDF is [10],

!!!! =!!!

!!!"#!!"#

where !!! is the doping concentration of the channel. Notice

that variance actually decreases with a more lightly doped channel because of the smaller number of charges affecting the threshold voltage. !!"# is the height of the cell and is fixed to be 30nm by the process. The corresponding change in !!! is approximately,

∆!!! =!!!"#∆!!!2!!"

Therefore, despite using minimum feature size (! = 30nm, !!"# = 15nm), Δ!!! ≈ 0.5mV, which is negligible compared to threshold variations caused by short-channel effects when varying the L and !!"#, as demonstrated by the following equations [10]:

∆!!! =−0.5 ∙ !"#0

cosh   !"#1 ∙ !!∙ !!" − !! +  

−0.5 ∙ !"#0

cosh !"#$ ∙ !!∙ !!"

In the equation, ! is a function of Tfin, and DVT0, ETA0, DVT1, and DSUB are fitting parameters. When applying transistor parameter variations, experimental results indicate roughly 14% variation of the nominal value for a 3! variation

Fig. 5. Simulation of read (left) and write (right) dynamic stability for 1-fin pull-down NMOS. For compactness, minimal feature size (both L and

TFIN) for access and pull-up device is desired at the expense of reducing read and write margin by 60% and 20%, respectively.

Fig. 6. Simulation of read (left) and write (right) dynamic stability for 2-fin pull-down NMOS. With minimal feature size, read and write margin

is reduced by 50% and 20% respectively.

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AXTFIN

PDTFINPUTFIN

AXL

PDLPUL

+/- 5% +/- 10% +/- 15% +/- 5% +/- 10% +/- 15%1-Fin PD 2-Fin PD

0.3/-0.40

-1.8/2.1-0.4/0.5

0.9/-1.0 1.4/-1.7

Read Access Time

-0.2/0.4

-3.8/4.0 -5.6/5.9-0.9/0.9 -1.5/1.6

0.2/-0.4

-1.8/1.6-0.2/0.3

0.8/-0.9 1.1/-1.3-0.1/0.0

-3.5/3.6 -4.9/5.1-0.7/0.7 -0.9/0.9

000

00

00 00

0 0 0 0 00

AXTFIN

PDTFINPUTFIN

AXL

PDLPUL

+/- 5% +/- 10% +/- 15% +/- 5% +/- 10% +/- 15%1-Fin PD 2-Fin PD

0.2/-0.1

-2.6/2.5-0.1/0.1-0.5/0.6

0.3/-0.3 0.5/-0.5

Dynamic Write Margin

-5.4/5.0 -9.0/7.6-0.2/0.2 -0.2/0.2-2.1/1.9 -3.4/2.8

-1.2/1.6-0.1/0.1-0.2/0.2

0.1/-0.1 0.2/-0.1

-2.9/3.1 -4.7/4.8-0.1/0.2 -0.2/0.2-0.8/0.7 -1.2/1.3

0 0 0 0 000 0 0 0 00

0

Table 1. Percentage change in RAT (top) and DWN (bottom) sensitivity to variation in transistor parameters.

1-Fin2-Fin

µ σ Read Access Time Dynamic Write Margin

51psσ/µ µ σ σ/µ

43ps5ps3.6ps

9.3%8.4%

83ps81ps*

8.7ps 10.5%6.8ps* 8.4%*

Table 2. Mean and standard deviation of RAT and DWM. [10]. All transistor L and Tfin distributions are assumed to be independent to simplify the variability analysis.

IV. SIMULATION RESULTS

The analysis of 32x32 FinFET SRAM array is carried out using BSIM-CMG, a Verilog-A based model card developed by BSIM group at UC Berkeley that models the electrical characteristics of multi-gate structures [11]. In particular, it is more advantageous over the BSIM model as it predicts scalability and variability of various parameters specific to FinFET geometry, such as fin height and fin thickness. Throughout the paper, we compare the performance of SRAM array with 1-fin and 2-fin pull-down NMOS. Also, as in a conventional SRAM array, the cells in a row share common cell VDD and wordline, and cells in a column share bitlines.

A. Read and Write stability Tradeoff

Fig. 5 and Fig. 6 demonstrate the effect of varying FinFET parameters on read and write dynamic stability of 1-fin and 2-fin SRAM cell, respectively. For both cells, we observe that read stability is enhanced by weakening the access transistor drive strength, by increasing its channel length and decreasing fin thickness, while the write stability is improved by strengthening the access transistor relative to pull-up PMOS. By choosing minimal feature size for all transistors, read and write margin is reduced by approximately 60% and 20% and 50% and 20% for 1-fin and 2-fin cell, respectively.

B. Sensitivity to Variations To observe the impact of local variations on dynamic cell

operation, transistor pair !!! was varied by modifying the transistor length and fin thickness as mentioned in Section III. The results of these calculations are summarized in Table 1 for

Read Access Time (RAT) and Dynamic Write Margin (DWM).

It is apparent that for both read and write, the variation in length (and to a lesser extent, the fin thickness) of the access transistor is the primary source of variation in the 6T FinFET SRAM. This is to be expected because of the access transistor’s role in passing current in or out of the cell during a read or write. For the speed of a read operation, variations in pull-down threshold are also significant because it is the transistor that effectively pulls down the voltage of the floating bit line capacitor. The write margin is sensitive to pull-up transistor strength because a write operation essentially amounts to a drive fight between the access transistor and the pull-up device. If the pull-up device is stronger than the access transistor, it will be more difficult to write into the cell.

C. Variation Distribution The 14% 3! variation proposed in Section III can be applied

while measuring dynamic margins outlined in Section II. The results of these simulations are summarized in Fig. 9 and Fig. 10. In addition, the means and standard deviations of the stability criteria for the nominal transistor parameters are summarized in Table 2.

Fig. 7. 2-Fin SRAM array operating at 5GHz does not exhibit normal distribution due to overpowering pull-down NMOS drive strength. By reducing the operation frequency (to 4GHz), DWM can be reduced by approximately 38.6% and shows Gaussian distribution around the mean.

Fig. 8. Bitline suppression for read assist becomes effective once the access transistor is operating in triode region.

40 60 80 100 120 140 160

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

Dynamic Write Margin [ps]

PDF

Simulated - 250psNorm PDF FitSimulated - 200psNorm PDF Fit

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.75

0.8

0.85

0.9

0.95

1

1.05

1.1

BL/BLB Voltage (V)

Nor

mal

ized

Rea

d Ac

cess

Tim

e

NFIN=1NFIN=2

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Note that in Fig. 7, the normal distribution does not fit the DWM simulated data well for 2-fin SRAM cell. This is not necessarily expected because the sensitivities of the static margins to individual transistor variations up to 3! are relatively linear, and we assume no correlation. This deviation occurs because with 2-fins, the strength of the pull-down NMOS transistors is overwhelming regardless of sensitivity that the cell cannot possibly be written to in the required 200ps. To demonstrate this, the cell is operated at 4GHz (250ps requirement), where the distribution once again fits to a normal nicely. These results are shown in Table 2. For the purpose of comparison, the nominal WDNM for a 2-fin pull-down cell is 132ps. Variance is ill-defined because the distribution is not strictly normal.

V. EFFECTS OF ASSIST TECHNIQUES

Due to the quantized fin widths for the pull-down transistors, there is a fundamental and non-beneficial tradeoff between read margin and write margin. In the 1-fin cell, the read access time is longer, but the more limiting write stability is shorter, allowing the cell to run faster. Contrarily, in the 2-fin cell, the read access time is shorter and the cell can retain at a lower voltage. But in the presence of variability it must operate at a significantly lower frequency. Either cell design can be used, but will require assist techniques to compensate for its drawbacks.

A. Negative Bitline Assist

One technique for improving cell stability, demonstrated in 32nm SOI arrays in [3], is a technique that can be interpreted as either write-assist or read-assist. Because other techniques examined improve write stability, only the effects of the read assist will be shown. During a read, the bitlines can be charged to a suppressed voltage below VCELL, weakening the access transistors and improving read stability. Additionally, a negative bitline during a write would have a similar effect to lowering the VCELL. It strengthens the access transistors.

However, [2, 3] suggests that in a tri-gate technology, bitline suppression for read stability is not effective (due to short-channel effects) unless the access transistors are forced to operate in the triode region. This is confirmed in Fig. 8 where a significant improvement in RAT is not observed until the access transistor is in the triode region. For a 10% reduction in RAT, a bitline voltage of 0.455V was needed for the 1-fin pull-down cell. This reduced the access time to 45.8ps with a standard deviation of approximately 4.5ps, 9.8% of the mean as shown in Fig. 9. For the 2-fin pull-down cell, the bitline voltage was 0.365V. This reduced access time to a nominal 38.61ps with a standard deviation of 3.4ps, 8.9% of the mean as shown in Fig. 9.

B. VDD Collapse An alternative technique for improving cell read and write

stability is to modulate the cell supply voltage. For instance,

Fig. 9. Gaussian distribution RAT for 1-fin (left) and 2-fins (right). The bitline voltages are chosen to give 10% improvement in the RAT.

Fig. 10. Gaussian distribution of DWM for 1-fin (left) and 2-fins (right). Both delayed WL boost and VDD collapse significantly reduces DWM.

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during a write operation, reducing VCELL makes it easier to write to the cell because the access transistor can more effectively overpower the internal positive feedback in the cell. This is demonstrated in [2] with minimum sized pull-down devices. However, because VDD is shared in a column, unselected cells will be subject to additional retention stress. This would suggest that larger pull-down devices would be more practical because they improve the retention margin of a cell. However, in [2], the authors demonstrate a scheme where the cell voltage is pulled below the cell VMIN dynamically to greatly improve write-ability of the targeted cell while retaining bits in unselected cells. This technique was applied to both the 1-fin pull-down and 2-fin pull-down arrays. The cell voltage was dropped to 50mV (less than static VMIN) for 16ps. For the 1-fin cell, the write margin improved to 72ps, a 13.5% improvement over the unassisted. For the 2-fin cell, it improved to 80ps, a 39.3% improvement. In an actual array, the stability of half selected cells would be comprised, although we were unable to observe this effect to working precision in our simulation.

Notice in Fig. 10, the variation in the assisted cell write stabilities goes down significantly. This is because the effect of variations in the PU and PD transistor is minimal, and is more dependent on the deterministic magnitude and duration of the cell voltage collapse.

C. Delayed Wordline Boost By increasing the wordline voltage above the cell voltage during a write, the write stability is improved [9]. However, This places half-selected cells under additional read stress. A delayed wordline boost, where the wordline voltage is raised for only the end of the wordline pulse, can be used to improve writeability. In addition, half-cell retention is not compromised because by the time the pulse that strengthens the access transistors occurs, the bitline will have discharged. Using a boost at the end of the wordline pulse with a magnitude of 20% of VDD and duration of 16ps, the TWRITE was improved to 78ps for a 1-fin cell (6% improvement) and to 95ps for a 2-fin cell (28% improvement) as shown in Fig. 10. The performance improvement is summarized in Table 3. Also, as demonstrated in [12], in-situ monitoring of read/write margins during run-time can be implemented for enhanced SRAM operation.

VI. CONCLUSION

Continued scaling of the SRAM cell is essential in lowering the power, area, and cost overhead of the modern integrated systems. In particular, design tradeoffs in FinFET-based SRAM cell array are vastly different and the accurate method

of measuring the stability of the cell is imperative. In this work, we assessed the design trade-offs of using assist techniques to compensate for quantized pull-down transistor widths in 6T SRAM in the presence of variability. When using a nominally read stable 2-fin pull-down SRAM cell, the dynamic write margin was reduced by 39.3% when using a VDD collapse technique, and 28% when using a delayed wordline boost. Similarly, the nominally write stable SRAM cell had a read access time improvement of 10% when using a reduced bitline voltage. Despite its shortcomings, FinFET SRAM, combined with appropriate assist techniques, can drive technology scaling in memory arrays in a variety of applications in the sub-32 nm regime.

ACKNOWLEDGMENT The authors would like to acknowledge Sriramkumar

Venugopalan and the BSIM group at UC Berkeley, for providing preliminary FinFET models.

REFERENCES [1] Hisamoto, D., et al., “FinFET – A Self-Aligned Double-Gate MOSFET

Scalable to 20nm,” IEEE Trans. Elec. Devices, vol. 47, No. 12, pp. 2320-2325, Dec. 2000.

[2] Karl, E., et al., “A 4.6 GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active Vmin-Enhancing Assist Circuitry,” ISSCC, pp. 230-231, Feb. 2012.

[3] Pilo, H., et.al., “A 64Mb SRAM in 32nm high-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancement”, IEEE International Solid State Circuits Conference Dig. Tech. Papers, pp.254-256, Feb. 2011.

[4] Carlson, A., et al., “SRAM Read/Write Margin Enhancements Using FinFETs,” VSLI, vol. 18, issue: 6, pp. 887-900, May 2010.

[5] Fan, Ming-Long et al., “Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach,” Transactions on Electronic Devices, vol. 58, issue: 3, pp. 609-616, Feb. 2011.

[6] Seevinck, E., et. al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. 22, NO. 5., Oct. 1987.

[7] Vatajelu, E.I., Gomez-Pau, A., Renovell, M., Figueras, J.; “Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric,” Test Symposium (ATS), 2011 20th Asian, pp.413-418, Nov.2011.

[8] Khalil, D., et. al., “Accurate Estimation of SRAM Dynamic Stability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 12, pp. 1639 – 1647, Dec. 2008.

[9] S. Mukhopadhyay, et al. “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE TCADICS, 24(12):1859-1880, Dec 2005

[10] D. D. Lu, et al. “Compact Modeling of Variation in FinFET SRAM Cells,” IEEE Design of Test of Computers, pp.44-50, Apr. 2010.

[11] Venugopalan, S., et al., “Multi-Gate MOSFET Compact Model: Technical Manual,” BSIM Group at University of California, Berkeley, 2012.

[12] Chen, Y., et. al, "Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40nm Fully Functional Embedded SRAM," IEEE JSSC, pp.969-980, Apr. 2012.

Table 3. Performance summary of 1-fin and 2-fin 1kbit SRAM array. Assist techniques for both RAT and DWM were used to improve the margin by 10% and 40% respectively.